#define DMA1_Channel2_IRQn DMA1_Stream1_IRQn
#define DMA1_Channel3_IRQn DMA1_Stream2_IRQn
#define DMA1_Channel4_IRQn DMA1_Stream3_IRQn
#define DMA1_Channel5_IRQn DMA1_Stream4_IRQn
#define DMA1_Channel6_IRQn DMA1_Stream5_IRQn
#define DMA1_Channel7_IRQn DMA1_Stream6_IRQn
#define DMA1_Channel8_IRQn DMA1_Stream7_IRQn
#define DMA2_Channel1_IRQn DMA2_Stream0_IRQn
#define DMA2_Channel2_IRQn DMA2_Stream1_IRQn
#define DMA2_Channel3_IRQn DMA2_Stream2_IRQn
#define DMA2_Channel4_IRQn DMA2_Stream3_IRQn
#define DMA2_Channel5_IRQn DMA2_Stream4_IRQn
#define DMA2_Channel6_IRQn DMA2_Stream5_IRQn
#define DMA2_Channel7_IRQn DMA2_Stream6_IRQn
#define DMA2_Channel8_IRQn DMA2_Stream7_IRQn
#define DMA_MINC DMA_SxCR_MINC