File nut/include/arch/cm3/stm/stm32f2xx.h

Cortex-M3 Processor Exceptions Numbers


Included Files

* @}


Preprocessor definitions

@addtogroup stm32f2xx * @{

#define __STM32F2xx_H

@addtogroup Library_configuration_section * @{

#define STM32F2XX

* @brief In the following line adjust the value of External High Speed oscillator (HSE) used in your application
Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor.

#define HSE_VALUE

* @brief In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value

#define HSE_STARTUP_TIMEOUT

#define HSI_VALUE

* @brief STM32F2Xxx Standard Peripherals Library version number V1.0.0

#define __STM32F2XX_STDPERIPH_VERSION_MAIN 0x01

#define __STM32F2XX_STDPERIPH_VERSION_SUB1 0x00

#define __STM32F2XX_STDPERIPH_VERSION_SUB2 0x00

#define __STM32F2XX_STDPERIPH_VERSION_RC 0x00

#define __STM32F2XX_STDPERIPH_VERSION

* @brief Configuration of the Cortex-M3 Processor and Core Peripherals

#define __MPU_PRESENT 1

#define __NVIC_PRIO_BITS 4

#define __Vendor_SysTickConfig 0

#define IS_FUNCTIONAL_STATE( STATE )

@addtogroup Peripheral_memory_map * @{

#define FLASH_BASE

#define SRAM_BASE

#define PERIPH_BASE

#define SRAM_BB_BASE

#define PERIPH_BB_BASE

#define FSMC_R_BASE

#define APB1PERIPH_BASE PERIPH_BASE

#define APB2PERIPH_BASE

#define AHB1PERIPH_BASE

#define AHB2PERIPH_BASE

#define TIM2_BASE

#define TIM3_BASE

#define TIM4_BASE

#define TIM5_BASE

#define TIM6_BASE

#define TIM7_BASE

#define TIM12_BASE

#define TIM13_BASE

#define TIM14_BASE

#define RTC_BASE

#define WWDG_BASE

#define IWDG_BASE

#define SPI2_BASE

#define SPI3_BASE

#define USART2_BASE

#define USART3_BASE

#define UART4_BASE

#define UART5_BASE

#define I2C1_BASE

#define I2C2_BASE

#define I2C3_BASE

#define CAN1_BASE

#define CAN2_BASE

#define PWR_BASE

#define DAC_BASE

#define TIM1_BASE

#define TIM8_BASE

#define USART1_BASE

#define USART6_BASE

#define ADC1_BASE

#define ADC2_BASE

#define ADC3_BASE

#define ADC_BASE

#define SDIO_BASE

#define SPI1_BASE

#define SYSCFG_BASE

#define EXTI_BASE

#define TIM9_BASE

#define TIM10_BASE

#define TIM11_BASE

#define GPIOA_BASE

#define GPIOB_BASE

#define GPIOC_BASE

#define GPIOD_BASE

#define GPIOE_BASE

#define GPIOF_BASE

#define GPIOG_BASE

#define GPIOH_BASE

#define GPIOI_BASE

#define CRC_BASE

#define RCC_BASE

#define FLASH_R_BASE

#define BKPSRAM_BASE

#define DMA1_BASE

#define DMA1_Stream0_BASE

#define DMA1_Stream1_BASE

#define DMA1_Stream2_BASE

#define DMA1_Stream3_BASE

#define DMA1_Stream4_BASE

#define DMA1_Stream5_BASE

#define DMA1_Stream6_BASE

#define DMA1_Stream7_BASE

#define DMA2_BASE

#define DMA2_Stream0_BASE

#define DMA2_Stream1_BASE

#define DMA2_Stream2_BASE

#define DMA2_Stream3_BASE

#define DMA2_Stream4_BASE

#define DMA2_Stream5_BASE

#define DMA2_Stream6_BASE

#define DMA2_Stream7_BASE

#define ETH_BASE

#define ETH_MAC_BASE ETH_BASE

#define ETH_MMC_BASE

#define ETH_PTP_BASE

#define ETH_DMA_BASE

#define DCMI_BASE

#define CRYP_BASE

#define HASH_BASE

#define RNG_BASE

#define FSMC_Bank1_R_BASE

#define FSMC_Bank1E_R_BASE

#define FSMC_Bank2_R_BASE

#define FSMC_Bank3_R_BASE

#define FSMC_Bank4_R_BASE

#define DBGMCU_BASE

@addtogroup Peripheral_declaration * @{

#define TIM2

#define TIM3

#define TIM4

#define TIM5

#define TIM6

#define TIM7

#define TIM12

#define TIM13

#define TIM14

#define RTC

#define WWDG

#define IWDG

#define SPI2

#define SPI3

#define USART2

#define USART3

#define UART4

#define UART5

#define I2C1

#define I2C2

#define I2C3

#define CAN1

#define CAN2

#define PWR

#define DAC

#define TIM1

#define TIM8

#define USART1

#define USART6

#define ADC

#define ADC1

#define ADC2

#define ADC3

#define SDIO

#define SPI1

#define SYSCFG

#define EXTI

#define TIM9

#define TIM10

#define TIM11

#define GPIOA

#define GPIOB

#define GPIOC

#define GPIOD

#define GPIOE

#define GPIOF

#define GPIOG

#define GPIOH

#define GPIOI

#define CRC

#define RCC

#define FLASH

#define DMA1

#define DMA1_Stream0

#define DMA1_Stream1

#define DMA1_Stream2

#define DMA1_Stream3

#define DMA1_Stream4

#define DMA1_Stream5

#define DMA1_Stream6

#define DMA1_Stream7

#define DMA2

#define DMA2_Stream0

#define DMA2_Stream1

#define DMA2_Stream2

#define DMA2_Stream3

#define DMA2_Stream4

#define DMA2_Stream5

#define DMA2_Stream6

#define DMA2_Stream7

#define ETH

#define DCMI

#define CRYP

#define HASH

#define RNG

#define FSMC_Bank1

#define FSMC_Bank1E

#define FSMC_Bank2

#define FSMC_Bank3

#define FSMC_Bank4

#define DBGMCU

#define ADC_SR_AWD

#define ADC_SR_EOC

#define ADC_SR_JEOC

#define ADC_SR_JSTRT

#define ADC_SR_STRT

#define ADC_SR_OVR

#define ADC_CR1_AWDCH

#define ADC_CR1_AWDCH_0

#define ADC_CR1_AWDCH_1

#define ADC_CR1_AWDCH_2

#define ADC_CR1_AWDCH_3

#define ADC_CR1_AWDCH_4

#define ADC_CR1_EOCIE

#define ADC_CR1_AWDIE

#define ADC_CR1_JEOCIE

#define ADC_CR1_SCAN

#define ADC_CR1_AWDSGL

#define ADC_CR1_JAUTO

#define ADC_CR1_DISCEN

#define ADC_CR1_JDISCEN

#define ADC_CR1_DISCNUM

#define ADC_CR1_DISCNUM_0

#define ADC_CR1_DISCNUM_1

#define ADC_CR1_DISCNUM_2

#define ADC_CR1_JAWDEN

#define ADC_CR1_AWDEN

#define ADC_CR1_RES

#define ADC_CR1_RES_0

#define ADC_CR1_RES_1

#define ADC_CR1_OVRIE

#define ADC_CR2_ADON

#define ADC_CR2_CONT

#define ADC_CR2_DMA

#define ADC_CR2_DDS

#define ADC_CR2_EOCS

#define ADC_CR2_ALIGN

#define ADC_CR2_JEXTSEL

#define ADC_CR2_JEXTSEL_0

#define ADC_CR2_JEXTSEL_1

#define ADC_CR2_JEXTSEL_2

#define ADC_CR2_JEXTSEL_3

#define ADC_CR2_JEXTEN

#define ADC_CR2_JEXTEN_0

#define ADC_CR2_JEXTEN_1

#define ADC_CR2_JSWSTART

#define ADC_CR2_EXTSEL

#define ADC_CR2_EXTSEL_0

#define ADC_CR2_EXTSEL_1

#define ADC_CR2_EXTSEL_2

#define ADC_CR2_EXTSEL_3

#define ADC_CR2_EXTEN

#define ADC_CR2_EXTEN_0

#define ADC_CR2_EXTEN_1

#define ADC_CR2_SWSTART

#define ADC_SMPR1_SMP10

#define ADC_SMPR1_SMP10_0

#define ADC_SMPR1_SMP10_1

#define ADC_SMPR1_SMP10_2

#define ADC_SMPR1_SMP11

#define ADC_SMPR1_SMP11_0

#define ADC_SMPR1_SMP11_1

#define ADC_SMPR1_SMP11_2

#define ADC_SMPR1_SMP12

#define ADC_SMPR1_SMP12_0

#define ADC_SMPR1_SMP12_1

#define ADC_SMPR1_SMP12_2

#define ADC_SMPR1_SMP13

#define ADC_SMPR1_SMP13_0

#define ADC_SMPR1_SMP13_1

#define ADC_SMPR1_SMP13_2

#define ADC_SMPR1_SMP14

#define ADC_SMPR1_SMP14_0

#define ADC_SMPR1_SMP14_1

#define ADC_SMPR1_SMP14_2

#define ADC_SMPR1_SMP15

#define ADC_SMPR1_SMP15_0

#define ADC_SMPR1_SMP15_1

#define ADC_SMPR1_SMP15_2

#define ADC_SMPR1_SMP16

#define ADC_SMPR1_SMP16_0

#define ADC_SMPR1_SMP16_1

#define ADC_SMPR1_SMP16_2

#define ADC_SMPR1_SMP17

#define ADC_SMPR1_SMP17_0

#define ADC_SMPR1_SMP17_1

#define ADC_SMPR1_SMP17_2

#define ADC_SMPR1_SMP18

#define ADC_SMPR1_SMP18_0

#define ADC_SMPR1_SMP18_1

#define ADC_SMPR1_SMP18_2

#define ADC_SMPR2_SMP0

#define ADC_SMPR2_SMP0_0

#define ADC_SMPR2_SMP0_1

#define ADC_SMPR2_SMP0_2

#define ADC_SMPR2_SMP1

#define ADC_SMPR2_SMP1_0

#define ADC_SMPR2_SMP1_1

#define ADC_SMPR2_SMP1_2

#define ADC_SMPR2_SMP2

#define ADC_SMPR2_SMP2_0

#define ADC_SMPR2_SMP2_1

#define ADC_SMPR2_SMP2_2

#define ADC_SMPR2_SMP3

#define ADC_SMPR2_SMP3_0

#define ADC_SMPR2_SMP3_1

#define ADC_SMPR2_SMP3_2

#define ADC_SMPR2_SMP4

#define ADC_SMPR2_SMP4_0

#define ADC_SMPR2_SMP4_1

#define ADC_SMPR2_SMP4_2

#define ADC_SMPR2_SMP5

#define ADC_SMPR2_SMP5_0

#define ADC_SMPR2_SMP5_1

#define ADC_SMPR2_SMP5_2

#define ADC_SMPR2_SMP6

#define ADC_SMPR2_SMP6_0

#define ADC_SMPR2_SMP6_1

#define ADC_SMPR2_SMP6_2

#define ADC_SMPR2_SMP7

#define ADC_SMPR2_SMP7_0

#define ADC_SMPR2_SMP7_1

#define ADC_SMPR2_SMP7_2

#define ADC_SMPR2_SMP8

#define ADC_SMPR2_SMP8_0

#define ADC_SMPR2_SMP8_1

#define ADC_SMPR2_SMP8_2

#define ADC_SMPR2_SMP9

#define ADC_SMPR2_SMP9_0

#define ADC_SMPR2_SMP9_1

#define ADC_SMPR2_SMP9_2

#define ADC_JOFR1_JOFFSET1

#define ADC_JOFR2_JOFFSET2

#define ADC_JOFR3_JOFFSET3

#define ADC_JOFR4_JOFFSET4

#define ADC_HTR_HT

#define ADC_LTR_LT

#define ADC_SQR1_SQ13

#define ADC_SQR1_SQ13_0

#define ADC_SQR1_SQ13_1

#define ADC_SQR1_SQ13_2

#define ADC_SQR1_SQ13_3

#define ADC_SQR1_SQ13_4

#define ADC_SQR1_SQ14

#define ADC_SQR1_SQ14_0

#define ADC_SQR1_SQ14_1

#define ADC_SQR1_SQ14_2

#define ADC_SQR1_SQ14_3

#define ADC_SQR1_SQ14_4

#define ADC_SQR1_SQ15

#define ADC_SQR1_SQ15_0

#define ADC_SQR1_SQ15_1

#define ADC_SQR1_SQ15_2

#define ADC_SQR1_SQ15_3

#define ADC_SQR1_SQ15_4

#define ADC_SQR1_SQ16

#define ADC_SQR1_SQ16_0

#define ADC_SQR1_SQ16_1

#define ADC_SQR1_SQ16_2

#define ADC_SQR1_SQ16_3

#define ADC_SQR1_SQ16_4

#define ADC_SQR1_L

#define ADC_SQR1_L_0

#define ADC_SQR1_L_1

#define ADC_SQR1_L_2

#define ADC_SQR1_L_3

#define ADC_SQR2_SQ7

#define ADC_SQR2_SQ7_0

#define ADC_SQR2_SQ7_1

#define ADC_SQR2_SQ7_2

#define ADC_SQR2_SQ7_3

#define ADC_SQR2_SQ7_4

#define ADC_SQR2_SQ8

#define ADC_SQR2_SQ8_0

#define ADC_SQR2_SQ8_1

#define ADC_SQR2_SQ8_2

#define ADC_SQR2_SQ8_3

#define ADC_SQR2_SQ8_4

#define ADC_SQR2_SQ9

#define ADC_SQR2_SQ9_0

#define ADC_SQR2_SQ9_1

#define ADC_SQR2_SQ9_2

#define ADC_SQR2_SQ9_3

#define ADC_SQR2_SQ9_4

#define ADC_SQR2_SQ10

#define ADC_SQR2_SQ10_0

#define ADC_SQR2_SQ10_1

#define ADC_SQR2_SQ10_2

#define ADC_SQR2_SQ10_3

#define ADC_SQR2_SQ10_4

#define ADC_SQR2_SQ11

#define ADC_SQR2_SQ11_0

#define ADC_SQR2_SQ11_1

#define ADC_SQR2_SQ11_2

#define ADC_SQR2_SQ11_3

#define ADC_SQR2_SQ11_4

#define ADC_SQR2_SQ12

#define ADC_SQR2_SQ12_0

#define ADC_SQR2_SQ12_1

#define ADC_SQR2_SQ12_2

#define ADC_SQR2_SQ12_3

#define ADC_SQR2_SQ12_4

#define ADC_SQR3_SQ1

#define ADC_SQR3_SQ1_0

#define ADC_SQR3_SQ1_1

#define ADC_SQR3_SQ1_2

#define ADC_SQR3_SQ1_3

#define ADC_SQR3_SQ1_4

#define ADC_SQR3_SQ2

#define ADC_SQR3_SQ2_0

#define ADC_SQR3_SQ2_1

#define ADC_SQR3_SQ2_2

#define ADC_SQR3_SQ2_3

#define ADC_SQR3_SQ2_4

#define ADC_SQR3_SQ3

#define ADC_SQR3_SQ3_0

#define ADC_SQR3_SQ3_1

#define ADC_SQR3_SQ3_2

#define ADC_SQR3_SQ3_3

#define ADC_SQR3_SQ3_4

#define ADC_SQR3_SQ4

#define ADC_SQR3_SQ4_0

#define ADC_SQR3_SQ4_1

#define ADC_SQR3_SQ4_2

#define ADC_SQR3_SQ4_3

#define ADC_SQR3_SQ4_4

#define ADC_SQR3_SQ5

#define ADC_SQR3_SQ5_0

#define ADC_SQR3_SQ5_1

#define ADC_SQR3_SQ5_2

#define ADC_SQR3_SQ5_3

#define ADC_SQR3_SQ5_4

#define ADC_SQR3_SQ6

#define ADC_SQR3_SQ6_0

#define ADC_SQR3_SQ6_1

#define ADC_SQR3_SQ6_2

#define ADC_SQR3_SQ6_3

#define ADC_SQR3_SQ6_4

#define ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_4

#define ADC_JSQR_JL

#define ADC_JSQR_JL_0

#define ADC_JSQR_JL_1

#define ADC_JDR1_JDATA

#define ADC_JDR2_JDATA

#define ADC_JDR3_JDATA

#define ADC_JDR4_JDATA

#define ADC_DR_DATA

#define ADC_DR_ADC2DATA

#define ADC_CSR_AWD1

#define ADC_CSR_EOC1

#define ADC_CSR_JEOC1

#define ADC_CSR_JSTRT1

#define ADC_CSR_STRT1

#define ADC_CSR_DOVR1

#define ADC_CSR_AWD2

#define ADC_CSR_EOC2

#define ADC_CSR_JEOC2

#define ADC_CSR_JSTRT2

#define ADC_CSR_STRT2

#define ADC_CSR_DOVR2

#define ADC_CSR_AWD3

#define ADC_CSR_EOC3

#define ADC_CSR_JEOC3

#define ADC_CSR_JSTRT3

#define ADC_CSR_STRT3

#define ADC_CSR_DOVR3

#define ADC_CCR_MULTI

#define ADC_CCR_MULTI_0

#define ADC_CCR_MULTI_1

#define ADC_CCR_MULTI_2

#define ADC_CCR_MULTI_3

#define ADC_CCR_MULTI_4

#define ADC_CCR_DELAY

#define ADC_CCR_DELAY_0

#define ADC_CCR_DELAY_1

#define ADC_CCR_DELAY_2

#define ADC_CCR_DELAY_3

#define ADC_CCR_DDS

#define ADC_CCR_DMA

#define ADC_CCR_DMA_0

#define ADC_CCR_DMA_1

#define ADC_CCR_ADCPRE

#define ADC_CCR_ADCPRE_0

#define ADC_CCR_ADCPRE_1

#define ADC_CCR_VBATE

#define ADC_CCR_TSVREFE

#define ADC_CDR_DATA1

#define ADC_CDR_DATA2

#define CAN_MCR_INRQ

#define CAN_MCR_SLEEP

#define CAN_MCR_TXFP

#define CAN_MCR_RFLM

#define CAN_MCR_NART

#define CAN_MCR_AWUM

#define CAN_MCR_ABOM

#define CAN_MCR_TTCM

#define CAN_MCR_RESET

#define CAN_MSR_INAK

#define CAN_MSR_SLAK

#define CAN_MSR_ERRI

#define CAN_MSR_WKUI

#define CAN_MSR_SLAKI

#define CAN_MSR_TXM

#define CAN_MSR_RXM

#define CAN_MSR_SAMP

#define CAN_MSR_RX

#define CAN_TSR_RQCP0

#define CAN_TSR_TXOK0

#define CAN_TSR_ALST0

#define CAN_TSR_TERR0

#define CAN_TSR_ABRQ0

#define CAN_TSR_RQCP1

#define CAN_TSR_TXOK1

#define CAN_TSR_ALST1

#define CAN_TSR_TERR1

#define CAN_TSR_ABRQ1

#define CAN_TSR_RQCP2

#define CAN_TSR_TXOK2

#define CAN_TSR_ALST2

#define CAN_TSR_TERR2

#define CAN_TSR_ABRQ2

#define CAN_TSR_CODE

#define CAN_TSR_TME

#define CAN_TSR_TME0

#define CAN_TSR_TME1

#define CAN_TSR_TME2

#define CAN_TSR_LOW

#define CAN_TSR_LOW0

#define CAN_TSR_LOW1

#define CAN_TSR_LOW2

#define CAN_RF0R_FMP0

#define CAN_RF0R_FULL0

#define CAN_RF0R_FOVR0

#define CAN_RF0R_RFOM0

#define CAN_RF1R_FMP1

#define CAN_RF1R_FULL1

#define CAN_RF1R_FOVR1

#define CAN_RF1R_RFOM1

#define CAN_IER_TMEIE

#define CAN_IER_FMPIE0

#define CAN_IER_FFIE0

#define CAN_IER_FOVIE0

#define CAN_IER_FMPIE1

#define CAN_IER_FFIE1

#define CAN_IER_FOVIE1

#define CAN_IER_EWGIE

#define CAN_IER_EPVIE

#define CAN_IER_BOFIE

#define CAN_IER_LECIE

#define CAN_IER_ERRIE

#define CAN_IER_WKUIE

#define CAN_IER_SLKIE

#define CAN_ESR_EWGF

#define CAN_ESR_EPVF

#define CAN_ESR_BOFF

#define CAN_ESR_LEC

#define CAN_ESR_LEC_0

#define CAN_ESR_LEC_1

#define CAN_ESR_LEC_2

#define CAN_ESR_TEC

#define CAN_ESR_REC

#define CAN_BTR_BRP

#define CAN_BTR_TS1

#define CAN_BTR_TS2

#define CAN_BTR_SJW

#define CAN_BTR_LBKM

#define CAN_BTR_SILM

#define CAN_TI0R_TXRQ

#define CAN_TI0R_RTR

#define CAN_TI0R_IDE

#define CAN_TI0R_EXID

#define CAN_TI0R_STID

#define CAN_TDT0R_DLC

#define CAN_TDT0R_TGT

#define CAN_TDT0R_TIME

#define CAN_TDL0R_DATA0

#define CAN_TDL0R_DATA1

#define CAN_TDL0R_DATA2

#define CAN_TDL0R_DATA3

#define CAN_TDH0R_DATA4

#define CAN_TDH0R_DATA5

#define CAN_TDH0R_DATA6

#define CAN_TDH0R_DATA7

#define CAN_TI1R_TXRQ

#define CAN_TI1R_RTR

#define CAN_TI1R_IDE

#define CAN_TI1R_EXID

#define CAN_TI1R_STID

#define CAN_TDT1R_DLC

#define CAN_TDT1R_TGT

#define CAN_TDT1R_TIME

#define CAN_TDL1R_DATA0

#define CAN_TDL1R_DATA1

#define CAN_TDL1R_DATA2

#define CAN_TDL1R_DATA3

#define CAN_TDH1R_DATA4

#define CAN_TDH1R_DATA5

#define CAN_TDH1R_DATA6

#define CAN_TDH1R_DATA7

#define CAN_TI2R_TXRQ

#define CAN_TI2R_RTR

#define CAN_TI2R_IDE

#define CAN_TI2R_EXID

#define CAN_TI2R_STID

#define CAN_TDT2R_DLC

#define CAN_TDT2R_TGT

#define CAN_TDT2R_TIME

#define CAN_TDL2R_DATA0

#define CAN_TDL2R_DATA1

#define CAN_TDL2R_DATA2

#define CAN_TDL2R_DATA3

#define CAN_TDH2R_DATA4

#define CAN_TDH2R_DATA5

#define CAN_TDH2R_DATA6

#define CAN_TDH2R_DATA7

#define CAN_RI0R_RTR

#define CAN_RI0R_IDE

#define CAN_RI0R_EXID

#define CAN_RI0R_STID

#define CAN_RDT0R_DLC

#define CAN_RDT0R_FMI

#define CAN_RDT0R_TIME

#define CAN_RDL0R_DATA0

#define CAN_RDL0R_DATA1

#define CAN_RDL0R_DATA2

#define CAN_RDL0R_DATA3

#define CAN_RDH0R_DATA4

#define CAN_RDH0R_DATA5

#define CAN_RDH0R_DATA6

#define CAN_RDH0R_DATA7

#define CAN_RI1R_RTR

#define CAN_RI1R_IDE

#define CAN_RI1R_EXID

#define CAN_RI1R_STID

#define CAN_RDT1R_DLC

#define CAN_RDT1R_FMI

#define CAN_RDT1R_TIME

#define CAN_RDL1R_DATA0

#define CAN_RDL1R_DATA1

#define CAN_RDL1R_DATA2

#define CAN_RDL1R_DATA3

#define CAN_RDH1R_DATA4

#define CAN_RDH1R_DATA5

#define CAN_RDH1R_DATA6

#define CAN_RDH1R_DATA7

#define CAN_FMR_FINIT

#define CAN_FM1R_FBM

#define CAN_FM1R_FBM0

#define CAN_FM1R_FBM1

#define CAN_FM1R_FBM2

#define CAN_FM1R_FBM3

#define CAN_FM1R_FBM4

#define CAN_FM1R_FBM5

#define CAN_FM1R_FBM6

#define CAN_FM1R_FBM7

#define CAN_FM1R_FBM8

#define CAN_FM1R_FBM9

#define CAN_FM1R_FBM10

#define CAN_FM1R_FBM11

#define CAN_FM1R_FBM12

#define CAN_FM1R_FBM13

#define CAN_FS1R_FSC

#define CAN_FS1R_FSC0

#define CAN_FS1R_FSC1

#define CAN_FS1R_FSC2

#define CAN_FS1R_FSC3

#define CAN_FS1R_FSC4

#define CAN_FS1R_FSC5

#define CAN_FS1R_FSC6

#define CAN_FS1R_FSC7

#define CAN_FS1R_FSC8

#define CAN_FS1R_FSC9

#define CAN_FS1R_FSC10

#define CAN_FS1R_FSC11

#define CAN_FS1R_FSC12

#define CAN_FS1R_FSC13

#define CAN_FFA1R_FFA

#define CAN_FFA1R_FFA0

#define CAN_FFA1R_FFA1

#define CAN_FFA1R_FFA2

#define CAN_FFA1R_FFA3

#define CAN_FFA1R_FFA4

#define CAN_FFA1R_FFA5

#define CAN_FFA1R_FFA6

#define CAN_FFA1R_FFA7

#define CAN_FFA1R_FFA8

#define CAN_FFA1R_FFA9

#define CAN_FFA1R_FFA10

#define CAN_FFA1R_FFA11

#define CAN_FFA1R_FFA12

#define CAN_FFA1R_FFA13

#define CAN_FA1R_FACT

#define CAN_FA1R_FACT0

#define CAN_FA1R_FACT1

#define CAN_FA1R_FACT2

#define CAN_FA1R_FACT3

#define CAN_FA1R_FACT4

#define CAN_FA1R_FACT5

#define CAN_FA1R_FACT6

#define CAN_FA1R_FACT7

#define CAN_FA1R_FACT8

#define CAN_FA1R_FACT9

#define CAN_FA1R_FACT10

#define CAN_FA1R_FACT11

#define CAN_FA1R_FACT12

#define CAN_FA1R_FACT13

#define CAN_F0R1_FB0

#define CAN_F0R1_FB1

#define CAN_F0R1_FB2

#define CAN_F0R1_FB3

#define CAN_F0R1_FB4

#define CAN_F0R1_FB5

#define CAN_F0R1_FB6

#define CAN_F0R1_FB7

#define CAN_F0R1_FB8

#define CAN_F0R1_FB9

#define CAN_F0R1_FB10

#define CAN_F0R1_FB11

#define CAN_F0R1_FB12

#define CAN_F0R1_FB13

#define CAN_F0R1_FB14

#define CAN_F0R1_FB15

#define CAN_F0R1_FB16

#define CAN_F0R1_FB17

#define CAN_F0R1_FB18

#define CAN_F0R1_FB19

#define CAN_F0R1_FB20

#define CAN_F0R1_FB21

#define CAN_F0R1_FB22

#define CAN_F0R1_FB23

#define CAN_F0R1_FB24

#define CAN_F0R1_FB25

#define CAN_F0R1_FB26

#define CAN_F0R1_FB27

#define CAN_F0R1_FB28

#define CAN_F0R1_FB29

#define CAN_F0R1_FB30

#define CAN_F0R1_FB31

#define CAN_F1R1_FB0

#define CAN_F1R1_FB1

#define CAN_F1R1_FB2

#define CAN_F1R1_FB3

#define CAN_F1R1_FB4

#define CAN_F1R1_FB5

#define CAN_F1R1_FB6

#define CAN_F1R1_FB7

#define CAN_F1R1_FB8

#define CAN_F1R1_FB9

#define CAN_F1R1_FB10

#define CAN_F1R1_FB11

#define CAN_F1R1_FB12

#define CAN_F1R1_FB13

#define CAN_F1R1_FB14

#define CAN_F1R1_FB15

#define CAN_F1R1_FB16

#define CAN_F1R1_FB17

#define CAN_F1R1_FB18

#define CAN_F1R1_FB19

#define CAN_F1R1_FB20

#define CAN_F1R1_FB21

#define CAN_F1R1_FB22

#define CAN_F1R1_FB23

#define CAN_F1R1_FB24

#define CAN_F1R1_FB25

#define CAN_F1R1_FB26

#define CAN_F1R1_FB27

#define CAN_F1R1_FB28

#define CAN_F1R1_FB29

#define CAN_F1R1_FB30

#define CAN_F1R1_FB31

#define CAN_F2R1_FB0

#define CAN_F2R1_FB1

#define CAN_F2R1_FB2

#define CAN_F2R1_FB3

#define CAN_F2R1_FB4

#define CAN_F2R1_FB5

#define CAN_F2R1_FB6

#define CAN_F2R1_FB7

#define CAN_F2R1_FB8

#define CAN_F2R1_FB9

#define CAN_F2R1_FB10

#define CAN_F2R1_FB11

#define CAN_F2R1_FB12

#define CAN_F2R1_FB13

#define CAN_F2R1_FB14

#define CAN_F2R1_FB15

#define CAN_F2R1_FB16

#define CAN_F2R1_FB17

#define CAN_F2R1_FB18

#define CAN_F2R1_FB19

#define CAN_F2R1_FB20

#define CAN_F2R1_FB21

#define CAN_F2R1_FB22

#define CAN_F2R1_FB23

#define CAN_F2R1_FB24

#define CAN_F2R1_FB25

#define CAN_F2R1_FB26

#define CAN_F2R1_FB27

#define CAN_F2R1_FB28

#define CAN_F2R1_FB29

#define CAN_F2R1_FB30

#define CAN_F2R1_FB31

#define CAN_F3R1_FB0

#define CAN_F3R1_FB1

#define CAN_F3R1_FB2

#define CAN_F3R1_FB3

#define CAN_F3R1_FB4

#define CAN_F3R1_FB5

#define CAN_F3R1_FB6

#define CAN_F3R1_FB7

#define CAN_F3R1_FB8

#define CAN_F3R1_FB9

#define CAN_F3R1_FB10

#define CAN_F3R1_FB11

#define CAN_F3R1_FB12

#define CAN_F3R1_FB13

#define CAN_F3R1_FB14

#define CAN_F3R1_FB15

#define CAN_F3R1_FB16

#define CAN_F3R1_FB17

#define CAN_F3R1_FB18

#define CAN_F3R1_FB19

#define CAN_F3R1_FB20

#define CAN_F3R1_FB21

#define CAN_F3R1_FB22

#define CAN_F3R1_FB23

#define CAN_F3R1_FB24

#define CAN_F3R1_FB25

#define CAN_F3R1_FB26

#define CAN_F3R1_FB27

#define CAN_F3R1_FB28

#define CAN_F3R1_FB29

#define CAN_F3R1_FB30

#define CAN_F3R1_FB31

#define CAN_F4R1_FB0

#define CAN_F4R1_FB1

#define CAN_F4R1_FB2

#define CAN_F4R1_FB3

#define CAN_F4R1_FB4

#define CAN_F4R1_FB5

#define CAN_F4R1_FB6

#define CAN_F4R1_FB7

#define CAN_F4R1_FB8

#define CAN_F4R1_FB9

#define CAN_F4R1_FB10

#define CAN_F4R1_FB11

#define CAN_F4R1_FB12

#define CAN_F4R1_FB13

#define CAN_F4R1_FB14

#define CAN_F4R1_FB15

#define CAN_F4R1_FB16

#define CAN_F4R1_FB17

#define CAN_F4R1_FB18

#define CAN_F4R1_FB19

#define CAN_F4R1_FB20

#define CAN_F4R1_FB21

#define CAN_F4R1_FB22

#define CAN_F4R1_FB23

#define CAN_F4R1_FB24

#define CAN_F4R1_FB25

#define CAN_F4R1_FB26

#define CAN_F4R1_FB27

#define CAN_F4R1_FB28

#define CAN_F4R1_FB29

#define CAN_F4R1_FB30

#define CAN_F4R1_FB31

#define CAN_F5R1_FB0

#define CAN_F5R1_FB1

#define CAN_F5R1_FB2

#define CAN_F5R1_FB3

#define CAN_F5R1_FB4

#define CAN_F5R1_FB5

#define CAN_F5R1_FB6

#define CAN_F5R1_FB7

#define CAN_F5R1_FB8

#define CAN_F5R1_FB9

#define CAN_F5R1_FB10

#define CAN_F5R1_FB11

#define CAN_F5R1_FB12

#define CAN_F5R1_FB13

#define CAN_F5R1_FB14

#define CAN_F5R1_FB15

#define CAN_F5R1_FB16

#define CAN_F5R1_FB17

#define CAN_F5R1_FB18

#define CAN_F5R1_FB19

#define CAN_F5R1_FB20

#define CAN_F5R1_FB21

#define CAN_F5R1_FB22

#define CAN_F5R1_FB23

#define CAN_F5R1_FB24

#define CAN_F5R1_FB25

#define CAN_F5R1_FB26

#define CAN_F5R1_FB27

#define CAN_F5R1_FB28

#define CAN_F5R1_FB29

#define CAN_F5R1_FB30

#define CAN_F5R1_FB31

#define CAN_F6R1_FB0

#define CAN_F6R1_FB1

#define CAN_F6R1_FB2

#define CAN_F6R1_FB3

#define CAN_F6R1_FB4

#define CAN_F6R1_FB5

#define CAN_F6R1_FB6

#define CAN_F6R1_FB7

#define CAN_F6R1_FB8

#define CAN_F6R1_FB9

#define CAN_F6R1_FB10

#define CAN_F6R1_FB11

#define CAN_F6R1_FB12

#define CAN_F6R1_FB13

#define CAN_F6R1_FB14

#define CAN_F6R1_FB15

#define CAN_F6R1_FB16

#define CAN_F6R1_FB17

#define CAN_F6R1_FB18

#define CAN_F6R1_FB19

#define CAN_F6R1_FB20

#define CAN_F6R1_FB21

#define CAN_F6R1_FB22

#define CAN_F6R1_FB23

#define CAN_F6R1_FB24

#define CAN_F6R1_FB25

#define CAN_F6R1_FB26

#define CAN_F6R1_FB27

#define CAN_F6R1_FB28

#define CAN_F6R1_FB29

#define CAN_F6R1_FB30

#define CAN_F6R1_FB31

#define CAN_F7R1_FB0

#define CAN_F7R1_FB1

#define CAN_F7R1_FB2

#define CAN_F7R1_FB3

#define CAN_F7R1_FB4

#define CAN_F7R1_FB5

#define CAN_F7R1_FB6

#define CAN_F7R1_FB7

#define CAN_F7R1_FB8

#define CAN_F7R1_FB9

#define CAN_F7R1_FB10

#define CAN_F7R1_FB11

#define CAN_F7R1_FB12

#define CAN_F7R1_FB13

#define CAN_F7R1_FB14

#define CAN_F7R1_FB15

#define CAN_F7R1_FB16

#define CAN_F7R1_FB17

#define CAN_F7R1_FB18

#define CAN_F7R1_FB19

#define CAN_F7R1_FB20

#define CAN_F7R1_FB21

#define CAN_F7R1_FB22

#define CAN_F7R1_FB23

#define CAN_F7R1_FB24

#define CAN_F7R1_FB25

#define CAN_F7R1_FB26

#define CAN_F7R1_FB27

#define CAN_F7R1_FB28

#define CAN_F7R1_FB29

#define CAN_F7R1_FB30

#define CAN_F7R1_FB31

#define CAN_F8R1_FB0

#define CAN_F8R1_FB1

#define CAN_F8R1_FB2

#define CAN_F8R1_FB3

#define CAN_F8R1_FB4

#define CAN_F8R1_FB5

#define CAN_F8R1_FB6

#define CAN_F8R1_FB7

#define CAN_F8R1_FB8

#define CAN_F8R1_FB9

#define CAN_F8R1_FB10

#define CAN_F8R1_FB11

#define CAN_F8R1_FB12

#define CAN_F8R1_FB13

#define CAN_F8R1_FB14

#define CAN_F8R1_FB15

#define CAN_F8R1_FB16

#define CAN_F8R1_FB17

#define CAN_F8R1_FB18

#define CAN_F8R1_FB19

#define CAN_F8R1_FB20

#define CAN_F8R1_FB21

#define CAN_F8R1_FB22

#define CAN_F8R1_FB23

#define CAN_F8R1_FB24

#define CAN_F8R1_FB25

#define CAN_F8R1_FB26

#define CAN_F8R1_FB27

#define CAN_F8R1_FB28

#define CAN_F8R1_FB29

#define CAN_F8R1_FB30

#define CAN_F8R1_FB31

#define CAN_F9R1_FB0

#define CAN_F9R1_FB1

#define CAN_F9R1_FB2

#define CAN_F9R1_FB3

#define CAN_F9R1_FB4

#define CAN_F9R1_FB5

#define CAN_F9R1_FB6

#define CAN_F9R1_FB7

#define CAN_F9R1_FB8

#define CAN_F9R1_FB9

#define CAN_F9R1_FB10

#define CAN_F9R1_FB11

#define CAN_F9R1_FB12

#define CAN_F9R1_FB13

#define CAN_F9R1_FB14

#define CAN_F9R1_FB15

#define CAN_F9R1_FB16

#define CAN_F9R1_FB17

#define CAN_F9R1_FB18

#define CAN_F9R1_FB19

#define CAN_F9R1_FB20

#define CAN_F9R1_FB21

#define CAN_F9R1_FB22

#define CAN_F9R1_FB23

#define CAN_F9R1_FB24

#define CAN_F9R1_FB25

#define CAN_F9R1_FB26

#define CAN_F9R1_FB27

#define CAN_F9R1_FB28

#define CAN_F9R1_FB29

#define CAN_F9R1_FB30

#define CAN_F9R1_FB31

#define CAN_F10R1_FB0

#define CAN_F10R1_FB1

#define CAN_F10R1_FB2

#define CAN_F10R1_FB3

#define CAN_F10R1_FB4

#define CAN_F10R1_FB5

#define CAN_F10R1_FB6

#define CAN_F10R1_FB7

#define CAN_F10R1_FB8

#define CAN_F10R1_FB9

#define CAN_F10R1_FB10

#define CAN_F10R1_FB11

#define CAN_F10R1_FB12

#define CAN_F10R1_FB13

#define CAN_F10R1_FB14

#define CAN_F10R1_FB15

#define CAN_F10R1_FB16

#define CAN_F10R1_FB17

#define CAN_F10R1_FB18

#define CAN_F10R1_FB19

#define CAN_F10R1_FB20

#define CAN_F10R1_FB21

#define CAN_F10R1_FB22

#define CAN_F10R1_FB23

#define CAN_F10R1_FB24

#define CAN_F10R1_FB25

#define CAN_F10R1_FB26

#define CAN_F10R1_FB27

#define CAN_F10R1_FB28

#define CAN_F10R1_FB29

#define CAN_F10R1_FB30

#define CAN_F10R1_FB31

#define CAN_F11R1_FB0

#define CAN_F11R1_FB1

#define CAN_F11R1_FB2

#define CAN_F11R1_FB3

#define CAN_F11R1_FB4

#define CAN_F11R1_FB5

#define CAN_F11R1_FB6

#define CAN_F11R1_FB7

#define CAN_F11R1_FB8

#define CAN_F11R1_FB9

#define CAN_F11R1_FB10

#define CAN_F11R1_FB11

#define CAN_F11R1_FB12

#define CAN_F11R1_FB13

#define CAN_F11R1_FB14

#define CAN_F11R1_FB15

#define CAN_F11R1_FB16

#define CAN_F11R1_FB17

#define CAN_F11R1_FB18

#define CAN_F11R1_FB19

#define CAN_F11R1_FB20

#define CAN_F11R1_FB21

#define CAN_F11R1_FB22

#define CAN_F11R1_FB23

#define CAN_F11R1_FB24

#define CAN_F11R1_FB25

#define CAN_F11R1_FB26

#define CAN_F11R1_FB27

#define CAN_F11R1_FB28

#define CAN_F11R1_FB29

#define CAN_F11R1_FB30

#define CAN_F11R1_FB31

#define CAN_F12R1_FB0

#define CAN_F12R1_FB1

#define CAN_F12R1_FB2

#define CAN_F12R1_FB3

#define CAN_F12R1_FB4

#define CAN_F12R1_FB5

#define CAN_F12R1_FB6

#define CAN_F12R1_FB7

#define CAN_F12R1_FB8

#define CAN_F12R1_FB9

#define CAN_F12R1_FB10

#define CAN_F12R1_FB11

#define CAN_F12R1_FB12

#define CAN_F12R1_FB13

#define CAN_F12R1_FB14

#define CAN_F12R1_FB15

#define CAN_F12R1_FB16

#define CAN_F12R1_FB17

#define CAN_F12R1_FB18

#define CAN_F12R1_FB19

#define CAN_F12R1_FB20

#define CAN_F12R1_FB21

#define CAN_F12R1_FB22

#define CAN_F12R1_FB23

#define CAN_F12R1_FB24

#define CAN_F12R1_FB25

#define CAN_F12R1_FB26

#define CAN_F12R1_FB27

#define CAN_F12R1_FB28

#define CAN_F12R1_FB29

#define CAN_F12R1_FB30

#define CAN_F12R1_FB31

#define CAN_F13R1_FB0

#define CAN_F13R1_FB1

#define CAN_F13R1_FB2

#define CAN_F13R1_FB3

#define CAN_F13R1_FB4

#define CAN_F13R1_FB5

#define CAN_F13R1_FB6

#define CAN_F13R1_FB7

#define CAN_F13R1_FB8

#define CAN_F13R1_FB9

#define CAN_F13R1_FB10

#define CAN_F13R1_FB11

#define CAN_F13R1_FB12

#define CAN_F13R1_FB13

#define CAN_F13R1_FB14

#define CAN_F13R1_FB15

#define CAN_F13R1_FB16

#define CAN_F13R1_FB17

#define CAN_F13R1_FB18

#define CAN_F13R1_FB19

#define CAN_F13R1_FB20

#define CAN_F13R1_FB21

#define CAN_F13R1_FB22

#define CAN_F13R1_FB23

#define CAN_F13R1_FB24

#define CAN_F13R1_FB25

#define CAN_F13R1_FB26

#define CAN_F13R1_FB27

#define CAN_F13R1_FB28

#define CAN_F13R1_FB29

#define CAN_F13R1_FB30

#define CAN_F13R1_FB31

#define CAN_F0R2_FB0

#define CAN_F0R2_FB1

#define CAN_F0R2_FB2

#define CAN_F0R2_FB3

#define CAN_F0R2_FB4

#define CAN_F0R2_FB5

#define CAN_F0R2_FB6

#define CAN_F0R2_FB7

#define CAN_F0R2_FB8

#define CAN_F0R2_FB9

#define CAN_F0R2_FB10

#define CAN_F0R2_FB11

#define CAN_F0R2_FB12

#define CAN_F0R2_FB13

#define CAN_F0R2_FB14

#define CAN_F0R2_FB15

#define CAN_F0R2_FB16

#define CAN_F0R2_FB17

#define CAN_F0R2_FB18

#define CAN_F0R2_FB19

#define CAN_F0R2_FB20

#define CAN_F0R2_FB21

#define CAN_F0R2_FB22

#define CAN_F0R2_FB23

#define CAN_F0R2_FB24

#define CAN_F0R2_FB25

#define CAN_F0R2_FB26

#define CAN_F0R2_FB27

#define CAN_F0R2_FB28

#define CAN_F0R2_FB29

#define CAN_F0R2_FB30

#define CAN_F0R2_FB31

#define CAN_F1R2_FB0

#define CAN_F1R2_FB1

#define CAN_F1R2_FB2

#define CAN_F1R2_FB3

#define CAN_F1R2_FB4

#define CAN_F1R2_FB5

#define CAN_F1R2_FB6

#define CAN_F1R2_FB7

#define CAN_F1R2_FB8

#define CAN_F1R2_FB9

#define CAN_F1R2_FB10

#define CAN_F1R2_FB11

#define CAN_F1R2_FB12

#define CAN_F1R2_FB13

#define CAN_F1R2_FB14

#define CAN_F1R2_FB15

#define CAN_F1R2_FB16

#define CAN_F1R2_FB17

#define CAN_F1R2_FB18

#define CAN_F1R2_FB19

#define CAN_F1R2_FB20

#define CAN_F1R2_FB21

#define CAN_F1R2_FB22

#define CAN_F1R2_FB23

#define CAN_F1R2_FB24

#define CAN_F1R2_FB25

#define CAN_F1R2_FB26

#define CAN_F1R2_FB27

#define CAN_F1R2_FB28

#define CAN_F1R2_FB29

#define CAN_F1R2_FB30

#define CAN_F1R2_FB31

#define CAN_F2R2_FB0

#define CAN_F2R2_FB1

#define CAN_F2R2_FB2

#define CAN_F2R2_FB3

#define CAN_F2R2_FB4

#define CAN_F2R2_FB5

#define CAN_F2R2_FB6

#define CAN_F2R2_FB7

#define CAN_F2R2_FB8

#define CAN_F2R2_FB9

#define CAN_F2R2_FB10

#define CAN_F2R2_FB11

#define CAN_F2R2_FB12

#define CAN_F2R2_FB13

#define CAN_F2R2_FB14

#define CAN_F2R2_FB15

#define CAN_F2R2_FB16

#define CAN_F2R2_FB17

#define CAN_F2R2_FB18

#define CAN_F2R2_FB19

#define CAN_F2R2_FB20

#define CAN_F2R2_FB21

#define CAN_F2R2_FB22

#define CAN_F2R2_FB23

#define CAN_F2R2_FB24

#define CAN_F2R2_FB25

#define CAN_F2R2_FB26

#define CAN_F2R2_FB27

#define CAN_F2R2_FB28

#define CAN_F2R2_FB29

#define CAN_F2R2_FB30

#define CAN_F2R2_FB31

#define CAN_F3R2_FB0

#define CAN_F3R2_FB1

#define CAN_F3R2_FB2

#define CAN_F3R2_FB3

#define CAN_F3R2_FB4

#define CAN_F3R2_FB5

#define CAN_F3R2_FB6

#define CAN_F3R2_FB7

#define CAN_F3R2_FB8

#define CAN_F3R2_FB9

#define CAN_F3R2_FB10

#define CAN_F3R2_FB11

#define CAN_F3R2_FB12

#define CAN_F3R2_FB13

#define CAN_F3R2_FB14

#define CAN_F3R2_FB15

#define CAN_F3R2_FB16

#define CAN_F3R2_FB17

#define CAN_F3R2_FB18

#define CAN_F3R2_FB19

#define CAN_F3R2_FB20

#define CAN_F3R2_FB21

#define CAN_F3R2_FB22

#define CAN_F3R2_FB23

#define CAN_F3R2_FB24

#define CAN_F3R2_FB25

#define CAN_F3R2_FB26

#define CAN_F3R2_FB27

#define CAN_F3R2_FB28

#define CAN_F3R2_FB29

#define CAN_F3R2_FB30

#define CAN_F3R2_FB31

#define CAN_F4R2_FB0

#define CAN_F4R2_FB1

#define CAN_F4R2_FB2

#define CAN_F4R2_FB3

#define CAN_F4R2_FB4

#define CAN_F4R2_FB5

#define CAN_F4R2_FB6

#define CAN_F4R2_FB7

#define CAN_F4R2_FB8

#define CAN_F4R2_FB9

#define CAN_F4R2_FB10

#define CAN_F4R2_FB11

#define CAN_F4R2_FB12

#define CAN_F4R2_FB13

#define CAN_F4R2_FB14

#define CAN_F4R2_FB15

#define CAN_F4R2_FB16

#define CAN_F4R2_FB17

#define CAN_F4R2_FB18

#define CAN_F4R2_FB19

#define CAN_F4R2_FB20

#define CAN_F4R2_FB21

#define CAN_F4R2_FB22

#define CAN_F4R2_FB23

#define CAN_F4R2_FB24

#define CAN_F4R2_FB25

#define CAN_F4R2_FB26

#define CAN_F4R2_FB27

#define CAN_F4R2_FB28

#define CAN_F4R2_FB29

#define CAN_F4R2_FB30

#define CAN_F4R2_FB31

#define CAN_F5R2_FB0

#define CAN_F5R2_FB1

#define CAN_F5R2_FB2

#define CAN_F5R2_FB3

#define CAN_F5R2_FB4

#define CAN_F5R2_FB5

#define CAN_F5R2_FB6

#define CAN_F5R2_FB7

#define CAN_F5R2_FB8

#define CAN_F5R2_FB9

#define CAN_F5R2_FB10

#define CAN_F5R2_FB11

#define CAN_F5R2_FB12

#define CAN_F5R2_FB13

#define CAN_F5R2_FB14

#define CAN_F5R2_FB15

#define CAN_F5R2_FB16

#define CAN_F5R2_FB17

#define CAN_F5R2_FB18

#define CAN_F5R2_FB19

#define CAN_F5R2_FB20

#define CAN_F5R2_FB21

#define CAN_F5R2_FB22

#define CAN_F5R2_FB23

#define CAN_F5R2_FB24

#define CAN_F5R2_FB25

#define CAN_F5R2_FB26

#define CAN_F5R2_FB27

#define CAN_F5R2_FB28

#define CAN_F5R2_FB29

#define CAN_F5R2_FB30

#define CAN_F5R2_FB31

#define CAN_F6R2_FB0

#define CAN_F6R2_FB1

#define CAN_F6R2_FB2

#define CAN_F6R2_FB3

#define CAN_F6R2_FB4

#define CAN_F6R2_FB5

#define CAN_F6R2_FB6

#define CAN_F6R2_FB7

#define CAN_F6R2_FB8

#define CAN_F6R2_FB9

#define CAN_F6R2_FB10

#define CAN_F6R2_FB11

#define CAN_F6R2_FB12

#define CAN_F6R2_FB13

#define CAN_F6R2_FB14

#define CAN_F6R2_FB15

#define CAN_F6R2_FB16

#define CAN_F6R2_FB17

#define CAN_F6R2_FB18

#define CAN_F6R2_FB19

#define CAN_F6R2_FB20

#define CAN_F6R2_FB21

#define CAN_F6R2_FB22

#define CAN_F6R2_FB23

#define CAN_F6R2_FB24

#define CAN_F6R2_FB25

#define CAN_F6R2_FB26

#define CAN_F6R2_FB27

#define CAN_F6R2_FB28

#define CAN_F6R2_FB29

#define CAN_F6R2_FB30

#define CAN_F6R2_FB31

#define CAN_F7R2_FB0

#define CAN_F7R2_FB1

#define CAN_F7R2_FB2

#define CAN_F7R2_FB3

#define CAN_F7R2_FB4

#define CAN_F7R2_FB5

#define CAN_F7R2_FB6

#define CAN_F7R2_FB7

#define CAN_F7R2_FB8

#define CAN_F7R2_FB9

#define CAN_F7R2_FB10

#define CAN_F7R2_FB11

#define CAN_F7R2_FB12

#define CAN_F7R2_FB13

#define CAN_F7R2_FB14

#define CAN_F7R2_FB15

#define CAN_F7R2_FB16

#define CAN_F7R2_FB17

#define CAN_F7R2_FB18

#define CAN_F7R2_FB19

#define CAN_F7R2_FB20

#define CAN_F7R2_FB21

#define CAN_F7R2_FB22

#define CAN_F7R2_FB23

#define CAN_F7R2_FB24

#define CAN_F7R2_FB25

#define CAN_F7R2_FB26

#define CAN_F7R2_FB27

#define CAN_F7R2_FB28

#define CAN_F7R2_FB29

#define CAN_F7R2_FB30

#define CAN_F7R2_FB31

#define CAN_F8R2_FB0

#define CAN_F8R2_FB1

#define CAN_F8R2_FB2

#define CAN_F8R2_FB3

#define CAN_F8R2_FB4

#define CAN_F8R2_FB5

#define CAN_F8R2_FB6

#define CAN_F8R2_FB7

#define CAN_F8R2_FB8

#define CAN_F8R2_FB9

#define CAN_F8R2_FB10

#define CAN_F8R2_FB11

#define CAN_F8R2_FB12

#define CAN_F8R2_FB13

#define CAN_F8R2_FB14

#define CAN_F8R2_FB15

#define CAN_F8R2_FB16

#define CAN_F8R2_FB17

#define CAN_F8R2_FB18

#define CAN_F8R2_FB19

#define CAN_F8R2_FB20

#define CAN_F8R2_FB21

#define CAN_F8R2_FB22

#define CAN_F8R2_FB23

#define CAN_F8R2_FB24

#define CAN_F8R2_FB25

#define CAN_F8R2_FB26

#define CAN_F8R2_FB27

#define CAN_F8R2_FB28

#define CAN_F8R2_FB29

#define CAN_F8R2_FB30

#define CAN_F8R2_FB31

#define CAN_F9R2_FB0

#define CAN_F9R2_FB1

#define CAN_F9R2_FB2

#define CAN_F9R2_FB3

#define CAN_F9R2_FB4

#define CAN_F9R2_FB5

#define CAN_F9R2_FB6

#define CAN_F9R2_FB7

#define CAN_F9R2_FB8

#define CAN_F9R2_FB9

#define CAN_F9R2_FB10

#define CAN_F9R2_FB11

#define CAN_F9R2_FB12

#define CAN_F9R2_FB13

#define CAN_F9R2_FB14

#define CAN_F9R2_FB15

#define CAN_F9R2_FB16

#define CAN_F9R2_FB17

#define CAN_F9R2_FB18

#define CAN_F9R2_FB19

#define CAN_F9R2_FB20

#define CAN_F9R2_FB21

#define CAN_F9R2_FB22

#define CAN_F9R2_FB23

#define CAN_F9R2_FB24

#define CAN_F9R2_FB25

#define CAN_F9R2_FB26

#define CAN_F9R2_FB27

#define CAN_F9R2_FB28

#define CAN_F9R2_FB29

#define CAN_F9R2_FB30

#define CAN_F9R2_FB31

#define CAN_F10R2_FB0

#define CAN_F10R2_FB1

#define CAN_F10R2_FB2

#define CAN_F10R2_FB3

#define CAN_F10R2_FB4

#define CAN_F10R2_FB5

#define CAN_F10R2_FB6

#define CAN_F10R2_FB7

#define CAN_F10R2_FB8

#define CAN_F10R2_FB9

#define CAN_F10R2_FB10

#define CAN_F10R2_FB11

#define CAN_F10R2_FB12

#define CAN_F10R2_FB13

#define CAN_F10R2_FB14

#define CAN_F10R2_FB15

#define CAN_F10R2_FB16

#define CAN_F10R2_FB17

#define CAN_F10R2_FB18

#define CAN_F10R2_FB19

#define CAN_F10R2_FB20

#define CAN_F10R2_FB21

#define CAN_F10R2_FB22

#define CAN_F10R2_FB23

#define CAN_F10R2_FB24

#define CAN_F10R2_FB25

#define CAN_F10R2_FB26

#define CAN_F10R2_FB27

#define CAN_F10R2_FB28

#define CAN_F10R2_FB29

#define CAN_F10R2_FB30

#define CAN_F10R2_FB31

#define CAN_F11R2_FB0

#define CAN_F11R2_FB1

#define CAN_F11R2_FB2

#define CAN_F11R2_FB3

#define CAN_F11R2_FB4

#define CAN_F11R2_FB5

#define CAN_F11R2_FB6

#define CAN_F11R2_FB7

#define CAN_F11R2_FB8

#define CAN_F11R2_FB9

#define CAN_F11R2_FB10

#define CAN_F11R2_FB11

#define CAN_F11R2_FB12

#define CAN_F11R2_FB13

#define CAN_F11R2_FB14

#define CAN_F11R2_FB15

#define CAN_F11R2_FB16

#define CAN_F11R2_FB17

#define CAN_F11R2_FB18

#define CAN_F11R2_FB19

#define CAN_F11R2_FB20

#define CAN_F11R2_FB21

#define CAN_F11R2_FB22

#define CAN_F11R2_FB23

#define CAN_F11R2_FB24

#define CAN_F11R2_FB25

#define CAN_F11R2_FB26

#define CAN_F11R2_FB27

#define CAN_F11R2_FB28

#define CAN_F11R2_FB29

#define CAN_F11R2_FB30

#define CAN_F11R2_FB31

#define CAN_F12R2_FB0

#define CAN_F12R2_FB1

#define CAN_F12R2_FB2

#define CAN_F12R2_FB3

#define CAN_F12R2_FB4

#define CAN_F12R2_FB5

#define CAN_F12R2_FB6

#define CAN_F12R2_FB7

#define CAN_F12R2_FB8

#define CAN_F12R2_FB9

#define CAN_F12R2_FB10

#define CAN_F12R2_FB11

#define CAN_F12R2_FB12

#define CAN_F12R2_FB13

#define CAN_F12R2_FB14

#define CAN_F12R2_FB15

#define CAN_F12R2_FB16

#define CAN_F12R2_FB17

#define CAN_F12R2_FB18

#define CAN_F12R2_FB19

#define CAN_F12R2_FB20

#define CAN_F12R2_FB21

#define CAN_F12R2_FB22

#define CAN_F12R2_FB23

#define CAN_F12R2_FB24

#define CAN_F12R2_FB25

#define CAN_F12R2_FB26

#define CAN_F12R2_FB27

#define CAN_F12R2_FB28

#define CAN_F12R2_FB29

#define CAN_F12R2_FB30

#define CAN_F12R2_FB31

#define CAN_F13R2_FB0

#define CAN_F13R2_FB1

#define CAN_F13R2_FB2

#define CAN_F13R2_FB3

#define CAN_F13R2_FB4

#define CAN_F13R2_FB5

#define CAN_F13R2_FB6

#define CAN_F13R2_FB7

#define CAN_F13R2_FB8

#define CAN_F13R2_FB9

#define CAN_F13R2_FB10

#define CAN_F13R2_FB11

#define CAN_F13R2_FB12

#define CAN_F13R2_FB13

#define CAN_F13R2_FB14

#define CAN_F13R2_FB15

#define CAN_F13R2_FB16

#define CAN_F13R2_FB17

#define CAN_F13R2_FB18

#define CAN_F13R2_FB19

#define CAN_F13R2_FB20

#define CAN_F13R2_FB21

#define CAN_F13R2_FB22

#define CAN_F13R2_FB23

#define CAN_F13R2_FB24

#define CAN_F13R2_FB25

#define CAN_F13R2_FB26

#define CAN_F13R2_FB27

#define CAN_F13R2_FB28

#define CAN_F13R2_FB29

#define CAN_F13R2_FB30

#define CAN_F13R2_FB31

#define CRC_DR_DR

#define CRC_IDR_IDR

#define CRC_CR_RESET

#define CRYP_CR_ALGODIR

#define CRYP_CR_ALGOMODE

#define CRYP_CR_ALGOMODE_0

#define CRYP_CR_ALGOMODE_1

#define CRYP_CR_ALGOMODE_2

#define CRYP_CR_ALGOMODE_TDES_ECB

#define CRYP_CR_ALGOMODE_TDES_CBC

#define CRYP_CR_ALGOMODE_DES_ECB

#define CRYP_CR_ALGOMODE_DES_CBC

#define CRYP_CR_ALGOMODE_AES_ECB

#define CRYP_CR_ALGOMODE_AES_CBC

#define CRYP_CR_ALGOMODE_AES_CTR

#define CRYP_CR_ALGOMODE_AES_KEY

#define CRYP_CR_DATATYPE

#define CRYP_CR_DATATYPE_0

#define CRYP_CR_DATATYPE_1

#define CRYP_CR_KEYSIZE

#define CRYP_CR_KEYSIZE_0

#define CRYP_CR_KEYSIZE_1

#define CRYP_CR_FFLUSH

#define CRYP_CR_CRYPEN

#define CRYP_SR_IFEM

#define CRYP_SR_IFNF

#define CRYP_SR_OFNE

#define CRYP_SR_OFFU

#define CRYP_SR_BUSY

#define CRYP_DMACR_DIEN

#define CRYP_DMACR_DOEN

#define CRYP_IMSCR_INIM

#define CRYP_IMSCR_OUTIM

#define CRYP_RISR_OUTRIS

#define CRYP_RISR_INRIS

#define CRYP_MISR_INMIS

#define CRYP_MISR_OUTMIS

#define DAC_CR_EN1

#define DAC_CR_BOFF1

#define DAC_CR_TEN1

#define DAC_CR_TSEL1

#define DAC_CR_TSEL1_0

#define DAC_CR_TSEL1_1

#define DAC_CR_TSEL1_2

#define DAC_CR_WAVE1

#define DAC_CR_WAVE1_0

#define DAC_CR_WAVE1_1

#define DAC_CR_MAMP1

#define DAC_CR_MAMP1_0

#define DAC_CR_MAMP1_1

#define DAC_CR_MAMP1_2

#define DAC_CR_MAMP1_3

#define DAC_CR_DMAEN1

#define DAC_CR_EN2

#define DAC_CR_BOFF2

#define DAC_CR_TEN2

#define DAC_CR_TSEL2

#define DAC_CR_TSEL2_0

#define DAC_CR_TSEL2_1

#define DAC_CR_TSEL2_2

#define DAC_CR_WAVE2

#define DAC_CR_WAVE2_0

#define DAC_CR_WAVE2_1

#define DAC_CR_MAMP2

#define DAC_CR_MAMP2_0

#define DAC_CR_MAMP2_1

#define DAC_CR_MAMP2_2

#define DAC_CR_MAMP2_3

#define DAC_CR_DMAEN2

#define DAC_SWTRIGR_SWTRIG1

#define DAC_SWTRIGR_SWTRIG2

#define DAC_DHR12R1_DACC1DHR

#define DAC_DHR12L1_DACC1DHR

#define DAC_DHR8R1_DACC1DHR

#define DAC_DHR12R2_DACC2DHR

#define DAC_DHR12L2_DACC2DHR

#define DAC_DHR8R2_DACC2DHR

#define DAC_DHR12RD_DACC1DHR

#define DAC_DHR12RD_DACC2DHR

#define DAC_DHR12LD_DACC1DHR

#define DAC_DHR12LD_DACC2DHR

#define DAC_DHR8RD_DACC1DHR

#define DAC_DHR8RD_DACC2DHR

#define DAC_DOR1_DACC1DOR

#define DAC_DOR2_DACC2DOR

#define DAC_SR_DMAUDR1

#define DAC_SR_DMAUDR2

#define DCMI_CR_CAPTURE

#define DCMI_CR_CM

#define DCMI_CR_CROP

#define DCMI_CR_JPEG

#define DCMI_CR_ESS

#define DCMI_CR_PCKPOL

#define DCMI_CR_HSPOL

#define DCMI_CR_VSPOL

#define DCMI_CR_FCRC_0

#define DCMI_CR_FCRC_1

#define DCMI_CR_EDM_0

#define DCMI_CR_EDM_1

#define DCMI_CR_CRE

#define DCMI_CR_ENABLE

#define DCMI_SR_HSYNC

#define DCMI_SR_VSYNC

#define DCMI_SR_FNE

#define DCMI_RISR_FRAME_RIS

#define DCMI_RISR_OVF_RIS

#define DCMI_RISR_ERR_RIS

#define DCMI_RISR_VSYNC_RIS

#define DCMI_RISR_LINE_RIS

#define DCMI_IER_FRAME_IE

#define DCMI_IER_OVF_IE

#define DCMI_IER_ERR_IE

#define DCMI_IER_VSYNC_IE

#define DCMI_IER_LINE_IE

#define DCMI_MISR_FRAME_MIS

#define DCMI_MISR_OVF_MIS

#define DCMI_MISR_ERR_MIS

#define DCMI_MISR_VSYNC_MIS

#define DCMI_MISR_LINE_MIS

#define DCMI_ICR_FRAME_ISC

#define DCMI_ICR_OVF_ISC

#define DCMI_ICR_ERR_ISC

#define DCMI_ICR_VSYNC_ISC

#define DCMI_ICR_LINE_ISC

#define DMA_SxCR_CHSEL

#define DMA_SxCR_CHSEL_0

#define DMA_SxCR_CHSEL_1

#define DMA_SxCR_CHSEL_2

#define DMA_SxCR_MBURST

#define DMA_SxCR_MBURST_0

#define DMA_SxCR_MBURST_1

#define DMA_SxCR_PBURST

#define DMA_SxCR_PBURST_0

#define DMA_SxCR_PBURST_1

#define DMA_SxCR_ACK

#define DMA_SxCR_CT

#define DMA_SxCR_DBM

#define DMA_SxCR_PL

#define DMA_SxCR_PL_0

#define DMA_SxCR_PL_1

#define DMA_SxCR_PINCOS

#define DMA_SxCR_MSIZE

#define DMA_SxCR_MSIZE_0

#define DMA_SxCR_MSIZE_1

#define DMA_SxCR_PSIZE

#define DMA_SxCR_PSIZE_0

#define DMA_SxCR_PSIZE_1

#define DMA_SxCR_MINC

#define DMA_SxCR_PINC

#define DMA_SxCR_CIRC

#define DMA_SxCR_DIR

#define DMA_SxCR_DIR_0

#define DMA_SxCR_DIR_1

#define DMA_SxCR_PFCTRL

#define DMA_SxCR_TCIE

#define DMA_SxCR_HTIE

#define DMA_SxCR_TEIE

#define DMA_SxCR_DMEIE

#define DMA_SxCR_EN

#define DMA_SxNDT

#define DMA_SxNDT_0

#define DMA_SxNDT_1

#define DMA_SxNDT_2

#define DMA_SxNDT_3

#define DMA_SxNDT_4

#define DMA_SxNDT_5

#define DMA_SxNDT_6

#define DMA_SxNDT_7

#define DMA_SxNDT_8

#define DMA_SxNDT_9

#define DMA_SxNDT_10

#define DMA_SxNDT_11

#define DMA_SxNDT_12

#define DMA_SxNDT_13

#define DMA_SxNDT_14

#define DMA_SxNDT_15

#define DMA_SxFCR_FEIE

#define DMA_SxFCR_FS

#define DMA_SxFCR_FS_0

#define DMA_SxFCR_FS_1

#define DMA_SxFCR_FS_2

#define DMA_SxFCR_DMDIS

#define DMA_SxFCR_FTH

#define DMA_SxFCR_FTH_0

#define DMA_SxFCR_FTH_1

#define DMA_LISR_TCIF3

#define DMA_LISR_HTIF3

#define DMA_LISR_TEIF3

#define DMA_LISR_DMEIF3

#define DMA_LISR_FEIF3

#define DMA_LISR_TCIF2

#define DMA_LISR_HTIF2

#define DMA_LISR_TEIF2

#define DMA_LISR_DMEIF2

#define DMA_LISR_FEIF2

#define DMA_LISR_TCIF1

#define DMA_LISR_HTIF1

#define DMA_LISR_TEIF1

#define DMA_LISR_DMEIF1

#define DMA_LISR_FEIF1

#define DMA_LISR_TCIF0

#define DMA_LISR_HTIF0

#define DMA_LISR_TEIF0

#define DMA_LISR_DMEIF0

#define DMA_LISR_FEIF0

#define DMA_HISR_TCIF7

#define DMA_HISR_HTIF7

#define DMA_HISR_TEIF7

#define DMA_HISR_DMEIF7

#define DMA_HISR_FEIF7

#define DMA_HISR_TCIF6

#define DMA_HISR_HTIF6

#define DMA_HISR_TEIF6

#define DMA_HISR_DMEIF6

#define DMA_HISR_FEIF6

#define DMA_HISR_TCIF5

#define DMA_HISR_HTIF5

#define DMA_HISR_TEIF5

#define DMA_HISR_DMEIF5

#define DMA_HISR_FEIF5

#define DMA_HISR_TCIF4

#define DMA_HISR_HTIF4

#define DMA_HISR_TEIF4

#define DMA_HISR_DMEIF4

#define DMA_HISR_FEIF4

#define DMA_LIFCR_CTCIF3

#define DMA_LIFCR_CHTIF3

#define DMA_LIFCR_CTEIF3

#define DMA_LIFCR_CDMEIF3

#define DMA_LIFCR_CFEIF3

#define DMA_LIFCR_CTCIF2

#define DMA_LIFCR_CHTIF2

#define DMA_LIFCR_CTEIF2

#define DMA_LIFCR_CDMEIF2

#define DMA_LIFCR_CFEIF2

#define DMA_LIFCR_CTCIF1

#define DMA_LIFCR_CHTIF1

#define DMA_LIFCR_CTEIF1

#define DMA_LIFCR_CDMEIF1

#define DMA_LIFCR_CFEIF1

#define DMA_LIFCR_CTCIF0

#define DMA_LIFCR_CHTIF0

#define DMA_LIFCR_CTEIF0

#define DMA_LIFCR_CDMEIF0

#define DMA_LIFCR_CFEIF0

#define DMA_HIFCR_CTCIF7

#define DMA_HIFCR_CHTIF7

#define DMA_HIFCR_CTEIF7

#define DMA_HIFCR_CDMEIF7

#define DMA_HIFCR_CFEIF7

#define DMA_HIFCR_CTCIF6

#define DMA_HIFCR_CHTIF6

#define DMA_HIFCR_CTEIF6

#define DMA_HIFCR_CDMEIF6

#define DMA_HIFCR_CFEIF6

#define DMA_HIFCR_CTCIF5

#define DMA_HIFCR_CHTIF5

#define DMA_HIFCR_CTEIF5

#define DMA_HIFCR_CDMEIF5

#define DMA_HIFCR_CFEIF5

#define DMA_HIFCR_CTCIF4

#define DMA_HIFCR_CHTIF4

#define DMA_HIFCR_CTEIF4

#define DMA_HIFCR_CDMEIF4

#define DMA_HIFCR_CFEIF4

#define EXTI_IMR_MR0

#define EXTI_IMR_MR1

#define EXTI_IMR_MR2

#define EXTI_IMR_MR3

#define EXTI_IMR_MR4

#define EXTI_IMR_MR5

#define EXTI_IMR_MR6

#define EXTI_IMR_MR7

#define EXTI_IMR_MR8

#define EXTI_IMR_MR9

#define EXTI_IMR_MR10

#define EXTI_IMR_MR11

#define EXTI_IMR_MR12

#define EXTI_IMR_MR13

#define EXTI_IMR_MR14

#define EXTI_IMR_MR15

#define EXTI_IMR_MR16

#define EXTI_IMR_MR17

#define EXTI_IMR_MR18

#define EXTI_IMR_MR19

#define EXTI_EMR_MR0

#define EXTI_EMR_MR1

#define EXTI_EMR_MR2

#define EXTI_EMR_MR3

#define EXTI_EMR_MR4

#define EXTI_EMR_MR5

#define EXTI_EMR_MR6

#define EXTI_EMR_MR7

#define EXTI_EMR_MR8

#define EXTI_EMR_MR9

#define EXTI_EMR_MR10

#define EXTI_EMR_MR11

#define EXTI_EMR_MR12

#define EXTI_EMR_MR13

#define EXTI_EMR_MR14

#define EXTI_EMR_MR15

#define EXTI_EMR_MR16

#define EXTI_EMR_MR17

#define EXTI_EMR_MR18

#define EXTI_EMR_MR19

#define EXTI_RTSR_TR0

#define EXTI_RTSR_TR1

#define EXTI_RTSR_TR2

#define EXTI_RTSR_TR3

#define EXTI_RTSR_TR4

#define EXTI_RTSR_TR5

#define EXTI_RTSR_TR6

#define EXTI_RTSR_TR7

#define EXTI_RTSR_TR8

#define EXTI_RTSR_TR9

#define EXTI_RTSR_TR10

#define EXTI_RTSR_TR11

#define EXTI_RTSR_TR12

#define EXTI_RTSR_TR13

#define EXTI_RTSR_TR14

#define EXTI_RTSR_TR15

#define EXTI_RTSR_TR16

#define EXTI_RTSR_TR17

#define EXTI_RTSR_TR18

#define EXTI_RTSR_TR19

#define EXTI_FTSR_TR0

#define EXTI_FTSR_TR1

#define EXTI_FTSR_TR2

#define EXTI_FTSR_TR3

#define EXTI_FTSR_TR4

#define EXTI_FTSR_TR5

#define EXTI_FTSR_TR6

#define EXTI_FTSR_TR7

#define EXTI_FTSR_TR8

#define EXTI_FTSR_TR9

#define EXTI_FTSR_TR10

#define EXTI_FTSR_TR11

#define EXTI_FTSR_TR12

#define EXTI_FTSR_TR13

#define EXTI_FTSR_TR14

#define EXTI_FTSR_TR15

#define EXTI_FTSR_TR16

#define EXTI_FTSR_TR17

#define EXTI_FTSR_TR18

#define EXTI_FTSR_TR19

#define EXTI_SWIER_SWIER0

#define EXTI_SWIER_SWIER1

#define EXTI_SWIER_SWIER2

#define EXTI_SWIER_SWIER3

#define EXTI_SWIER_SWIER4

#define EXTI_SWIER_SWIER5

#define EXTI_SWIER_SWIER6

#define EXTI_SWIER_SWIER7

#define EXTI_SWIER_SWIER8

#define EXTI_SWIER_SWIER9

#define EXTI_SWIER_SWIER10

#define EXTI_SWIER_SWIER11

#define EXTI_SWIER_SWIER12

#define EXTI_SWIER_SWIER13

#define EXTI_SWIER_SWIER14

#define EXTI_SWIER_SWIER15

#define EXTI_SWIER_SWIER16

#define EXTI_SWIER_SWIER17

#define EXTI_SWIER_SWIER18

#define EXTI_SWIER_SWIER19

#define EXTI_PR_PR0

#define EXTI_PR_PR1

#define EXTI_PR_PR2

#define EXTI_PR_PR3

#define EXTI_PR_PR4

#define EXTI_PR_PR5

#define EXTI_PR_PR6

#define EXTI_PR_PR7

#define EXTI_PR_PR8

#define EXTI_PR_PR9

#define EXTI_PR_PR10

#define EXTI_PR_PR11

#define EXTI_PR_PR12

#define EXTI_PR_PR13

#define EXTI_PR_PR14

#define EXTI_PR_PR15

#define EXTI_PR_PR16

#define EXTI_PR_PR17

#define EXTI_PR_PR18

#define EXTI_PR_PR19

#define FLASH_ACR_LATENCY

#define FLASH_ACR_LATENCY_0WS

#define FLASH_ACR_LATENCY_1WS

#define FLASH_ACR_LATENCY_2WS

#define FLASH_ACR_LATENCY_3WS

#define FLASH_ACR_LATENCY_4WS

#define FLASH_ACR_LATENCY_5WS

#define FLASH_ACR_LATENCY_6WS

#define FLASH_ACR_LATENCY_7WS

#define FLASH_ACR_PRFTEN

#define FLASH_ACR_ICEN

#define FLASH_ACR_DCEN

#define FLASH_ACR_ICRST

#define FLASH_ACR_DCRST

#define FLASH_ACR_BYTE0_ADDRESS

#define FLASH_ACR_BYTE2_ADDRESS

#define FLASH_SR_EOP

#define FLASH_SR_SOP

#define FLASH_SR_WRPERR

#define FLASH_SR_PGAERR

#define FLASH_SR_PGPERR

#define FLASH_SR_PGSERR

#define FLASH_SR_BSY

#define FLASH_CR_PG

#define FLASH_CR_SER

#define FLASH_CR_MER

#define FLASH_CR_SNB_0

#define FLASH_CR_SNB_1

#define FLASH_CR_SNB_2

#define FLASH_CR_SNB_3

#define FLASH_CR_PSIZE_0

#define FLASH_CR_PSIZE_1

#define FLASH_CR_STRT

#define FLASH_CR_EOPIE

#define FLASH_CR_LOCK

#define FLASH_OPTCR_OPTLOCK

#define FLASH_OPTCR_OPTSTRT

#define FLASH_OPTCR_BOR_LEV_0

#define FLASH_OPTCR_BOR_LEV_1

#define FLASH_OPTCR_BOR_LEV

#define FLASH_OPTCR_WDG_SW

#define FLASH_OPTCR_nRST_STOP

#define FLASH_OPTCR_nRST_STDBY

#define FLASH_OPTCR_RDP_0

#define FLASH_OPTCR_RDP_1

#define FLASH_OPTCR_RDP_2

#define FLASH_OPTCR_RDP_3

#define FLASH_OPTCR_RDP_4

#define FLASH_OPTCR_RDP_5

#define FLASH_OPTCR_RDP_6

#define FLASH_OPTCR_RDP_7

#define FLASH_OPTCR_nWRP_0

#define FLASH_OPTCR_nWRP_1

#define FLASH_OPTCR_nWRP_2

#define FLASH_OPTCR_nWRP_3

#define FLASH_OPTCR_nWRP_4

#define FLASH_OPTCR_nWRP_5

#define FLASH_OPTCR_nWRP_6

#define FLASH_OPTCR_nWRP_7

#define FLASH_OPTCR_nWRP_8

#define FLASH_OPTCR_nWRP_9

#define FLASH_OPTCR_nWRP_10

#define FLASH_OPTCR_nWRP_11

#define FSMC_BCR1_MBKEN

#define FSMC_BCR1_MUXEN

#define FSMC_BCR1_MTYP

#define FSMC_BCR1_MTYP_0

#define FSMC_BCR1_MTYP_1

#define FSMC_BCR1_MWID

#define FSMC_BCR1_MWID_0

#define FSMC_BCR1_MWID_1

#define FSMC_BCR1_FACCEN

#define FSMC_BCR1_BURSTEN

#define FSMC_BCR1_WAITPOL

#define FSMC_BCR1_WRAPMOD

#define FSMC_BCR1_WAITCFG

#define FSMC_BCR1_WREN

#define FSMC_BCR1_WAITEN

#define FSMC_BCR1_EXTMOD

#define FSMC_BCR1_ASYNCWAIT

#define FSMC_BCR1_CBURSTRW

#define FSMC_BCR2_MBKEN

#define FSMC_BCR2_MUXEN

#define FSMC_BCR2_MTYP

#define FSMC_BCR2_MTYP_0

#define FSMC_BCR2_MTYP_1

#define FSMC_BCR2_MWID

#define FSMC_BCR2_MWID_0

#define FSMC_BCR2_MWID_1

#define FSMC_BCR2_FACCEN

#define FSMC_BCR2_BURSTEN

#define FSMC_BCR2_WAITPOL

#define FSMC_BCR2_WRAPMOD

#define FSMC_BCR2_WAITCFG

#define FSMC_BCR2_WREN

#define FSMC_BCR2_WAITEN

#define FSMC_BCR2_EXTMOD

#define FSMC_BCR2_ASYNCWAIT

#define FSMC_BCR2_CBURSTRW

#define FSMC_BCR3_MBKEN

#define FSMC_BCR3_MUXEN

#define FSMC_BCR3_MTYP

#define FSMC_BCR3_MTYP_0

#define FSMC_BCR3_MTYP_1

#define FSMC_BCR3_MWID

#define FSMC_BCR3_MWID_0

#define FSMC_BCR3_MWID_1

#define FSMC_BCR3_FACCEN

#define FSMC_BCR3_BURSTEN

#define FSMC_BCR3_WAITPOL

#define FSMC_BCR3_WRAPMOD

#define FSMC_BCR3_WAITCFG

#define FSMC_BCR3_WREN

#define FSMC_BCR3_WAITEN

#define FSMC_BCR3_EXTMOD

#define FSMC_BCR3_ASYNCWAIT

#define FSMC_BCR3_CBURSTRW

#define FSMC_BCR4_MBKEN

#define FSMC_BCR4_MUXEN

#define FSMC_BCR4_MTYP

#define FSMC_BCR4_MTYP_0

#define FSMC_BCR4_MTYP_1

#define FSMC_BCR4_MWID

#define FSMC_BCR4_MWID_0

#define FSMC_BCR4_MWID_1

#define FSMC_BCR4_FACCEN

#define FSMC_BCR4_BURSTEN

#define FSMC_BCR4_WAITPOL

#define FSMC_BCR4_WRAPMOD

#define FSMC_BCR4_WAITCFG

#define FSMC_BCR4_WREN

#define FSMC_BCR4_WAITEN

#define FSMC_BCR4_EXTMOD

#define FSMC_BCR4_ASYNCWAIT

#define FSMC_BCR4_CBURSTRW

#define FSMC_BTR1_ADDSET

#define FSMC_BTR1_ADDSET_0

#define FSMC_BTR1_ADDSET_1

#define FSMC_BTR1_ADDSET_2

#define FSMC_BTR1_ADDSET_3

#define FSMC_BTR1_ADDHLD

#define FSMC_BTR1_ADDHLD_0

#define FSMC_BTR1_ADDHLD_1

#define FSMC_BTR1_ADDHLD_2

#define FSMC_BTR1_ADDHLD_3

#define FSMC_BTR1_DATAST

#define FSMC_BTR1_DATAST_0

#define FSMC_BTR1_DATAST_1

#define FSMC_BTR1_DATAST_2

#define FSMC_BTR1_DATAST_3

#define FSMC_BTR1_BUSTURN

#define FSMC_BTR1_BUSTURN_0

#define FSMC_BTR1_BUSTURN_1

#define FSMC_BTR1_BUSTURN_2

#define FSMC_BTR1_BUSTURN_3

#define FSMC_BTR1_CLKDIV

#define FSMC_BTR1_CLKDIV_0

#define FSMC_BTR1_CLKDIV_1

#define FSMC_BTR1_CLKDIV_2

#define FSMC_BTR1_CLKDIV_3

#define FSMC_BTR1_DATLAT

#define FSMC_BTR1_DATLAT_0

#define FSMC_BTR1_DATLAT_1

#define FSMC_BTR1_DATLAT_2

#define FSMC_BTR1_DATLAT_3

#define FSMC_BTR1_ACCMOD

#define FSMC_BTR1_ACCMOD_0

#define FSMC_BTR1_ACCMOD_1

#define FSMC_BTR2_ADDSET

#define FSMC_BTR2_ADDSET_0

#define FSMC_BTR2_ADDSET_1

#define FSMC_BTR2_ADDSET_2

#define FSMC_BTR2_ADDSET_3

#define FSMC_BTR2_ADDHLD

#define FSMC_BTR2_ADDHLD_0

#define FSMC_BTR2_ADDHLD_1

#define FSMC_BTR2_ADDHLD_2

#define FSMC_BTR2_ADDHLD_3

#define FSMC_BTR2_DATAST

#define FSMC_BTR2_DATAST_0

#define FSMC_BTR2_DATAST_1

#define FSMC_BTR2_DATAST_2

#define FSMC_BTR2_DATAST_3

#define FSMC_BTR2_BUSTURN

#define FSMC_BTR2_BUSTURN_0

#define FSMC_BTR2_BUSTURN_1

#define FSMC_BTR2_BUSTURN_2

#define FSMC_BTR2_BUSTURN_3

#define FSMC_BTR2_CLKDIV

#define FSMC_BTR2_CLKDIV_0

#define FSMC_BTR2_CLKDIV_1

#define FSMC_BTR2_CLKDIV_2

#define FSMC_BTR2_CLKDIV_3

#define FSMC_BTR2_DATLAT

#define FSMC_BTR2_DATLAT_0

#define FSMC_BTR2_DATLAT_1

#define FSMC_BTR2_DATLAT_2

#define FSMC_BTR2_DATLAT_3

#define FSMC_BTR2_ACCMOD

#define FSMC_BTR2_ACCMOD_0

#define FSMC_BTR2_ACCMOD_1

#define FSMC_BTR3_ADDSET

#define FSMC_BTR3_ADDSET_0

#define FSMC_BTR3_ADDSET_1

#define FSMC_BTR3_ADDSET_2

#define FSMC_BTR3_ADDSET_3

#define FSMC_BTR3_ADDHLD

#define FSMC_BTR3_ADDHLD_0

#define FSMC_BTR3_ADDHLD_1

#define FSMC_BTR3_ADDHLD_2

#define FSMC_BTR3_ADDHLD_3

#define FSMC_BTR3_DATAST

#define FSMC_BTR3_DATAST_0

#define FSMC_BTR3_DATAST_1

#define FSMC_BTR3_DATAST_2

#define FSMC_BTR3_DATAST_3

#define FSMC_BTR3_BUSTURN

#define FSMC_BTR3_BUSTURN_0

#define FSMC_BTR3_BUSTURN_1

#define FSMC_BTR3_BUSTURN_2

#define FSMC_BTR3_BUSTURN_3

#define FSMC_BTR3_CLKDIV

#define FSMC_BTR3_CLKDIV_0

#define FSMC_BTR3_CLKDIV_1

#define FSMC_BTR3_CLKDIV_2

#define FSMC_BTR3_CLKDIV_3

#define FSMC_BTR3_DATLAT

#define FSMC_BTR3_DATLAT_0

#define FSMC_BTR3_DATLAT_1

#define FSMC_BTR3_DATLAT_2

#define FSMC_BTR3_DATLAT_3

#define FSMC_BTR3_ACCMOD

#define FSMC_BTR3_ACCMOD_0

#define FSMC_BTR3_ACCMOD_1

#define FSMC_BTR4_ADDSET

#define FSMC_BTR4_ADDSET_0

#define FSMC_BTR4_ADDSET_1

#define FSMC_BTR4_ADDSET_2

#define FSMC_BTR4_ADDSET_3

#define FSMC_BTR4_ADDHLD

#define FSMC_BTR4_ADDHLD_0

#define FSMC_BTR4_ADDHLD_1

#define FSMC_BTR4_ADDHLD_2

#define FSMC_BTR4_ADDHLD_3

#define FSMC_BTR4_DATAST

#define FSMC_BTR4_DATAST_0

#define FSMC_BTR4_DATAST_1

#define FSMC_BTR4_DATAST_2

#define FSMC_BTR4_DATAST_3

#define FSMC_BTR4_BUSTURN

#define FSMC_BTR4_BUSTURN_0

#define FSMC_BTR4_BUSTURN_1

#define FSMC_BTR4_BUSTURN_2

#define FSMC_BTR4_BUSTURN_3

#define FSMC_BTR4_CLKDIV

#define FSMC_BTR4_CLKDIV_0

#define FSMC_BTR4_CLKDIV_1

#define FSMC_BTR4_CLKDIV_2

#define FSMC_BTR4_CLKDIV_3

#define FSMC_BTR4_DATLAT

#define FSMC_BTR4_DATLAT_0

#define FSMC_BTR4_DATLAT_1

#define FSMC_BTR4_DATLAT_2

#define FSMC_BTR4_DATLAT_3

#define FSMC_BTR4_ACCMOD

#define FSMC_BTR4_ACCMOD_0

#define FSMC_BTR4_ACCMOD_1

#define FSMC_BWTR1_ADDSET

#define FSMC_BWTR1_ADDSET_0

#define FSMC_BWTR1_ADDSET_1

#define FSMC_BWTR1_ADDSET_2

#define FSMC_BWTR1_ADDSET_3

#define FSMC_BWTR1_ADDHLD

#define FSMC_BWTR1_ADDHLD_0

#define FSMC_BWTR1_ADDHLD_1

#define FSMC_BWTR1_ADDHLD_2

#define FSMC_BWTR1_ADDHLD_3

#define FSMC_BWTR1_DATAST

#define FSMC_BWTR1_DATAST_0

#define FSMC_BWTR1_DATAST_1

#define FSMC_BWTR1_DATAST_2

#define FSMC_BWTR1_DATAST_3

#define FSMC_BWTR1_CLKDIV

#define FSMC_BWTR1_CLKDIV_0

#define FSMC_BWTR1_CLKDIV_1

#define FSMC_BWTR1_CLKDIV_2

#define FSMC_BWTR1_CLKDIV_3

#define FSMC_BWTR1_DATLAT

#define FSMC_BWTR1_DATLAT_0

#define FSMC_BWTR1_DATLAT_1

#define FSMC_BWTR1_DATLAT_2

#define FSMC_BWTR1_DATLAT_3

#define FSMC_BWTR1_ACCMOD

#define FSMC_BWTR1_ACCMOD_0

#define FSMC_BWTR1_ACCMOD_1

#define FSMC_BWTR2_ADDSET

#define FSMC_BWTR2_ADDSET_0

#define FSMC_BWTR2_ADDSET_1

#define FSMC_BWTR2_ADDSET_2

#define FSMC_BWTR2_ADDSET_3

#define FSMC_BWTR2_ADDHLD

#define FSMC_BWTR2_ADDHLD_0

#define FSMC_BWTR2_ADDHLD_1

#define FSMC_BWTR2_ADDHLD_2

#define FSMC_BWTR2_ADDHLD_3

#define FSMC_BWTR2_DATAST

#define FSMC_BWTR2_DATAST_0

#define FSMC_BWTR2_DATAST_1

#define FSMC_BWTR2_DATAST_2

#define FSMC_BWTR2_DATAST_3

#define FSMC_BWTR2_CLKDIV

#define FSMC_BWTR2_CLKDIV_0

#define FSMC_BWTR2_CLKDIV_1

#define FSMC_BWTR2_CLKDIV_2

#define FSMC_BWTR2_CLKDIV_3

#define FSMC_BWTR2_DATLAT

#define FSMC_BWTR2_DATLAT_0

#define FSMC_BWTR2_DATLAT_1

#define FSMC_BWTR2_DATLAT_2

#define FSMC_BWTR2_DATLAT_3

#define FSMC_BWTR2_ACCMOD

#define FSMC_BWTR2_ACCMOD_0

#define FSMC_BWTR2_ACCMOD_1

#define FSMC_BWTR3_ADDSET

#define FSMC_BWTR3_ADDSET_0

#define FSMC_BWTR3_ADDSET_1

#define FSMC_BWTR3_ADDSET_2

#define FSMC_BWTR3_ADDSET_3

#define FSMC_BWTR3_ADDHLD

#define FSMC_BWTR3_ADDHLD_0

#define FSMC_BWTR3_ADDHLD_1

#define FSMC_BWTR3_ADDHLD_2

#define FSMC_BWTR3_ADDHLD_3

#define FSMC_BWTR3_DATAST

#define FSMC_BWTR3_DATAST_0

#define FSMC_BWTR3_DATAST_1

#define FSMC_BWTR3_DATAST_2

#define FSMC_BWTR3_DATAST_3

#define FSMC_BWTR3_CLKDIV

#define FSMC_BWTR3_CLKDIV_0

#define FSMC_BWTR3_CLKDIV_1

#define FSMC_BWTR3_CLKDIV_2

#define FSMC_BWTR3_CLKDIV_3

#define FSMC_BWTR3_DATLAT

#define FSMC_BWTR3_DATLAT_0

#define FSMC_BWTR3_DATLAT_1

#define FSMC_BWTR3_DATLAT_2

#define FSMC_BWTR3_DATLAT_3

#define FSMC_BWTR3_ACCMOD

#define FSMC_BWTR3_ACCMOD_0

#define FSMC_BWTR3_ACCMOD_1

#define FSMC_BWTR4_ADDSET

#define FSMC_BWTR4_ADDSET_0

#define FSMC_BWTR4_ADDSET_1

#define FSMC_BWTR4_ADDSET_2

#define FSMC_BWTR4_ADDSET_3

#define FSMC_BWTR4_ADDHLD

#define FSMC_BWTR4_ADDHLD_0

#define FSMC_BWTR4_ADDHLD_1

#define FSMC_BWTR4_ADDHLD_2

#define FSMC_BWTR4_ADDHLD_3

#define FSMC_BWTR4_DATAST

#define FSMC_BWTR4_DATAST_0

#define FSMC_BWTR4_DATAST_1

#define FSMC_BWTR4_DATAST_2

#define FSMC_BWTR4_DATAST_3

#define FSMC_BWTR4_CLKDIV

#define FSMC_BWTR4_CLKDIV_0

#define FSMC_BWTR4_CLKDIV_1

#define FSMC_BWTR4_CLKDIV_2

#define FSMC_BWTR4_CLKDIV_3

#define FSMC_BWTR4_DATLAT

#define FSMC_BWTR4_DATLAT_0

#define FSMC_BWTR4_DATLAT_1

#define FSMC_BWTR4_DATLAT_2

#define FSMC_BWTR4_DATLAT_3

#define FSMC_BWTR4_ACCMOD

#define FSMC_BWTR4_ACCMOD_0

#define FSMC_BWTR4_ACCMOD_1

#define FSMC_PCR2_PWAITEN

#define FSMC_PCR2_PBKEN

#define FSMC_PCR2_PTYP

#define FSMC_PCR2_PWID

#define FSMC_PCR2_PWID_0

#define FSMC_PCR2_PWID_1

#define FSMC_PCR2_ECCEN

#define FSMC_PCR2_TCLR

#define FSMC_PCR2_TCLR_0

#define FSMC_PCR2_TCLR_1

#define FSMC_PCR2_TCLR_2

#define FSMC_PCR2_TCLR_3

#define FSMC_PCR2_TAR

#define FSMC_PCR2_TAR_0

#define FSMC_PCR2_TAR_1

#define FSMC_PCR2_TAR_2

#define FSMC_PCR2_TAR_3

#define FSMC_PCR2_ECCPS

#define FSMC_PCR2_ECCPS_0

#define FSMC_PCR2_ECCPS_1

#define FSMC_PCR2_ECCPS_2

#define FSMC_PCR3_PWAITEN

#define FSMC_PCR3_PBKEN

#define FSMC_PCR3_PTYP

#define FSMC_PCR3_PWID

#define FSMC_PCR3_PWID_0

#define FSMC_PCR3_PWID_1

#define FSMC_PCR3_ECCEN

#define FSMC_PCR3_TCLR

#define FSMC_PCR3_TCLR_0

#define FSMC_PCR3_TCLR_1

#define FSMC_PCR3_TCLR_2

#define FSMC_PCR3_TCLR_3

#define FSMC_PCR3_TAR

#define FSMC_PCR3_TAR_0

#define FSMC_PCR3_TAR_1

#define FSMC_PCR3_TAR_2

#define FSMC_PCR3_TAR_3

#define FSMC_PCR3_ECCPS

#define FSMC_PCR3_ECCPS_0

#define FSMC_PCR3_ECCPS_1

#define FSMC_PCR3_ECCPS_2

#define FSMC_PCR4_PWAITEN

#define FSMC_PCR4_PBKEN

#define FSMC_PCR4_PTYP

#define FSMC_PCR4_PWID

#define FSMC_PCR4_PWID_0

#define FSMC_PCR4_PWID_1

#define FSMC_PCR4_ECCEN

#define FSMC_PCR4_TCLR

#define FSMC_PCR4_TCLR_0

#define FSMC_PCR4_TCLR_1

#define FSMC_PCR4_TCLR_2

#define FSMC_PCR4_TCLR_3

#define FSMC_PCR4_TAR

#define FSMC_PCR4_TAR_0

#define FSMC_PCR4_TAR_1

#define FSMC_PCR4_TAR_2

#define FSMC_PCR4_TAR_3

#define FSMC_PCR4_ECCPS

#define FSMC_PCR4_ECCPS_0

#define FSMC_PCR4_ECCPS_1

#define FSMC_PCR4_ECCPS_2

#define FSMC_SR2_IRS

#define FSMC_SR2_ILS

#define FSMC_SR2_IFS

#define FSMC_SR2_IREN

#define FSMC_SR2_ILEN

#define FSMC_SR2_IFEN

#define FSMC_SR2_FEMPT

#define FSMC_SR3_IRS

#define FSMC_SR3_ILS

#define FSMC_SR3_IFS

#define FSMC_SR3_IREN

#define FSMC_SR3_ILEN

#define FSMC_SR3_IFEN

#define FSMC_SR3_FEMPT

#define FSMC_SR4_IRS

#define FSMC_SR4_ILS

#define FSMC_SR4_IFS

#define FSMC_SR4_IREN

#define FSMC_SR4_ILEN

#define FSMC_SR4_IFEN

#define FSMC_SR4_FEMPT

#define FSMC_PMEM2_MEMSET2

#define FSMC_PMEM2_MEMSET2_0

#define FSMC_PMEM2_MEMSET2_1

#define FSMC_PMEM2_MEMSET2_2

#define FSMC_PMEM2_MEMSET2_3

#define FSMC_PMEM2_MEMSET2_4

#define FSMC_PMEM2_MEMSET2_5

#define FSMC_PMEM2_MEMSET2_6

#define FSMC_PMEM2_MEMSET2_7

#define FSMC_PMEM2_MEMWAIT2

#define FSMC_PMEM2_MEMWAIT2_0

#define FSMC_PMEM2_MEMWAIT2_1

#define FSMC_PMEM2_MEMWAIT2_2

#define FSMC_PMEM2_MEMWAIT2_3

#define FSMC_PMEM2_MEMWAIT2_4

#define FSMC_PMEM2_MEMWAIT2_5

#define FSMC_PMEM2_MEMWAIT2_6

#define FSMC_PMEM2_MEMWAIT2_7

#define FSMC_PMEM2_MEMHOLD2

#define FSMC_PMEM2_MEMHOLD2_0

#define FSMC_PMEM2_MEMHOLD2_1

#define FSMC_PMEM2_MEMHOLD2_2

#define FSMC_PMEM2_MEMHOLD2_3

#define FSMC_PMEM2_MEMHOLD2_4

#define FSMC_PMEM2_MEMHOLD2_5

#define FSMC_PMEM2_MEMHOLD2_6

#define FSMC_PMEM2_MEMHOLD2_7

#define FSMC_PMEM2_MEMHIZ2

#define FSMC_PMEM2_MEMHIZ2_0

#define FSMC_PMEM2_MEMHIZ2_1

#define FSMC_PMEM2_MEMHIZ2_2

#define FSMC_PMEM2_MEMHIZ2_3

#define FSMC_PMEM2_MEMHIZ2_4

#define FSMC_PMEM2_MEMHIZ2_5

#define FSMC_PMEM2_MEMHIZ2_6

#define FSMC_PMEM2_MEMHIZ2_7

#define FSMC_PMEM3_MEMSET3

#define FSMC_PMEM3_MEMSET3_0

#define FSMC_PMEM3_MEMSET3_1

#define FSMC_PMEM3_MEMSET3_2

#define FSMC_PMEM3_MEMSET3_3

#define FSMC_PMEM3_MEMSET3_4

#define FSMC_PMEM3_MEMSET3_5

#define FSMC_PMEM3_MEMSET3_6

#define FSMC_PMEM3_MEMSET3_7

#define FSMC_PMEM3_MEMWAIT3

#define FSMC_PMEM3_MEMWAIT3_0

#define FSMC_PMEM3_MEMWAIT3_1

#define FSMC_PMEM3_MEMWAIT3_2

#define FSMC_PMEM3_MEMWAIT3_3

#define FSMC_PMEM3_MEMWAIT3_4

#define FSMC_PMEM3_MEMWAIT3_5

#define FSMC_PMEM3_MEMWAIT3_6

#define FSMC_PMEM3_MEMWAIT3_7

#define FSMC_PMEM3_MEMHOLD3

#define FSMC_PMEM3_MEMHOLD3_0

#define FSMC_PMEM3_MEMHOLD3_1

#define FSMC_PMEM3_MEMHOLD3_2

#define FSMC_PMEM3_MEMHOLD3_3

#define FSMC_PMEM3_MEMHOLD3_4

#define FSMC_PMEM3_MEMHOLD3_5

#define FSMC_PMEM3_MEMHOLD3_6

#define FSMC_PMEM3_MEMHOLD3_7

#define FSMC_PMEM3_MEMHIZ3

#define FSMC_PMEM3_MEMHIZ3_0

#define FSMC_PMEM3_MEMHIZ3_1

#define FSMC_PMEM3_MEMHIZ3_2

#define FSMC_PMEM3_MEMHIZ3_3

#define FSMC_PMEM3_MEMHIZ3_4

#define FSMC_PMEM3_MEMHIZ3_5

#define FSMC_PMEM3_MEMHIZ3_6

#define FSMC_PMEM3_MEMHIZ3_7

#define FSMC_PMEM4_MEMSET4

#define FSMC_PMEM4_MEMSET4_0

#define FSMC_PMEM4_MEMSET4_1

#define FSMC_PMEM4_MEMSET4_2

#define FSMC_PMEM4_MEMSET4_3

#define FSMC_PMEM4_MEMSET4_4

#define FSMC_PMEM4_MEMSET4_5

#define FSMC_PMEM4_MEMSET4_6

#define FSMC_PMEM4_MEMSET4_7

#define FSMC_PMEM4_MEMWAIT4

#define FSMC_PMEM4_MEMWAIT4_0

#define FSMC_PMEM4_MEMWAIT4_1

#define FSMC_PMEM4_MEMWAIT4_2

#define FSMC_PMEM4_MEMWAIT4_3

#define FSMC_PMEM4_MEMWAIT4_4

#define FSMC_PMEM4_MEMWAIT4_5

#define FSMC_PMEM4_MEMWAIT4_6

#define FSMC_PMEM4_MEMWAIT4_7

#define FSMC_PMEM4_MEMHOLD4

#define FSMC_PMEM4_MEMHOLD4_0

#define FSMC_PMEM4_MEMHOLD4_1

#define FSMC_PMEM4_MEMHOLD4_2

#define FSMC_PMEM4_MEMHOLD4_3

#define FSMC_PMEM4_MEMHOLD4_4

#define FSMC_PMEM4_MEMHOLD4_5

#define FSMC_PMEM4_MEMHOLD4_6

#define FSMC_PMEM4_MEMHOLD4_7

#define FSMC_PMEM4_MEMHIZ4

#define FSMC_PMEM4_MEMHIZ4_0

#define FSMC_PMEM4_MEMHIZ4_1

#define FSMC_PMEM4_MEMHIZ4_2

#define FSMC_PMEM4_MEMHIZ4_3

#define FSMC_PMEM4_MEMHIZ4_4

#define FSMC_PMEM4_MEMHIZ4_5

#define FSMC_PMEM4_MEMHIZ4_6

#define FSMC_PMEM4_MEMHIZ4_7

#define FSMC_PATT2_ATTSET2

#define FSMC_PATT2_ATTSET2_0

#define FSMC_PATT2_ATTSET2_1

#define FSMC_PATT2_ATTSET2_2

#define FSMC_PATT2_ATTSET2_3

#define FSMC_PATT2_ATTSET2_4

#define FSMC_PATT2_ATTSET2_5

#define FSMC_PATT2_ATTSET2_6

#define FSMC_PATT2_ATTSET2_7

#define FSMC_PATT2_ATTWAIT2

#define FSMC_PATT2_ATTWAIT2_0

#define FSMC_PATT2_ATTWAIT2_1

#define FSMC_PATT2_ATTWAIT2_2

#define FSMC_PATT2_ATTWAIT2_3

#define FSMC_PATT2_ATTWAIT2_4

#define FSMC_PATT2_ATTWAIT2_5

#define FSMC_PATT2_ATTWAIT2_6

#define FSMC_PATT2_ATTWAIT2_7

#define FSMC_PATT2_ATTHOLD2

#define FSMC_PATT2_ATTHOLD2_0

#define FSMC_PATT2_ATTHOLD2_1

#define FSMC_PATT2_ATTHOLD2_2

#define FSMC_PATT2_ATTHOLD2_3

#define FSMC_PATT2_ATTHOLD2_4

#define FSMC_PATT2_ATTHOLD2_5

#define FSMC_PATT2_ATTHOLD2_6

#define FSMC_PATT2_ATTHOLD2_7

#define FSMC_PATT2_ATTHIZ2

#define FSMC_PATT2_ATTHIZ2_0

#define FSMC_PATT2_ATTHIZ2_1

#define FSMC_PATT2_ATTHIZ2_2

#define FSMC_PATT2_ATTHIZ2_3

#define FSMC_PATT2_ATTHIZ2_4

#define FSMC_PATT2_ATTHIZ2_5

#define FSMC_PATT2_ATTHIZ2_6

#define FSMC_PATT2_ATTHIZ2_7

#define FSMC_PATT3_ATTSET3

#define FSMC_PATT3_ATTSET3_0

#define FSMC_PATT3_ATTSET3_1

#define FSMC_PATT3_ATTSET3_2

#define FSMC_PATT3_ATTSET3_3

#define FSMC_PATT3_ATTSET3_4

#define FSMC_PATT3_ATTSET3_5

#define FSMC_PATT3_ATTSET3_6

#define FSMC_PATT3_ATTSET3_7

#define FSMC_PATT3_ATTWAIT3

#define FSMC_PATT3_ATTWAIT3_0

#define FSMC_PATT3_ATTWAIT3_1

#define FSMC_PATT3_ATTWAIT3_2

#define FSMC_PATT3_ATTWAIT3_3

#define FSMC_PATT3_ATTWAIT3_4

#define FSMC_PATT3_ATTWAIT3_5

#define FSMC_PATT3_ATTWAIT3_6

#define FSMC_PATT3_ATTWAIT3_7

#define FSMC_PATT3_ATTHOLD3

#define FSMC_PATT3_ATTHOLD3_0

#define FSMC_PATT3_ATTHOLD3_1

#define FSMC_PATT3_ATTHOLD3_2

#define FSMC_PATT3_ATTHOLD3_3

#define FSMC_PATT3_ATTHOLD3_4

#define FSMC_PATT3_ATTHOLD3_5

#define FSMC_PATT3_ATTHOLD3_6

#define FSMC_PATT3_ATTHOLD3_7

#define FSMC_PATT3_ATTHIZ3

#define FSMC_PATT3_ATTHIZ3_0

#define FSMC_PATT3_ATTHIZ3_1

#define FSMC_PATT3_ATTHIZ3_2

#define FSMC_PATT3_ATTHIZ3_3

#define FSMC_PATT3_ATTHIZ3_4

#define FSMC_PATT3_ATTHIZ3_5

#define FSMC_PATT3_ATTHIZ3_6

#define FSMC_PATT3_ATTHIZ3_7

#define FSMC_PATT4_ATTSET4

#define FSMC_PATT4_ATTSET4_0

#define FSMC_PATT4_ATTSET4_1

#define FSMC_PATT4_ATTSET4_2

#define FSMC_PATT4_ATTSET4_3

#define FSMC_PATT4_ATTSET4_4

#define FSMC_PATT4_ATTSET4_5

#define FSMC_PATT4_ATTSET4_6

#define FSMC_PATT4_ATTSET4_7

#define FSMC_PATT4_ATTWAIT4

#define FSMC_PATT4_ATTWAIT4_0

#define FSMC_PATT4_ATTWAIT4_1

#define FSMC_PATT4_ATTWAIT4_2

#define FSMC_PATT4_ATTWAIT4_3

#define FSMC_PATT4_ATTWAIT4_4

#define FSMC_PATT4_ATTWAIT4_5

#define FSMC_PATT4_ATTWAIT4_6

#define FSMC_PATT4_ATTWAIT4_7

#define FSMC_PATT4_ATTHOLD4

#define FSMC_PATT4_ATTHOLD4_0

#define FSMC_PATT4_ATTHOLD4_1

#define FSMC_PATT4_ATTHOLD4_2

#define FSMC_PATT4_ATTHOLD4_3

#define FSMC_PATT4_ATTHOLD4_4

#define FSMC_PATT4_ATTHOLD4_5

#define FSMC_PATT4_ATTHOLD4_6

#define FSMC_PATT4_ATTHOLD4_7

#define FSMC_PATT4_ATTHIZ4

#define FSMC_PATT4_ATTHIZ4_0

#define FSMC_PATT4_ATTHIZ4_1

#define FSMC_PATT4_ATTHIZ4_2

#define FSMC_PATT4_ATTHIZ4_3

#define FSMC_PATT4_ATTHIZ4_4

#define FSMC_PATT4_ATTHIZ4_5

#define FSMC_PATT4_ATTHIZ4_6

#define FSMC_PATT4_ATTHIZ4_7

#define FSMC_PIO4_IOSET4

#define FSMC_PIO4_IOSET4_0

#define FSMC_PIO4_IOSET4_1

#define FSMC_PIO4_IOSET4_2

#define FSMC_PIO4_IOSET4_3

#define FSMC_PIO4_IOSET4_4

#define FSMC_PIO4_IOSET4_5

#define FSMC_PIO4_IOSET4_6

#define FSMC_PIO4_IOSET4_7

#define FSMC_PIO4_IOWAIT4

#define FSMC_PIO4_IOWAIT4_0

#define FSMC_PIO4_IOWAIT4_1

#define FSMC_PIO4_IOWAIT4_2

#define FSMC_PIO4_IOWAIT4_3

#define FSMC_PIO4_IOWAIT4_4

#define FSMC_PIO4_IOWAIT4_5

#define FSMC_PIO4_IOWAIT4_6

#define FSMC_PIO4_IOWAIT4_7

#define FSMC_PIO4_IOHOLD4

#define FSMC_PIO4_IOHOLD4_0

#define FSMC_PIO4_IOHOLD4_1

#define FSMC_PIO4_IOHOLD4_2

#define FSMC_PIO4_IOHOLD4_3

#define FSMC_PIO4_IOHOLD4_4

#define FSMC_PIO4_IOHOLD4_5

#define FSMC_PIO4_IOHOLD4_6

#define FSMC_PIO4_IOHOLD4_7

#define FSMC_PIO4_IOHIZ4

#define FSMC_PIO4_IOHIZ4_0

#define FSMC_PIO4_IOHIZ4_1

#define FSMC_PIO4_IOHIZ4_2

#define FSMC_PIO4_IOHIZ4_3

#define FSMC_PIO4_IOHIZ4_4

#define FSMC_PIO4_IOHIZ4_5

#define FSMC_PIO4_IOHIZ4_6

#define FSMC_PIO4_IOHIZ4_7

#define FSMC_ECCR2_ECC2

#define FSMC_ECCR3_ECC3

#define GPIO_MODER_MODER0

#define GPIO_MODER_MODER0_0

#define GPIO_MODER_MODER0_1

#define GPIO_MODER_MODER1

#define GPIO_MODER_MODER1_0

#define GPIO_MODER_MODER1_1

#define GPIO_MODER_MODER2

#define GPIO_MODER_MODER2_0

#define GPIO_MODER_MODER2_1

#define GPIO_MODER_MODER3

#define GPIO_MODER_MODER3_0

#define GPIO_MODER_MODER3_1

#define GPIO_MODER_MODER4

#define GPIO_MODER_MODER4_0

#define GPIO_MODER_MODER4_1

#define GPIO_MODER_MODER5

#define GPIO_MODER_MODER5_0

#define GPIO_MODER_MODER5_1

#define GPIO_MODER_MODER6

#define GPIO_MODER_MODER6_0

#define GPIO_MODER_MODER6_1

#define GPIO_MODER_MODER7

#define GPIO_MODER_MODER7_0

#define GPIO_MODER_MODER7_1

#define GPIO_MODER_MODER8

#define GPIO_MODER_MODER8_0

#define GPIO_MODER_MODER8_1

#define GPIO_MODER_MODER9

#define GPIO_MODER_MODER9_0

#define GPIO_MODER_MODER9_1

#define GPIO_MODER_MODER10

#define GPIO_MODER_MODER10_0

#define GPIO_MODER_MODER10_1

#define GPIO_MODER_MODER11

#define GPIO_MODER_MODER11_0

#define GPIO_MODER_MODER11_1

#define GPIO_MODER_MODER12

#define GPIO_MODER_MODER12_0

#define GPIO_MODER_MODER12_1

#define GPIO_MODER_MODER13

#define GPIO_MODER_MODER13_0

#define GPIO_MODER_MODER13_1

#define GPIO_MODER_MODER14

#define GPIO_MODER_MODER14_0

#define GPIO_MODER_MODER14_1

#define GPIO_MODER_MODER15

#define GPIO_MODER_MODER15_0

#define GPIO_MODER_MODER15_1

#define GPIO_OTYPER_OT_0

#define GPIO_OTYPER_OT_1

#define GPIO_OTYPER_OT_2

#define GPIO_OTYPER_OT_3

#define GPIO_OTYPER_OT_4

#define GPIO_OTYPER_OT_5

#define GPIO_OTYPER_OT_6

#define GPIO_OTYPER_OT_7

#define GPIO_OTYPER_OT_8

#define GPIO_OTYPER_OT_9

#define GPIO_OTYPER_OT_10

#define GPIO_OTYPER_OT_11

#define GPIO_OTYPER_OT_12

#define GPIO_OTYPER_OT_13

#define GPIO_OTYPER_OT_14

#define GPIO_OTYPER_OT_15

#define GPIO_OSPEEDER_OSPEEDR0

#define GPIO_OSPEEDER_OSPEEDR0_0

#define GPIO_OSPEEDER_OSPEEDR0_1

#define GPIO_OSPEEDER_OSPEEDR1

#define GPIO_OSPEEDER_OSPEEDR1_0

#define GPIO_OSPEEDER_OSPEEDR1_1

#define GPIO_OSPEEDER_OSPEEDR2

#define GPIO_OSPEEDER_OSPEEDR2_0

#define GPIO_OSPEEDER_OSPEEDR2_1

#define GPIO_OSPEEDER_OSPEEDR3

#define GPIO_OSPEEDER_OSPEEDR3_0

#define GPIO_OSPEEDER_OSPEEDR3_1

#define GPIO_OSPEEDER_OSPEEDR4

#define GPIO_OSPEEDER_OSPEEDR4_0

#define GPIO_OSPEEDER_OSPEEDR4_1

#define GPIO_OSPEEDER_OSPEEDR5

#define GPIO_OSPEEDER_OSPEEDR5_0

#define GPIO_OSPEEDER_OSPEEDR5_1

#define GPIO_OSPEEDER_OSPEEDR6

#define GPIO_OSPEEDER_OSPEEDR6_0

#define GPIO_OSPEEDER_OSPEEDR6_1

#define GPIO_OSPEEDER_OSPEEDR7

#define GPIO_OSPEEDER_OSPEEDR7_0

#define GPIO_OSPEEDER_OSPEEDR7_1

#define GPIO_OSPEEDER_OSPEEDR8

#define GPIO_OSPEEDER_OSPEEDR8_0

#define GPIO_OSPEEDER_OSPEEDR8_1

#define GPIO_OSPEEDER_OSPEEDR9

#define GPIO_OSPEEDER_OSPEEDR9_0

#define GPIO_OSPEEDER_OSPEEDR9_1

#define GPIO_OSPEEDER_OSPEEDR10

#define GPIO_OSPEEDER_OSPEEDR10_0

#define GPIO_OSPEEDER_OSPEEDR10_1

#define GPIO_OSPEEDER_OSPEEDR11

#define GPIO_OSPEEDER_OSPEEDR11_0

#define GPIO_OSPEEDER_OSPEEDR11_1

#define GPIO_OSPEEDER_OSPEEDR12

#define GPIO_OSPEEDER_OSPEEDR12_0

#define GPIO_OSPEEDER_OSPEEDR12_1

#define GPIO_OSPEEDER_OSPEEDR13

#define GPIO_OSPEEDER_OSPEEDR13_0

#define GPIO_OSPEEDER_OSPEEDR13_1

#define GPIO_OSPEEDER_OSPEEDR14

#define GPIO_OSPEEDER_OSPEEDR14_0

#define GPIO_OSPEEDER_OSPEEDR14_1

#define GPIO_OSPEEDER_OSPEEDR15

#define GPIO_OSPEEDER_OSPEEDR15_0

#define GPIO_OSPEEDER_OSPEEDR15_1

#define GPIO_PUPDR_PUPDR0

#define GPIO_PUPDR_PUPDR0_0

#define GPIO_PUPDR_PUPDR0_1

#define GPIO_PUPDR_PUPDR1

#define GPIO_PUPDR_PUPDR1_0

#define GPIO_PUPDR_PUPDR1_1

#define GPIO_PUPDR_PUPDR2

#define GPIO_PUPDR_PUPDR2_0

#define GPIO_PUPDR_PUPDR2_1

#define GPIO_PUPDR_PUPDR3

#define GPIO_PUPDR_PUPDR3_0

#define GPIO_PUPDR_PUPDR3_1

#define GPIO_PUPDR_PUPDR4

#define GPIO_PUPDR_PUPDR4_0

#define GPIO_PUPDR_PUPDR4_1

#define GPIO_PUPDR_PUPDR5

#define GPIO_PUPDR_PUPDR5_0

#define GPIO_PUPDR_PUPDR5_1

#define GPIO_PUPDR_PUPDR6

#define GPIO_PUPDR_PUPDR6_0

#define GPIO_PUPDR_PUPDR6_1

#define GPIO_PUPDR_PUPDR7

#define GPIO_PUPDR_PUPDR7_0

#define GPIO_PUPDR_PUPDR7_1

#define GPIO_PUPDR_PUPDR8

#define GPIO_PUPDR_PUPDR8_0

#define GPIO_PUPDR_PUPDR8_1

#define GPIO_PUPDR_PUPDR9

#define GPIO_PUPDR_PUPDR9_0

#define GPIO_PUPDR_PUPDR9_1

#define GPIO_PUPDR_PUPDR10

#define GPIO_PUPDR_PUPDR10_0

#define GPIO_PUPDR_PUPDR10_1

#define GPIO_PUPDR_PUPDR11

#define GPIO_PUPDR_PUPDR11_0

#define GPIO_PUPDR_PUPDR11_1

#define GPIO_PUPDR_PUPDR12

#define GPIO_PUPDR_PUPDR12_0

#define GPIO_PUPDR_PUPDR12_1

#define GPIO_PUPDR_PUPDR13

#define GPIO_PUPDR_PUPDR13_0

#define GPIO_PUPDR_PUPDR13_1

#define GPIO_PUPDR_PUPDR14

#define GPIO_PUPDR_PUPDR14_0

#define GPIO_PUPDR_PUPDR14_1

#define GPIO_PUPDR_PUPDR15

#define GPIO_PUPDR_PUPDR15_0

#define GPIO_PUPDR_PUPDR15_1

#define GPIO_OTYPER_IDR_0

#define GPIO_OTYPER_IDR_1

#define GPIO_OTYPER_IDR_2

#define GPIO_OTYPER_IDR_3

#define GPIO_OTYPER_IDR_4

#define GPIO_OTYPER_IDR_5

#define GPIO_OTYPER_IDR_6

#define GPIO_OTYPER_IDR_7

#define GPIO_OTYPER_IDR_8

#define GPIO_OTYPER_IDR_9

#define GPIO_OTYPER_IDR_10

#define GPIO_OTYPER_IDR_11

#define GPIO_OTYPER_IDR_12

#define GPIO_OTYPER_IDR_13

#define GPIO_OTYPER_IDR_14

#define GPIO_OTYPER_IDR_15

#define GPIO_OTYPER_ODR_0

#define GPIO_OTYPER_ODR_1

#define GPIO_OTYPER_ODR_2

#define GPIO_OTYPER_ODR_3

#define GPIO_OTYPER_ODR_4

#define GPIO_OTYPER_ODR_5

#define GPIO_OTYPER_ODR_6

#define GPIO_OTYPER_ODR_7

#define GPIO_OTYPER_ODR_8

#define GPIO_OTYPER_ODR_9

#define GPIO_OTYPER_ODR_10

#define GPIO_OTYPER_ODR_11

#define GPIO_OTYPER_ODR_12

#define GPIO_OTYPER_ODR_13

#define GPIO_OTYPER_ODR_14

#define GPIO_OTYPER_ODR_15

#define GPIO_BSRR_BS_0

#define GPIO_BSRR_BS_1

#define GPIO_BSRR_BS_2

#define GPIO_BSRR_BS_3

#define GPIO_BSRR_BS_4

#define GPIO_BSRR_BS_5

#define GPIO_BSRR_BS_6

#define GPIO_BSRR_BS_7

#define GPIO_BSRR_BS_8

#define GPIO_BSRR_BS_9

#define GPIO_BSRR_BS_10

#define GPIO_BSRR_BS_11

#define GPIO_BSRR_BS_12

#define GPIO_BSRR_BS_13

#define GPIO_BSRR_BS_14

#define GPIO_BSRR_BS_15

#define GPIO_BSRR_BR_0

#define GPIO_BSRR_BR_1

#define GPIO_BSRR_BR_2

#define GPIO_BSRR_BR_3

#define GPIO_BSRR_BR_4

#define GPIO_BSRR_BR_5

#define GPIO_BSRR_BR_6

#define GPIO_BSRR_BR_7

#define GPIO_BSRR_BR_8

#define GPIO_BSRR_BR_9

#define GPIO_BSRR_BR_10

#define GPIO_BSRR_BR_11

#define GPIO_BSRR_BR_12

#define GPIO_BSRR_BR_13

#define GPIO_BSRR_BR_14

#define GPIO_BSRR_BR_15

#define HASH_CR_INIT

#define HASH_CR_DMAE

#define HASH_CR_DATATYPE

#define HASH_CR_DATATYPE_0

#define HASH_CR_DATATYPE_1

#define HASH_CR_MODE

#define HASH_CR_ALGO

#define HASH_CR_NBW

#define HASH_CR_NBW_0

#define HASH_CR_NBW_1

#define HASH_CR_NBW_2

#define HASH_CR_NBW_3

#define HASH_CR_DINNE

#define HASH_CR_LKEY

#define HASH_STR_NBW

#define HASH_STR_NBW_0

#define HASH_STR_NBW_1

#define HASH_STR_NBW_2

#define HASH_STR_NBW_3

#define HASH_STR_NBW_4

#define HASH_STR_DCAL

#define HASH_IMR_DINIM

#define HASH_IMR_DCIM

#define HASH_SR_DINIS

#define HASH_SR_DCIS

#define HASH_SR_DMAS

#define HASH_SR_BUSY

#define I2C_CR1_PE

#define I2C_CR1_SMBUS

#define I2C_CR1_SMBTYPE

#define I2C_CR1_ENARP

#define I2C_CR1_ENPEC

#define I2C_CR1_ENGC

#define I2C_CR1_NOSTRETCH

#define I2C_CR1_START

#define I2C_CR1_STOP

#define I2C_CR1_ACK

#define I2C_CR1_POS

#define I2C_CR1_PEC

#define I2C_CR1_ALERT

#define I2C_CR1_SWRST

#define I2C_CR2_FREQ

#define I2C_CR2_FREQ_0

#define I2C_CR2_FREQ_1

#define I2C_CR2_FREQ_2

#define I2C_CR2_FREQ_3

#define I2C_CR2_FREQ_4

#define I2C_CR2_FREQ_5

#define I2C_CR2_ITERREN

#define I2C_CR2_ITEVTEN

#define I2C_CR2_ITBUFEN

#define I2C_CR2_DMAEN

#define I2C_CR2_LAST

#define I2C_OAR1_ADD1_7

#define I2C_OAR1_ADD8_9

#define I2C_OAR1_ADD0

#define I2C_OAR1_ADD1

#define I2C_OAR1_ADD2

#define I2C_OAR1_ADD3

#define I2C_OAR1_ADD4

#define I2C_OAR1_ADD5

#define I2C_OAR1_ADD6

#define I2C_OAR1_ADD7

#define I2C_OAR1_ADD8

#define I2C_OAR1_ADD9

#define I2C_OAR1_ADDMODE

#define I2C_OAR2_ENDUAL

#define I2C_OAR2_ADD2

#define I2C_DR_DR

#define I2C_SR1_SB

#define I2C_SR1_ADDR

#define I2C_SR1_BTF

#define I2C_SR1_ADD10

#define I2C_SR1_STOPF

#define I2C_SR1_RXNE

#define I2C_SR1_TXE

#define I2C_SR1_BERR

#define I2C_SR1_ARLO

#define I2C_SR1_AF

#define I2C_SR1_OVR

#define I2C_SR1_PECERR

#define I2C_SR1_TIMEOUT

#define I2C_SR1_SMBALERT

#define I2C_SR2_MSL

#define I2C_SR2_BUSY

#define I2C_SR2_TRA

#define I2C_SR2_GENCALL

#define I2C_SR2_SMBDEFAULT

#define I2C_SR2_SMBHOST

#define I2C_SR2_DUALF

#define I2C_SR2_PEC

#define I2C_CCR_CCR

#define I2C_CCR_DUTY

#define I2C_CCR_FS

#define I2C_TRISE_TRISE

#define IWDG_KR_KEY

#define IWDG_PR_PR

#define IWDG_PR_PR_0

#define IWDG_PR_PR_1

#define IWDG_PR_PR_2

#define IWDG_RLR_RL

#define IWDG_SR_PVU

#define IWDG_SR_RVU

#define PWR_CR_LPDS

#define PWR_CR_PDDS

#define PWR_CR_CWUF

#define PWR_CR_CSBF

#define PWR_CR_PVDE

#define PWR_CR_PLS

#define PWR_CR_PLS_0

#define PWR_CR_PLS_1

#define PWR_CR_PLS_2

#define PWR_CR_PLS_LEV0

#define PWR_CR_PLS_LEV1

#define PWR_CR_PLS_LEV2

#define PWR_CR_PLS_LEV3

#define PWR_CR_PLS_LEV4

#define PWR_CR_PLS_LEV5

#define PWR_CR_PLS_LEV6

#define PWR_CR_PLS_LEV7

#define PWR_CR_DBP

#define PWR_CR_FPDS

#define PWR_CSR_WUF

#define PWR_CSR_SBF

#define PWR_CSR_PVDO

#define PWR_CSR_BRR

#define PWR_CSR_EWUP

#define PWR_CSR_BRE

#define RCC_CR_HSION

#define RCC_CR_HSIRDY

#define RCC_CR_HSITRIM

#define RCC_CR_HSITRIM_0

#define RCC_CR_HSITRIM_1

#define RCC_CR_HSITRIM_2

#define RCC_CR_HSITRIM_3

#define RCC_CR_HSITRIM_4

#define RCC_CR_HSICAL

#define RCC_CR_HSICAL_0

#define RCC_CR_HSICAL_1

#define RCC_CR_HSICAL_2

#define RCC_CR_HSICAL_3

#define RCC_CR_HSICAL_4

#define RCC_CR_HSICAL_5

#define RCC_CR_HSICAL_6

#define RCC_CR_HSICAL_7

#define RCC_CR_HSEON

#define RCC_CR_HSERDY

#define RCC_CR_HSEBYP

#define RCC_CR_CSSON

#define RCC_CR_PLLON

#define RCC_CR_PLLRDY

#define RCC_CR_PLLI2SON

#define RCC_CR_PLLI2SRDY

#define RCC_PLLCFGR_PLLM

#define RCC_PLLCFGR_PLLM_0

#define RCC_PLLCFGR_PLLM_1

#define RCC_PLLCFGR_PLLM_2

#define RCC_PLLCFGR_PLLM_3

#define RCC_PLLCFGR_PLLM_4

#define RCC_PLLCFGR_PLLM_5

#define RCC_PLLCFGR_PLLN

#define RCC_PLLCFGR_PLLN_0

#define RCC_PLLCFGR_PLLN_1

#define RCC_PLLCFGR_PLLN_2

#define RCC_PLLCFGR_PLLN_3

#define RCC_PLLCFGR_PLLN_4

#define RCC_PLLCFGR_PLLN_5

#define RCC_PLLCFGR_PLLN_6

#define RCC_PLLCFGR_PLLN_7

#define RCC_PLLCFGR_PLLN_8

#define RCC_PLLCFGR_PLLP

#define RCC_PLLCFGR_PLLP_0

#define RCC_PLLCFGR_PLLP_1

#define RCC_PLLCFGR_PLLSRC

#define RCC_PLLCFGR_PLLSRC_HSE

#define RCC_PLLCFGR_PLLSRC_HSI

#define RCC_PLLCFGR_PLLQ

#define RCC_PLLCFGR_PLLQ_0

#define RCC_PLLCFGR_PLLQ_1

#define RCC_PLLCFGR_PLLQ_2

#define RCC_PLLCFGR_PLLQ_3

#define RCC_CFGR_SW

#define RCC_CFGR_SW_0

#define RCC_CFGR_SW_1

#define RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_PLL

#define RCC_CFGR_SWS

#define RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_PLL

#define RCC_CFGR_HPRE

#define RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV2

#define RCC_CFGR_HPRE_DIV4

#define RCC_CFGR_HPRE_DIV8

#define RCC_CFGR_HPRE_DIV16

#define RCC_CFGR_HPRE_DIV64

#define RCC_CFGR_HPRE_DIV128

#define RCC_CFGR_HPRE_DIV256

#define RCC_CFGR_HPRE_DIV512

#define RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1_0

#define RCC_CFGR_PPRE1_1

#define RCC_CFGR_PPRE1_2

#define RCC_CFGR_PPRE1_DIV1

#define RCC_CFGR_PPRE1_DIV2

#define RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV8

#define RCC_CFGR_PPRE1_DIV16

#define RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2_0

#define RCC_CFGR_PPRE2_1

#define RCC_CFGR_PPRE2_2

#define RCC_CFGR_PPRE2_DIV1

#define RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV4

#define RCC_CFGR_PPRE2_DIV8

#define RCC_CFGR_PPRE2_DIV16

#define RCC_CFGR_RTCPRE

#define RCC_CFGR_RTCPRE_0

#define RCC_CFGR_RTCPRE_1

#define RCC_CFGR_RTCPRE_2

#define RCC_CFGR_RTCPRE_3

#define RCC_CFGR_RTCPRE_4

#define RCC_CFGR_MCO1

#define RCC_CFGR_MCO1_0

#define RCC_CFGR_MCO1_1

#define RCC_CFGR_I2SSRC

#define RCC_CFGR_MCO1PRE

#define RCC_CFGR_MCO1PRE_0

#define RCC_CFGR_MCO1PRE_1

#define RCC_CFGR_MCO1PRE_2

#define RCC_CFGR_MCO2PRE

#define RCC_CFGR_MCO2PRE_0

#define RCC_CFGR_MCO2PRE_1

#define RCC_CFGR_MCO2PRE_2

#define RCC_CFGR_MCO2

#define RCC_CFGR_MCO2_0

#define RCC_CFGR_MCO2_1

#define RCC_CIR_LSIRDYF

#define RCC_CIR_LSERDYF

#define RCC_CIR_HSIRDYF

#define RCC_CIR_HSERDYF

#define RCC_CIR_PLLRDYF

#define RCC_CIR_PLLI2SRDYF

#define RCC_CIR_CSSF

#define RCC_CIR_LSIRDYIE

#define RCC_CIR_LSERDYIE

#define RCC_CIR_HSIRDYIE

#define RCC_CIR_HSERDYIE

#define RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLI2SRDYIE

#define RCC_CIR_LSIRDYC

#define RCC_CIR_LSERDYC

#define RCC_CIR_HSIRDYC

#define RCC_CIR_HSERDYC

#define RCC_CIR_PLLRDYC

#define RCC_CIR_PLLI2SRDYC

#define RCC_CIR_CSSC

#define RCC_AHB1RSTR_GPIOARST

#define RCC_AHB1RSTR_GPIOBRST

#define RCC_AHB1RSTR_GPIOCRST

#define RCC_AHB1RSTR_GPIODRST

#define RCC_AHB1RSTR_GPIOERST

#define RCC_AHB1RSTR_GPIOFRST

#define RCC_AHB1RSTR_GPIOGRST

#define RCC_AHB1RSTR_GPIOHRST

#define RCC_AHB1RSTR_GPIOIRST

#define RCC_AHB1RSTR_CRCRST

#define RCC_AHB1RSTR_DMA1RST

#define RCC_AHB1RSTR_DMA2RST

#define RCC_AHB1RSTR_ETHMACRST

#define RCC_AHB1RSTR_OTGHRST

#define RCC_AHB2RSTR_DCMIRST

#define RCC_AHB2RSTR_CRYPRST

#define RCC_AHB2RSTR_HSAHRST

#define RCC_AHB2RSTR_RNGRST

#define RCC_AHB2RSTR_OTGFSRST

#define RCC_AHB3RSTR_FSMCRST

#define RCC_APB1RSTR_TIM2RST

#define RCC_APB1RSTR_TIM3RST

#define RCC_APB1RSTR_TIM4RST

#define RCC_APB1RSTR_TIM5RST

#define RCC_APB1RSTR_TIM6RST

#define RCC_APB1RSTR_TIM7RST

#define RCC_APB1RSTR_TIM12RST

#define RCC_APB1RSTR_TIM13RST

#define RCC_APB1RSTR_TIM14RST

#define RCC_APB1RSTR_WWDGEN

#define RCC_APB1RSTR_SPI2RST

#define RCC_APB1RSTR_SPI3RST

#define RCC_APB1RSTR_USART2RST

#define RCC_APB1RSTR_USART3RST

#define RCC_APB1RSTR_UART4RST

#define RCC_APB1RSTR_UART5RST

#define RCC_APB1RSTR_I2C1RST

#define RCC_APB1RSTR_I2C2RST

#define RCC_APB1RSTR_I2C3RST

#define RCC_APB1RSTR_CAN1RST

#define RCC_APB1RSTR_CAN2RST

#define RCC_APB1RSTR_PWRRST

#define RCC_APB1RSTR_DACRST

#define RCC_APB2RSTR_TIM1RST

#define RCC_APB2RSTR_TIM8RST

#define RCC_APB2RSTR_USART1RST

#define RCC_APB2RSTR_USART6RST

#define RCC_APB2RSTR_ADCRST

#define RCC_APB2RSTR_SDIORST

#define RCC_APB2RSTR_SPI1

#define RCC_APB2RSTR_SYSCFGRST

#define RCC_APB2RSTR_TIM9RST

#define RCC_APB2RSTR_TIM10RST

#define RCC_APB2RSTR_TIM11RST

#define RCC_AHB1ENR_GPIOAEN

#define RCC_AHB1ENR_GPIOBEN

#define RCC_AHB1ENR_GPIOCEN

#define RCC_AHB1ENR_GPIODEN

#define RCC_AHB1ENR_GPIOEEN

#define RCC_AHB1ENR_GPIOFEN

#define RCC_AHB1ENR_GPIOGEN

#define RCC_AHB1ENR_GPIOHEN

#define RCC_AHB1ENR_GPIOIEN

#define RCC_AHB1ENR_CRCEN

#define RCC_AHB1ENR_BKPSRAMEN

#define RCC_AHB1ENR_DMA1EN

#define RCC_AHB1ENR_DMA2EN

#define RCC_AHB1ENR_ETHMACEN

#define RCC_AHB1ENR_ETHMACTXEN

#define RCC_AHB1ENR_ETHMACRXEN

#define RCC_AHB1ENR_ETHMACPTPEN

#define RCC_AHB1ENR_OTGHSEN

#define RCC_AHB1ENR_OTGHSULPIEN

#define RCC_AHB2ENR_DCMIEN

#define RCC_AHB2ENR_CRYPEN

#define RCC_AHB2ENR_HASHEN

#define RCC_AHB2ENR_RNGEN

#define RCC_AHB2ENR_OTGFSEN

#define RCC_AHB3ENR_FSMCEN

#define RCC_APB1ENR_TIM2EN

#define RCC_APB1ENR_TIM3EN

#define RCC_APB1ENR_TIM4EN

#define RCC_APB1ENR_TIM5EN

#define RCC_APB1ENR_TIM6EN

#define RCC_APB1ENR_TIM7EN

#define RCC_APB1ENR_TIM12EN

#define RCC_APB1ENR_TIM13EN

#define RCC_APB1ENR_TIM14EN

#define RCC_APB1ENR_WWDGEN

#define RCC_APB1ENR_SPI2EN

#define RCC_APB1ENR_SPI3EN

#define RCC_APB1ENR_USART2EN

#define RCC_APB1ENR_USART3EN

#define RCC_APB1ENR_UART4EN

#define RCC_APB1ENR_UART5EN

#define RCC_APB1ENR_I2C1EN

#define RCC_APB1ENR_I2C2EN

#define RCC_APB1ENR_I2C3EN

#define RCC_APB1ENR_CAN1EN

#define RCC_APB1ENR_CAN2EN

#define RCC_APB1ENR_PWREN

#define RCC_APB1ENR_DACEN

#define RCC_APB2ENR_TIM1EN

#define RCC_APB2ENR_TIM8EN

#define RCC_APB2ENR_USART1EN

#define RCC_APB2ENR_USART6EN

#define RCC_APB2ENR_ADC1EN

#define RCC_APB2ENR_ADC2EN

#define RCC_APB2ENR_ADC3EN

#define RCC_APB2ENR_SDIOEN

#define RCC_APB2ENR_SPI1EN

#define RCC_APB2ENR_SYSCFGEN

#define RCC_APB2ENR_TIM11EN

#define RCC_APB2ENR_TIM10EN

#define RCC_APB2ENR_TIM9EN

#define RCC_AHB1LPENR_GPIOALPEN

#define RCC_AHB1LPENR_GPIOBLPEN

#define RCC_AHB1LPENR_GPIOCLPEN

#define RCC_AHB1LPENR_GPIODLPEN

#define RCC_AHB1LPENR_GPIOELPEN

#define RCC_AHB1LPENR_GPIOFLPEN

#define RCC_AHB1LPENR_GPIOGLPEN

#define RCC_AHB1LPENR_GPIOHLPEN

#define RCC_AHB1LPENR_GPIOILPEN

#define RCC_AHB1LPENR_CRCLPEN

#define RCC_AHB1LPENR_FLITFLPEN

#define RCC_AHB1LPENR_SRAM1LPEN

#define RCC_AHB1LPENR_SRAM2LPEN

#define RCC_AHB1LPENR_BKPSRAMLPEN

#define RCC_AHB1LPENR_DMA1LPEN

#define RCC_AHB1LPENR_DMA2LPEN

#define RCC_AHB1LPENR_ETHMACLPEN

#define RCC_AHB1LPENR_ETHMACTXLPEN

#define RCC_AHB1LPENR_ETHMACRXLPEN

#define RCC_AHB1LPENR_ETHMACPTPLPEN

#define RCC_AHB1LPENR_OTGHSLPEN

#define RCC_AHB1LPENR_OTGHSULPILPEN

#define RCC_AHB2LPENR_DCMILPEN

#define RCC_AHB2LPENR_CRYPLPEN

#define RCC_AHB2LPENR_HASHLPEN

#define RCC_AHB2LPENR_RNGLPEN

#define RCC_AHB2LPENR_OTGFSLPEN

#define RCC_AHB3LPENR_FSMCLPEN

#define RCC_APB1LPENR_TIM2LPEN

#define RCC_APB1LPENR_TIM3LPEN

#define RCC_APB1LPENR_TIM4LPEN

#define RCC_APB1LPENR_TIM5LPEN

#define RCC_APB1LPENR_TIM6LPEN

#define RCC_APB1LPENR_TIM7LPEN

#define RCC_APB1LPENR_TIM12LPEN

#define RCC_APB1LPENR_TIM13LPEN

#define RCC_APB1LPENR_TIM14LPEN

#define RCC_APB1LPENR_WWDGLPEN

#define RCC_APB1LPENR_SPI2LPEN

#define RCC_APB1LPENR_SPI3LPEN

#define RCC_APB1LPENR_USART2LPEN

#define RCC_APB1LPENR_USART3LPEN

#define RCC_APB1LPENR_UART4LPEN

#define RCC_APB1LPENR_UART5LPEN

#define RCC_APB1LPENR_I2C1LPEN

#define RCC_APB1LPENR_I2C2LPEN

#define RCC_APB1LPENR_I2C3LPEN

#define RCC_APB1LPENR_CAN1LPEN

#define RCC_APB1LPENR_CAN2LPEN

#define RCC_APB1LPENR_PWRLPEN

#define RCC_APB1LPENR_DACLPEN

#define RCC_APB2LPENR_TIM1LPEN

#define RCC_APB2LPENR_TIM8LPEN

#define RCC_APB2LPENR_USART1LPEN

#define RCC_APB2LPENR_USART6LPEN

#define RCC_APB2LPENR_ADC1LPEN

#define RCC_APB2LPENR_ADC2PEN

#define RCC_APB2LPENR_ADC3LPEN

#define RCC_APB2LPENR_SDIOLPEN

#define RCC_APB2LPENR_SPI1LPEN

#define RCC_APB2LPENR_SYSCFGLPEN

#define RCC_APB2LPENR_TIM9LPEN

#define RCC_APB2LPENR_TIM10LPEN

#define RCC_APB2LPENR_TIM11LPEN

#define RCC_BDCR_LSEON

#define RCC_BDCR_LSERDY

#define RCC_BDCR_LSEBYP

#define RCC_BDCR_RTCSEL

#define RCC_BDCR_RTCSEL_0

#define RCC_BDCR_RTCSEL_1

#define RCC_BDCR_RTCEN

#define RCC_BDCR_BDRST

#define RCC_CSR_LSION

#define RCC_CSR_LSIRDY

#define RCC_CSR_RMVF

#define RCC_CSR_BORRSTF

#define RCC_CSR_PADRSTF

#define RCC_CSR_PORRSTF

#define RCC_CSR_SFTRSTF

#define RCC_CSR_WDGRSTF

#define RCC_CSR_WWDGRSTF

#define RCC_CSR_LPWRRSTF

#define RCC_SSCGR_MODPER

#define RCC_SSCGR_INCSTEP

#define RCC_SSCGR_SPREADSEL

#define RCC_SSCGR_SSCGEN

#define RCC_PLLI2SCFGR_PLLI2SN

#define RCC_PLLI2SCFGR_PLLI2SR

#define RNG_CR_RNGEN

#define RNG_CR_IE

#define RNG_SR_DRDY

#define RNG_SR_CECS

#define RNG_SR_SECS

#define RNG_SR_CEIS

#define RNG_SR_SEIS

#define RTC_TR_PM

#define RTC_TR_HT

#define RTC_TR_HT_0

#define RTC_TR_HT_1

#define RTC_TR_HU

#define RTC_TR_HU_0

#define RTC_TR_HU_1

#define RTC_TR_HU_2

#define RTC_TR_HU_3

#define RTC_TR_MNT

#define RTC_TR_MNT_0

#define RTC_TR_MNT_1

#define RTC_TR_MNT_2

#define RTC_TR_MNU

#define RTC_TR_MNU_0

#define RTC_TR_MNU_1

#define RTC_TR_MNU_2

#define RTC_TR_MNU_3

#define RTC_TR_ST

#define RTC_TR_ST_0

#define RTC_TR_ST_1

#define RTC_TR_ST_2

#define RTC_TR_SU

#define RTC_TR_SU_0

#define RTC_TR_SU_1

#define RTC_TR_SU_2

#define RTC_TR_SU_3

#define RTC_DR_YT

#define RTC_DR_YT_0

#define RTC_DR_YT_1

#define RTC_DR_YT_2

#define RTC_DR_YT_3

#define RTC_DR_YU

#define RTC_DR_YU_0

#define RTC_DR_YU_1

#define RTC_DR_YU_2

#define RTC_DR_YU_3

#define RTC_DR_WDU

#define RTC_DR_WDU_0

#define RTC_DR_WDU_1

#define RTC_DR_WDU_2

#define RTC_DR_MT

#define RTC_DR_MU

#define RTC_DR_MU_0

#define RTC_DR_MU_1

#define RTC_DR_MU_2

#define RTC_DR_MU_3

#define RTC_DR_DT

#define RTC_DR_DT_0

#define RTC_DR_DT_1

#define RTC_DR_DU

#define RTC_DR_DU_0

#define RTC_DR_DU_1

#define RTC_DR_DU_2

#define RTC_DR_DU_3

#define RTC_CR_COE

#define RTC_CR_OSEL

#define RTC_CR_OSEL_0

#define RTC_CR_OSEL_1

#define RTC_CR_POL

#define RTC_CR_BCK

#define RTC_CR_SUB1H

#define RTC_CR_ADD1H

#define RTC_CR_TSIE

#define RTC_CR_WUTIE

#define RTC_CR_ALRBIE

#define RTC_CR_ALRAIE

#define RTC_CR_TSE

#define RTC_CR_WUTE

#define RTC_CR_ALRBE

#define RTC_CR_ALRAE

#define RTC_CR_DCE

#define RTC_CR_FMT

#define RTC_CR_REFCKON

#define RTC_CR_TSEDGE

#define RTC_CR_WUCKSEL

#define RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_2

#define RTC_ISR_TAMP1F

#define RTC_ISR_TSOVF

#define RTC_ISR_TSF

#define RTC_ISR_WUTF

#define RTC_ISR_ALRBF

#define RTC_ISR_ALRAF

#define RTC_ISR_INIT

#define RTC_ISR_INITF

#define RTC_ISR_RSF

#define RTC_ISR_INITS

#define RTC_ISR_WUTWF

#define RTC_ISR_ALRBWF

#define RTC_ISR_ALRAWF

#define RTC_PRER_PREDIV_A

#define RTC_PRER_PREDIV_S

#define RTC_WUTR_WUT

#define RTC_CALIBR_DCS

#define RTC_CALIBR_DC

#define RTC_ALRMAR_MSK4

#define RTC_ALRMAR_WDSEL

#define RTC_ALRMAR_DT

#define RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DU

#define RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_3

#define RTC_ALRMAR_MSK3

#define RTC_ALRMAR_PM

#define RTC_ALRMAR_HT

#define RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HU

#define RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_3

#define RTC_ALRMAR_MSK2

#define RTC_ALRMAR_MNT

#define RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNU

#define RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MSK1

#define RTC_ALRMAR_ST

#define RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_2

#define RTC_ALRMAR_SU

#define RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_3

#define RTC_ALRMBR_MSK4

#define RTC_ALRMBR_WDSEL

#define RTC_ALRMBR_DT

#define RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DU

#define RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_3

#define RTC_ALRMBR_MSK3

#define RTC_ALRMBR_PM

#define RTC_ALRMBR_HT

#define RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HU

#define RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_3

#define RTC_ALRMBR_MSK2

#define RTC_ALRMBR_MNT

#define RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNU

#define RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MSK1

#define RTC_ALRMBR_ST

#define RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_2

#define RTC_ALRMBR_SU

#define RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_3

#define RTC_WPR_KEY

#define RTC_TSTR_PM

#define RTC_TSTR_HT

#define RTC_TSTR_HT_0

#define RTC_TSTR_HT_1

#define RTC_TSTR_HU

#define RTC_TSTR_HU_0

#define RTC_TSTR_HU_1

#define RTC_TSTR_HU_2

#define RTC_TSTR_HU_3

#define RTC_TSTR_MNT

#define RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_2

#define RTC_TSTR_MNU

#define RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_3

#define RTC_TSTR_ST

#define RTC_TSTR_ST_0

#define RTC_TSTR_ST_1

#define RTC_TSTR_ST_2

#define RTC_TSTR_SU

#define RTC_TSTR_SU_0

#define RTC_TSTR_SU_1

#define RTC_TSTR_SU_2

#define RTC_TSTR_SU_3

#define RTC_TSDR_WDU

#define RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_2

#define RTC_TSDR_MT

#define RTC_TSDR_MU

#define RTC_TSDR_MU_0

#define RTC_TSDR_MU_1

#define RTC_TSDR_MU_2

#define RTC_TSDR_MU_3

#define RTC_TSDR_DT

#define RTC_TSDR_DT_0

#define RTC_TSDR_DT_1

#define RTC_TSDR_DU

#define RTC_TSDR_DU_0

#define RTC_TSDR_DU_1

#define RTC_TSDR_DU_2

#define RTC_TSDR_DU_3

#define RTC_TAFCR_ALARMOUTTYPE

#define RTC_TAFCR_TSINSEL

#define RTC_TAFCR_TAMPINSEL

#define RTC_TAFCR_TAMPIE

#define RTC_TAFCR_TAMP1TRG

#define RTC_TAFCR_TAMP1E

#define RTC_BKP0R

#define RTC_BKP1R

#define RTC_BKP2R

#define RTC_BKP3R

#define RTC_BKP4R

#define RTC_BKP5R

#define RTC_BKP6R

#define RTC_BKP7R

#define RTC_BKP8R

#define RTC_BKP9R

#define RTC_BKP10R

#define RTC_BKP11R

#define RTC_BKP12R

#define RTC_BKP13R

#define RTC_BKP14R

#define RTC_BKP15R

#define RTC_BKP16R

#define RTC_BKP17R

#define RTC_BKP18R

#define RTC_BKP19R

#define SDIO_POWER_PWRCTRL

#define SDIO_POWER_PWRCTRL_0

#define SDIO_POWER_PWRCTRL_1

#define SDIO_CLKCR_CLKDIV

#define SDIO_CLKCR_CLKEN

#define SDIO_CLKCR_PWRSAV

#define SDIO_CLKCR_BYPASS

#define SDIO_CLKCR_WIDBUS

#define SDIO_CLKCR_WIDBUS_0

#define SDIO_CLKCR_WIDBUS_1

#define SDIO_CLKCR_NEGEDGE

#define SDIO_CLKCR_HWFC_EN

#define SDIO_ARG_CMDARG

#define SDIO_CMD_CMDINDEX

#define SDIO_CMD_WAITRESP

#define SDIO_CMD_WAITRESP_0

#define SDIO_CMD_WAITRESP_1

#define SDIO_CMD_WAITINT

#define SDIO_CMD_WAITPEND

#define SDIO_CMD_CPSMEN

#define SDIO_CMD_SDIOSUSPEND

#define SDIO_CMD_ENCMDCOMPL

#define SDIO_CMD_NIEN

#define SDIO_CMD_CEATACMD

#define SDIO_RESPCMD_RESPCMD

#define SDIO_RESP0_CARDSTATUS0

#define SDIO_RESP1_CARDSTATUS1

#define SDIO_RESP2_CARDSTATUS2

#define SDIO_RESP3_CARDSTATUS3

#define SDIO_RESP4_CARDSTATUS4

#define SDIO_DTIMER_DATATIME

#define SDIO_DLEN_DATALENGTH

#define SDIO_DCTRL_DTEN

#define SDIO_DCTRL_DTDIR

#define SDIO_DCTRL_DTMODE

#define SDIO_DCTRL_DMAEN

#define SDIO_DCTRL_DBLOCKSIZE

#define SDIO_DCTRL_DBLOCKSIZE_0

#define SDIO_DCTRL_DBLOCKSIZE_1

#define SDIO_DCTRL_DBLOCKSIZE_2

#define SDIO_DCTRL_DBLOCKSIZE_3

#define SDIO_DCTRL_RWSTART

#define SDIO_DCTRL_RWSTOP

#define SDIO_DCTRL_RWMOD

#define SDIO_DCTRL_SDIOEN

#define SDIO_DCOUNT_DATACOUNT

#define SDIO_STA_CCRCFAIL

#define SDIO_STA_DCRCFAIL

#define SDIO_STA_CTIMEOUT

#define SDIO_STA_DTIMEOUT

#define SDIO_STA_TXUNDERR

#define SDIO_STA_RXOVERR

#define SDIO_STA_CMDREND

#define SDIO_STA_CMDSENT

#define SDIO_STA_DATAEND

#define SDIO_STA_STBITERR

#define SDIO_STA_DBCKEND

#define SDIO_STA_CMDACT

#define SDIO_STA_TXACT

#define SDIO_STA_RXACT

#define SDIO_STA_TXFIFOHE

#define SDIO_STA_RXFIFOHF

#define SDIO_STA_TXFIFOF

#define SDIO_STA_RXFIFOF

#define SDIO_STA_TXFIFOE

#define SDIO_STA_RXFIFOE

#define SDIO_STA_TXDAVL

#define SDIO_STA_RXDAVL

#define SDIO_STA_SDIOIT

#define SDIO_STA_CEATAEND

#define SDIO_ICR_CCRCFAILC

#define SDIO_ICR_DCRCFAILC

#define SDIO_ICR_CTIMEOUTC

#define SDIO_ICR_DTIMEOUTC

#define SDIO_ICR_TXUNDERRC

#define SDIO_ICR_RXOVERRC

#define SDIO_ICR_CMDRENDC

#define SDIO_ICR_CMDSENTC

#define SDIO_ICR_DATAENDC

#define SDIO_ICR_STBITERRC

#define SDIO_ICR_DBCKENDC

#define SDIO_ICR_SDIOITC

#define SDIO_ICR_CEATAENDC

#define SDIO_MASK_CCRCFAILIE

#define SDIO_MASK_DCRCFAILIE

#define SDIO_MASK_CTIMEOUTIE

#define SDIO_MASK_DTIMEOUTIE

#define SDIO_MASK_TXUNDERRIE

#define SDIO_MASK_RXOVERRIE

#define SDIO_MASK_CMDRENDIE

#define SDIO_MASK_CMDSENTIE

#define SDIO_MASK_DATAENDIE

#define SDIO_MASK_STBITERRIE

#define SDIO_MASK_DBCKENDIE

#define SDIO_MASK_CMDACTIE

#define SDIO_MASK_TXACTIE

#define SDIO_MASK_RXACTIE

#define SDIO_MASK_TXFIFOHEIE

#define SDIO_MASK_RXFIFOHFIE

#define SDIO_MASK_TXFIFOFIE

#define SDIO_MASK_RXFIFOFIE

#define SDIO_MASK_TXFIFOEIE

#define SDIO_MASK_RXFIFOEIE

#define SDIO_MASK_TXDAVLIE

#define SDIO_MASK_RXDAVLIE

#define SDIO_MASK_SDIOITIE

#define SDIO_MASK_CEATAENDIE

#define SDIO_FIFOCNT_FIFOCOUNT

#define SDIO_FIFO_FIFODATA

#define SPI_CR1_CPHA

#define SPI_CR1_CPOL

#define SPI_CR1_MSTR

#define SPI_CR1_BR

#define SPI_CR1_BR_0

#define SPI_CR1_BR_1

#define SPI_CR1_BR_2

#define SPI_CR1_SPE

#define SPI_CR1_LSBFIRST

#define SPI_CR1_SSI

#define SPI_CR1_SSM

#define SPI_CR1_RXONLY

#define SPI_CR1_DFF

#define SPI_CR1_CRCNEXT

#define SPI_CR1_CRCEN

#define SPI_CR1_BIDIOE

#define SPI_CR1_BIDIMODE

#define SPI_CR2_RXDMAEN

#define SPI_CR2_TXDMAEN

#define SPI_CR2_SSOE

#define SPI_CR2_ERRIE

#define SPI_CR2_RXNEIE

#define SPI_CR2_TXEIE

#define SPI_SR_RXNE

#define SPI_SR_TXE

#define SPI_SR_CHSIDE

#define SPI_SR_UDR

#define SPI_SR_CRCERR

#define SPI_SR_MODF

#define SPI_SR_OVR

#define SPI_SR_BSY

#define SPI_DR_DR

#define SPI_CRCPR_CRCPOLY

#define SPI_RXCRCR_RXCRC

#define SPI_TXCRCR_TXCRC

#define SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SMOD

#define SPI_I2SPR_I2SDIV

#define SPI_I2SPR_ODD

#define SPI_I2SPR_MCKOE

#define SYSCFG_MEMRMP_MEM_MODE

#define SYSCFG_MEMRMP_MEM_MODE_0

#define SYSCFG_MEMRMP_MEM_MODE_1

#define SYSCFG_PMC_MII_RMII

#define SYSCFG_EXTICR1_EXTI0

#define SYSCFG_EXTICR1_EXTI1

#define SYSCFG_EXTICR1_EXTI2

#define SYSCFG_EXTICR1_EXTI3

* @brief EXTI0 configuration

#define SYSCFG_EXTICR1_EXTI0_PA

#define SYSCFG_EXTICR1_EXTI0_PB

#define SYSCFG_EXTICR1_EXTI0_PC

#define SYSCFG_EXTICR1_EXTI0_PD

#define SYSCFG_EXTICR1_EXTI0_PE

#define SYSCFG_EXTICR1_EXTI0_PF

#define SYSCFG_EXTICR1_EXTI0_PG

#define SYSCFG_EXTICR1_EXTI0_PH

#define SYSCFG_EXTICR1_EXTI0_PI

* @brief EXTI1 configuration

#define SYSCFG_EXTICR1_EXTI1_PA

#define SYSCFG_EXTICR1_EXTI1_PB

#define SYSCFG_EXTICR1_EXTI1_PC

#define SYSCFG_EXTICR1_EXTI1_PD

#define SYSCFG_EXTICR1_EXTI1_PE

#define SYSCFG_EXTICR1_EXTI1_PF

#define SYSCFG_EXTICR1_EXTI1_PG

#define SYSCFG_EXTICR1_EXTI1_PH

#define SYSCFG_EXTICR1_EXTI1_PI

* @brief EXTI2 configuration

#define SYSCFG_EXTICR1_EXTI2_PA

#define SYSCFG_EXTICR1_EXTI2_PB

#define SYSCFG_EXTICR1_EXTI2_PC

#define SYSCFG_EXTICR1_EXTI2_PD

#define SYSCFG_EXTICR1_EXTI2_PE

#define SYSCFG_EXTICR1_EXTI2_PF

#define SYSCFG_EXTICR1_EXTI2_PG

#define SYSCFG_EXTICR1_EXTI2_PH

#define SYSCFG_EXTICR1_EXTI2_PI

* @brief EXTI3 configuration

#define SYSCFG_EXTICR1_EXTI3_PA

#define SYSCFG_EXTICR1_EXTI3_PB

#define SYSCFG_EXTICR1_EXTI3_PC

#define SYSCFG_EXTICR1_EXTI3_PD

#define SYSCFG_EXTICR1_EXTI3_PE

#define SYSCFG_EXTICR1_EXTI3_PF

#define SYSCFG_EXTICR1_EXTI3_PG

#define SYSCFG_EXTICR1_EXTI3_PH

#define SYSCFG_EXTICR1_EXTI3_PI

#define SYSCFG_EXTICR2_EXTI4

#define SYSCFG_EXTICR2_EXTI5

#define SYSCFG_EXTICR2_EXTI6

#define SYSCFG_EXTICR2_EXTI7

* @brief EXTI4 configuration

#define SYSCFG_EXTICR2_EXTI4_PA

#define SYSCFG_EXTICR2_EXTI4_PB

#define SYSCFG_EXTICR2_EXTI4_PC

#define SYSCFG_EXTICR2_EXTI4_PD

#define SYSCFG_EXTICR2_EXTI4_PE

#define SYSCFG_EXTICR2_EXTI4_PF

#define SYSCFG_EXTICR2_EXTI4_PG

#define SYSCFG_EXTICR2_EXTI4_PH

#define SYSCFG_EXTICR2_EXTI4_PI

* @brief EXTI5 configuration

#define SYSCFG_EXTICR2_EXTI5_PA

#define SYSCFG_EXTICR2_EXTI5_PB

#define SYSCFG_EXTICR2_EXTI5_PC

#define SYSCFG_EXTICR2_EXTI5_PD

#define SYSCFG_EXTICR2_EXTI5_PE

#define SYSCFG_EXTICR2_EXTI5_PF

#define SYSCFG_EXTICR2_EXTI5_PG

#define SYSCFG_EXTICR2_EXTI5_PH

#define SYSCFG_EXTICR2_EXTI5_PI

* @brief EXTI6 configuration

#define SYSCFG_EXTICR2_EXTI6_PA

#define SYSCFG_EXTICR2_EXTI6_PB

#define SYSCFG_EXTICR2_EXTI6_PC

#define SYSCFG_EXTICR2_EXTI6_PD

#define SYSCFG_EXTICR2_EXTI6_PE

#define SYSCFG_EXTICR2_EXTI6_PF

#define SYSCFG_EXTICR2_EXTI6_PG

#define SYSCFG_EXTICR2_EXTI6_PH

#define SYSCFG_EXTICR2_EXTI6_PI

* @brief EXTI7 configuration

#define SYSCFG_EXTICR2_EXTI7_PA

#define SYSCFG_EXTICR2_EXTI7_PB

#define SYSCFG_EXTICR2_EXTI7_PC

#define SYSCFG_EXTICR2_EXTI7_PD

#define SYSCFG_EXTICR2_EXTI7_PE

#define SYSCFG_EXTICR2_EXTI7_PF

#define SYSCFG_EXTICR2_EXTI7_PG

#define SYSCFG_EXTICR2_EXTI7_PH

#define SYSCFG_EXTICR2_EXTI7_PI

#define SYSCFG_EXTICR3_EXTI8

#define SYSCFG_EXTICR3_EXTI9

#define SYSCFG_EXTICR3_EXTI10

#define SYSCFG_EXTICR3_EXTI11

* @brief EXTI8 configuration

#define SYSCFG_EXTICR3_EXTI8_PA

#define SYSCFG_EXTICR3_EXTI8_PB

#define SYSCFG_EXTICR3_EXTI8_PC

#define SYSCFG_EXTICR3_EXTI8_PD

#define SYSCFG_EXTICR3_EXTI8_PE

#define SYSCFG_EXTICR3_EXTI8_PF

#define SYSCFG_EXTICR3_EXTI8_PG

#define SYSCFG_EXTICR3_EXTI8_PH

#define SYSCFG_EXTICR3_EXTI8_PI

* @brief EXTI9 configuration

#define SYSCFG_EXTICR3_EXTI9_PA

#define SYSCFG_EXTICR3_EXTI9_PB

#define SYSCFG_EXTICR3_EXTI9_PC

#define SYSCFG_EXTICR3_EXTI9_PD

#define SYSCFG_EXTICR3_EXTI9_PE

#define SYSCFG_EXTICR3_EXTI9_PF

#define SYSCFG_EXTICR3_EXTI9_PG

#define SYSCFG_EXTICR3_EXTI9_PH

#define SYSCFG_EXTICR3_EXTI9_PI

* @brief EXTI10 configuration

#define SYSCFG_EXTICR3_EXTI10_PA

#define SYSCFG_EXTICR3_EXTI10_PB

#define SYSCFG_EXTICR3_EXTI10_PC

#define SYSCFG_EXTICR3_EXTI10_PD

#define SYSCFG_EXTICR3_EXTI10_PE

#define SYSCFG_EXTICR3_EXTI10_PF

#define SYSCFG_EXTICR3_EXTI10_PG

#define SYSCFG_EXTICR3_EXTI10_PH

#define SYSCFG_EXTICR3_EXTI10_PI

* @brief EXTI11 configuration

#define SYSCFG_EXTICR3_EXTI11_PA

#define SYSCFG_EXTICR3_EXTI11_PB

#define SYSCFG_EXTICR3_EXTI11_PC

#define SYSCFG_EXTICR3_EXTI11_PD

#define SYSCFG_EXTICR3_EXTI11_PE

#define SYSCFG_EXTICR3_EXTI11_PF

#define SYSCFG_EXTICR3_EXTI11_PG

#define SYSCFG_EXTICR3_EXTI11_PH

#define SYSCFG_EXTICR3_EXTI11_PI

#define SYSCFG_EXTICR4_EXTI12

#define SYSCFG_EXTICR4_EXTI13

#define SYSCFG_EXTICR4_EXTI14

#define SYSCFG_EXTICR4_EXTI15

* @brief EXTI12 configuration

#define SYSCFG_EXTICR4_EXTI12_PA

#define SYSCFG_EXTICR4_EXTI12_PB

#define SYSCFG_EXTICR4_EXTI12_PC

#define SYSCFG_EXTICR4_EXTI12_PD

#define SYSCFG_EXTICR4_EXTI12_PE

#define SYSCFG_EXTICR4_EXTI12_PF

#define SYSCFG_EXTICR4_EXTI12_PG

#define SYSCFG_EXTICR3_EXTI12_PH

* @brief EXTI13 configuration

#define SYSCFG_EXTICR4_EXTI13_PA

#define SYSCFG_EXTICR4_EXTI13_PB

#define SYSCFG_EXTICR4_EXTI13_PC

#define SYSCFG_EXTICR4_EXTI13_PD

#define SYSCFG_EXTICR4_EXTI13_PE

#define SYSCFG_EXTICR4_EXTI13_PF

#define SYSCFG_EXTICR4_EXTI13_PG

#define SYSCFG_EXTICR3_EXTI13_PH

* @brief EXTI14 configuration

#define SYSCFG_EXTICR4_EXTI14_PA

#define SYSCFG_EXTICR4_EXTI14_PB

#define SYSCFG_EXTICR4_EXTI14_PC

#define SYSCFG_EXTICR4_EXTI14_PD

#define SYSCFG_EXTICR4_EXTI14_PE

#define SYSCFG_EXTICR4_EXTI14_PF

#define SYSCFG_EXTICR4_EXTI14_PG

#define SYSCFG_EXTICR3_EXTI14_PH

* @brief EXTI15 configuration

#define SYSCFG_EXTICR4_EXTI15_PA

#define SYSCFG_EXTICR4_EXTI15_PB

#define SYSCFG_EXTICR4_EXTI15_PC

#define SYSCFG_EXTICR4_EXTI15_PD

#define SYSCFG_EXTICR4_EXTI15_PE

#define SYSCFG_EXTICR4_EXTI15_PF

#define SYSCFG_EXTICR4_EXTI15_PG

#define SYSCFG_EXTICR3_EXTI15_PH

#define SYSCFG_CMPCR_CMP_PD

#define SYSCFG_CMPCR_READY

#define TIM_CR1_CEN

#define TIM_CR1_UDIS

#define TIM_CR1_URS

#define TIM_CR1_OPM

#define TIM_CR1_DIR

#define TIM_CR1_CMS

#define TIM_CR1_CMS_0

#define TIM_CR1_CMS_1

#define TIM_CR1_ARPE

#define TIM_CR1_CKD

#define TIM_CR1_CKD_0

#define TIM_CR1_CKD_1

#define TIM_CR2_CCPC

#define TIM_CR2_CCUS

#define TIM_CR2_CCDS

#define TIM_CR2_MMS

#define TIM_CR2_MMS_0

#define TIM_CR2_MMS_1

#define TIM_CR2_MMS_2

#define TIM_CR2_TI1S

#define TIM_CR2_OIS1

#define TIM_CR2_OIS1N

#define TIM_CR2_OIS2

#define TIM_CR2_OIS2N

#define TIM_CR2_OIS3

#define TIM_CR2_OIS3N

#define TIM_CR2_OIS4

#define TIM_SMCR_SMS

#define TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_2

#define TIM_SMCR_TS

#define TIM_SMCR_TS_0

#define TIM_SMCR_TS_1

#define TIM_SMCR_TS_2

#define TIM_SMCR_MSM

#define TIM_SMCR_ETF

#define TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_3

#define TIM_SMCR_ETPS

#define TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_1

#define TIM_SMCR_ECE

#define TIM_SMCR_ETP

#define TIM_DIER_UIE

#define TIM_DIER_CC1IE

#define TIM_DIER_CC2IE

#define TIM_DIER_CC3IE

#define TIM_DIER_CC4IE

#define TIM_DIER_COMIE

#define TIM_DIER_TIE

#define TIM_DIER_BIE

#define TIM_DIER_UDE

#define TIM_DIER_CC1DE

#define TIM_DIER_CC2DE

#define TIM_DIER_CC3DE

#define TIM_DIER_CC4DE

#define TIM_DIER_COMDE

#define TIM_DIER_TDE

#define TIM_SR_UIF

#define TIM_SR_CC1IF

#define TIM_SR_CC2IF

#define TIM_SR_CC3IF

#define TIM_SR_CC4IF

#define TIM_SR_COMIF

#define TIM_SR_TIF

#define TIM_SR_BIF

#define TIM_SR_CC1OF

#define TIM_SR_CC2OF

#define TIM_SR_CC3OF

#define TIM_SR_CC4OF

#define TIM_EGR_UG

#define TIM_EGR_CC1G

#define TIM_EGR_CC2G

#define TIM_EGR_CC3G

#define TIM_EGR_CC4G

#define TIM_EGR_COMG

#define TIM_EGR_TG

#define TIM_EGR_BG

#define TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_1

#define TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1CE

#define TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_1

#define TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2CE

#define TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_3

#define TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_1

#define TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3CE

#define TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_1

#define TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4CE

#define TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_3

#define TIM_CCER_CC1E

#define TIM_CCER_CC1P

#define TIM_CCER_CC1NE

#define TIM_CCER_CC1NP

#define TIM_CCER_CC2E

#define TIM_CCER_CC2P

#define TIM_CCER_CC2NE

#define TIM_CCER_CC2NP

#define TIM_CCER_CC3E

#define TIM_CCER_CC3P

#define TIM_CCER_CC3NE

#define TIM_CCER_CC3NP

#define TIM_CCER_CC4E

#define TIM_CCER_CC4P

#define TIM_CCER_CC4NP

#define TIM_CNT_CNT

#define TIM_PSC_PSC

#define TIM_ARR_ARR

#define TIM_RCR_REP

#define TIM_CCR1_CCR1

#define TIM_CCR2_CCR2

#define TIM_CCR3_CCR3

#define TIM_CCR4_CCR4

#define TIM_BDTR_DTG

#define TIM_BDTR_DTG_0

#define TIM_BDTR_DTG_1

#define TIM_BDTR_DTG_2

#define TIM_BDTR_DTG_3

#define TIM_BDTR_DTG_4

#define TIM_BDTR_DTG_5

#define TIM_BDTR_DTG_6

#define TIM_BDTR_DTG_7

#define TIM_BDTR_LOCK

#define TIM_BDTR_LOCK_0

#define TIM_BDTR_LOCK_1

#define TIM_BDTR_OSSI

#define TIM_BDTR_OSSR

#define TIM_BDTR_BKE

#define TIM_BDTR_BKP

#define TIM_BDTR_AOE

#define TIM_BDTR_MOE

#define TIM_DCR_DBA

#define TIM_DCR_DBA_0

#define TIM_DCR_DBA_1

#define TIM_DCR_DBA_2

#define TIM_DCR_DBA_3

#define TIM_DCR_DBA_4

#define TIM_DCR_DBL

#define TIM_DCR_DBL_0

#define TIM_DCR_DBL_1

#define TIM_DCR_DBL_2

#define TIM_DCR_DBL_3

#define TIM_DCR_DBL_4

#define TIM_DMAR_DMAB

#define TIM_OR_TI4_RMP

#define TIM_OR_TI4_RMP_0

#define TIM_OR_TI4_RMP_1

#define TIM_OR_ITR1_RMP

#define TIM_OR_ITR1_RMP_0

#define TIM_OR_ITR1_RMP_1

#define USART_SR_PE

#define USART_SR_FE

#define USART_SR_NE

#define USART_SR_ORE

#define USART_SR_IDLE

#define USART_SR_RXNE

#define USART_SR_TC

#define USART_SR_TXE

#define USART_SR_LBD

#define USART_SR_CTS

#define USART_DR_DR

#define USART_BRR_DIV_Fraction

#define USART_BRR_DIV_Mantissa

#define USART_CR1_SBK

#define USART_CR1_RWU

#define USART_CR1_RE

#define USART_CR1_TE

#define USART_CR1_IDLEIE

#define USART_CR1_RXNEIE

#define USART_CR1_TCIE

#define USART_CR1_TXEIE

#define USART_CR1_PEIE

#define USART_CR1_PS

#define USART_CR1_PCE

#define USART_CR1_WAKE

#define USART_CR1_M

#define USART_CR1_UE

#define USART_CR1_OVER8

#define USART_CR2_ADD

#define USART_CR2_LBDL

#define USART_CR2_LBDIE

#define USART_CR2_LBCL

#define USART_CR2_CPHA

#define USART_CR2_CPOL

#define USART_CR2_CLKEN

#define USART_CR2_STOP

#define USART_CR2_STOP_0

#define USART_CR2_STOP_1

#define USART_CR2_LINEN

#define USART_CR3_EIE

#define USART_CR3_IREN

#define USART_CR3_IRLP

#define USART_CR3_HDSEL

#define USART_CR3_NACK

#define USART_CR3_SCEN

#define USART_CR3_DMAR

#define USART_CR3_DMAT

#define USART_CR3_RTSE

#define USART_CR3_CTSE

#define USART_CR3_CTSIE

#define USART_CR3_ONEBIT

#define USART_GTPR_PSC

#define USART_GTPR_PSC_0

#define USART_GTPR_PSC_1

#define USART_GTPR_PSC_2

#define USART_GTPR_PSC_3

#define USART_GTPR_PSC_4

#define USART_GTPR_PSC_5

#define USART_GTPR_PSC_6

#define USART_GTPR_PSC_7

#define USART_GTPR_GT

#define WWDG_CR_T

#define WWDG_CR_T0

#define WWDG_CR_T1

#define WWDG_CR_T2

#define WWDG_CR_T3

#define WWDG_CR_T4

#define WWDG_CR_T5

#define WWDG_CR_T6

#define WWDG_CR_WDGA

#define WWDG_CFR_W

#define WWDG_CFR_W0

#define WWDG_CFR_W1

#define WWDG_CFR_W2

#define WWDG_CFR_W3

#define WWDG_CFR_W4

#define WWDG_CFR_W5

#define WWDG_CFR_W6

#define WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB0

#define WWDG_CFR_WDGTB1

#define WWDG_CFR_EWI

#define WWDG_SR_EWIF

#define DBGMCU_IDCODE_DEV_ID

#define DBGMCU_IDCODE_REV_ID

#define DBGMCU_CR_DBG_SLEEP

#define DBGMCU_CR_DBG_STOP

#define DBGMCU_CR_DBG_STANDBY

#define DBGMCU_CR_TRACE_IOEN

#define DBGMCU_CR_TRACE_MODE

#define DBGMCU_CR_TRACE_MODE_0

#define DBGMCU_CR_TRACE_MODE_1

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP

#define DBGMCU_APB1_FZ_DBG_TIM12_STOP

#define DBGMCU_APB1_FZ_DBG_TIM13_STOP

#define DBGMCU_APB1_FZ_DBG_TIM14_STOP

#define DBGMCU_APB1_FZ_DBG_RTC_STOP

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP

#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP

#define DBGMCU_APB1_FZ_DBG_CAN2_STOP

#define DBGMCU_APB1_FZ_DBG_TIM1_STOP

#define DBGMCU_APB1_FZ_DBG_TIM8_STOP

#define DBGMCU_APB1_FZ_DBG_TIM9_STOP

#define DBGMCU_APB1_FZ_DBG_TIM10_STOP

#define DBGMCU_APB1_FZ_DBG_TIM11_STOP

#define ETH_MACCR_WD

#define ETH_MACCR_JD

#define ETH_MACCR_IFG

#define ETH_MACCR_IFG_96Bit

#define ETH_MACCR_IFG_88Bit

#define ETH_MACCR_IFG_80Bit

#define ETH_MACCR_IFG_72Bit

#define ETH_MACCR_IFG_64Bit

#define ETH_MACCR_IFG_56Bit

#define ETH_MACCR_IFG_48Bit

#define ETH_MACCR_IFG_40Bit

#define ETH_MACCR_CSD

#define ETH_MACCR_FES

#define ETH_MACCR_ROD

#define ETH_MACCR_LM

#define ETH_MACCR_DM

#define ETH_MACCR_IPCO

#define ETH_MACCR_RD

#define ETH_MACCR_APCS

#define ETH_MACCR_BL

#define ETH_MACCR_BL_10

#define ETH_MACCR_BL_8

#define ETH_MACCR_BL_4

#define ETH_MACCR_BL_1

#define ETH_MACCR_DC

#define ETH_MACCR_TE

#define ETH_MACCR_RE

#define ETH_MACFFR_RA

#define ETH_MACFFR_HPF

#define ETH_MACFFR_SAF

#define ETH_MACFFR_SAIF

#define ETH_MACFFR_PCF

#define ETH_MACFFR_PCF_BlockAll

#define ETH_MACFFR_PCF_ForwardAll

#define ETH_MACFFR_PCF_ForwardPassedAddrFilter

#define ETH_MACFFR_BFD

#define ETH_MACFFR_PAM

#define ETH_MACFFR_DAIF

#define ETH_MACFFR_HM

#define ETH_MACFFR_HU

#define ETH_MACFFR_PM

#define ETH_MACHTHR_HTH

#define ETH_MACHTLR_HTL

#define ETH_MACMIIAR_PA

#define ETH_MACMIIAR_MR

#define ETH_MACMIIAR_CR

#define ETH_MACMIIAR_CR_Div42

#define ETH_MACMIIAR_CR_Div62

#define ETH_MACMIIAR_CR_Div16

#define ETH_MACMIIAR_CR_Div26

#define ETH_MACMIIAR_MW

#define ETH_MACMIIAR_MB

#define ETH_MACMIIDR_MD

#define ETH_MACFCR_PT

#define ETH_MACFCR_ZQPD

#define ETH_MACFCR_PLT

#define ETH_MACFCR_PLT_Minus4

#define ETH_MACFCR_PLT_Minus28

#define ETH_MACFCR_PLT_Minus144

#define ETH_MACFCR_PLT_Minus256

#define ETH_MACFCR_UPFD

#define ETH_MACFCR_RFCE

#define ETH_MACFCR_TFCE

#define ETH_MACFCR_FCBBPA

#define ETH_MACVLANTR_VLANTC

#define ETH_MACVLANTR_VLANTI

#define ETH_MACRWUFFR_D

#define ETH_MACPMTCSR_WFFRPR

#define ETH_MACPMTCSR_GU

#define ETH_MACPMTCSR_WFR

#define ETH_MACPMTCSR_MPR

#define ETH_MACPMTCSR_WFE

#define ETH_MACPMTCSR_MPE

#define ETH_MACPMTCSR_PD

#define ETH_MACSR_TSTS

#define ETH_MACSR_MMCTS

#define ETH_MACSR_MMMCRS

#define ETH_MACSR_MMCS

#define ETH_MACSR_PMTS

#define ETH_MACIMR_TSTIM

#define ETH_MACIMR_PMTIM

#define ETH_MACA0HR_MACA0H

#define ETH_MACA0LR_MACA0L

#define ETH_MACA1HR_AE

#define ETH_MACA1HR_SA

#define ETH_MACA1HR_MBC

#define ETH_MACA1HR_MBC_HBits15_8

#define ETH_MACA1HR_MBC_HBits7_0

#define ETH_MACA1HR_MBC_LBits31_24

#define ETH_MACA1HR_MBC_LBits23_16

#define ETH_MACA1HR_MBC_LBits15_8

#define ETH_MACA1HR_MBC_LBits7_0

#define ETH_MACA1HR_MACA1H

#define ETH_MACA1LR_MACA1L

#define ETH_MACA2HR_AE

#define ETH_MACA2HR_SA

#define ETH_MACA2HR_MBC

#define ETH_MACA2HR_MBC_HBits15_8

#define ETH_MACA2HR_MBC_HBits7_0

#define ETH_MACA2HR_MBC_LBits31_24

#define ETH_MACA2HR_MBC_LBits23_16

#define ETH_MACA2HR_MBC_LBits15_8

#define ETH_MACA2HR_MBC_LBits7_0

#define ETH_MACA2HR_MACA2H

#define ETH_MACA2LR_MACA2L

#define ETH_MACA3HR_AE

#define ETH_MACA3HR_SA

#define ETH_MACA3HR_MBC

#define ETH_MACA3HR_MBC_HBits15_8

#define ETH_MACA3HR_MBC_HBits7_0

#define ETH_MACA3HR_MBC_LBits31_24

#define ETH_MACA3HR_MBC_LBits23_16

#define ETH_MACA3HR_MBC_LBits15_8

#define ETH_MACA3HR_MBC_LBits7_0

#define ETH_MACA3HR_MACA3H

#define ETH_MACA3LR_MACA3L

#define ETH_MMCCR_MCFHP

#define ETH_MMCCR_MCP

#define ETH_MMCCR_MCF

#define ETH_MMCCR_ROR

#define ETH_MMCCR_CSR

#define ETH_MMCCR_CR

#define ETH_MMCRIR_RGUFS

#define ETH_MMCRIR_RFAES

#define ETH_MMCRIR_RFCES

#define ETH_MMCTIR_TGFS

#define ETH_MMCTIR_TGFMSCS

#define ETH_MMCTIR_TGFSCS

#define ETH_MMCRIMR_RGUFM

#define ETH_MMCRIMR_RFAEM

#define ETH_MMCRIMR_RFCEM

#define ETH_MMCTIMR_TGFM

#define ETH_MMCTIMR_TGFMSCM

#define ETH_MMCTIMR_TGFSCM

#define ETH_MMCTGFSCCR_TGFSCC

#define ETH_MMCTGFMSCCR_TGFMSCC

#define ETH_MMCTGFCR_TGFC

#define ETH_MMCRFCECR_RFCEC

#define ETH_MMCRFAECR_RFAEC

#define ETH_MMCRGUFCR_RGUFC

#define ETH_PTPTSCR_TSCNT

#define ETH_PTPTSSR_TSSMRME

#define ETH_PTPTSSR_TSSEME

#define ETH_PTPTSSR_TSSIPV4FE

#define ETH_PTPTSSR_TSSIPV6FE

#define ETH_PTPTSSR_TSSPTPOEFE

#define ETH_PTPTSSR_TSPTPPSV2E

#define ETH_PTPTSSR_TSSSR

#define ETH_PTPTSSR_TSSARFE

#define ETH_PTPTSCR_TSARU

#define ETH_PTPTSCR_TSITE

#define ETH_PTPTSCR_TSSTU

#define ETH_PTPTSCR_TSSTI

#define ETH_PTPTSCR_TSFCU

#define ETH_PTPTSCR_TSE

#define ETH_PTPSSIR_STSSI

#define ETH_PTPTSHR_STS

#define ETH_PTPTSLR_STPNS

#define ETH_PTPTSLR_STSS

#define ETH_PTPTSHUR_TSUS

#define ETH_PTPTSLUR_TSUPNS

#define ETH_PTPTSLUR_TSUSS

#define ETH_PTPTSAR_TSA

#define ETH_PTPTTHR_TTSH

#define ETH_PTPTTLR_TTSL

#define ETH_PTPTSSR_TSTTR

#define ETH_PTPTSSR_TSSO

#define ETH_DMABMR_AAB

#define ETH_DMABMR_FPM

#define ETH_DMABMR_USP

#define ETH_DMABMR_RDP

#define ETH_DMABMR_RDP_1Beat

#define ETH_DMABMR_RDP_2Beat

#define ETH_DMABMR_RDP_4Beat

#define ETH_DMABMR_RDP_8Beat

#define ETH_DMABMR_RDP_16Beat

#define ETH_DMABMR_RDP_32Beat

#define ETH_DMABMR_RDP_4xPBL_4Beat

#define ETH_DMABMR_RDP_4xPBL_8Beat

#define ETH_DMABMR_RDP_4xPBL_16Beat

#define ETH_DMABMR_RDP_4xPBL_32Beat

#define ETH_DMABMR_RDP_4xPBL_64Beat

#define ETH_DMABMR_RDP_4xPBL_128Beat

#define ETH_DMABMR_FB

#define ETH_DMABMR_RTPR

#define ETH_DMABMR_RTPR_1_1

#define ETH_DMABMR_RTPR_2_1

#define ETH_DMABMR_RTPR_3_1

#define ETH_DMABMR_RTPR_4_1

#define ETH_DMABMR_PBL

#define ETH_DMABMR_PBL_1Beat

#define ETH_DMABMR_PBL_2Beat

#define ETH_DMABMR_PBL_4Beat

#define ETH_DMABMR_PBL_8Beat

#define ETH_DMABMR_PBL_16Beat

#define ETH_DMABMR_PBL_32Beat

#define ETH_DMABMR_PBL_4xPBL_4Beat

#define ETH_DMABMR_PBL_4xPBL_8Beat

#define ETH_DMABMR_PBL_4xPBL_16Beat

#define ETH_DMABMR_PBL_4xPBL_32Beat

#define ETH_DMABMR_PBL_4xPBL_64Beat

#define ETH_DMABMR_PBL_4xPBL_128Beat

#define ETH_DMABMR_EDE

#define ETH_DMABMR_DSL

#define ETH_DMABMR_DA

#define ETH_DMABMR_SR

#define ETH_DMATPDR_TPD

#define ETH_DMARPDR_RPD

#define ETH_DMARDLAR_SRL

#define ETH_DMATDLAR_STL

#define ETH_DMASR_TSTS

#define ETH_DMASR_PMTS

#define ETH_DMASR_MMCS

#define ETH_DMASR_EBS

#define ETH_DMASR_EBS_DescAccess

#define ETH_DMASR_EBS_ReadTransf

#define ETH_DMASR_EBS_DataTransfTx

#define ETH_DMASR_TPS

#define ETH_DMASR_TPS_Stopped

#define ETH_DMASR_TPS_Fetching

#define ETH_DMASR_TPS_Waiting

#define ETH_DMASR_TPS_Reading

#define ETH_DMASR_TPS_Suspended

#define ETH_DMASR_TPS_Closing

#define ETH_DMASR_RPS

#define ETH_DMASR_RPS_Stopped

#define ETH_DMASR_RPS_Fetching

#define ETH_DMASR_RPS_Waiting

#define ETH_DMASR_RPS_Suspended

#define ETH_DMASR_RPS_Closing

#define ETH_DMASR_RPS_Queuing

#define ETH_DMASR_NIS

#define ETH_DMASR_AIS

#define ETH_DMASR_ERS

#define ETH_DMASR_FBES

#define ETH_DMASR_ETS

#define ETH_DMASR_RWTS

#define ETH_DMASR_RPSS

#define ETH_DMASR_RBUS

#define ETH_DMASR_RS

#define ETH_DMASR_TUS

#define ETH_DMASR_ROS

#define ETH_DMASR_TJTS

#define ETH_DMASR_TBUS

#define ETH_DMASR_TPSS

#define ETH_DMASR_TS

#define ETH_DMAOMR_DTCEFD

#define ETH_DMAOMR_RSF

#define ETH_DMAOMR_DFRF

#define ETH_DMAOMR_TSF

#define ETH_DMAOMR_FTF

#define ETH_DMAOMR_TTC

#define ETH_DMAOMR_TTC_64Bytes

#define ETH_DMAOMR_TTC_128Bytes

#define ETH_DMAOMR_TTC_192Bytes

#define ETH_DMAOMR_TTC_256Bytes

#define ETH_DMAOMR_TTC_40Bytes

#define ETH_DMAOMR_TTC_32Bytes

#define ETH_DMAOMR_TTC_24Bytes

#define ETH_DMAOMR_TTC_16Bytes

#define ETH_DMAOMR_ST

#define ETH_DMAOMR_FEF

#define ETH_DMAOMR_FUGF

#define ETH_DMAOMR_RTC

#define ETH_DMAOMR_RTC_64Bytes

#define ETH_DMAOMR_RTC_32Bytes

#define ETH_DMAOMR_RTC_96Bytes

#define ETH_DMAOMR_RTC_128Bytes

#define ETH_DMAOMR_OSF

#define ETH_DMAOMR_SR

#define ETH_DMAIER_NISE

#define ETH_DMAIER_AISE

#define ETH_DMAIER_ERIE

#define ETH_DMAIER_FBEIE

#define ETH_DMAIER_ETIE

#define ETH_DMAIER_RWTIE

#define ETH_DMAIER_RPSIE

#define ETH_DMAIER_RBUIE

#define ETH_DMAIER_RIE

#define ETH_DMAIER_TUIE

#define ETH_DMAIER_ROIE

#define ETH_DMAIER_TJTIE

#define ETH_DMAIER_TBUIE

#define ETH_DMAIER_TPSIE

#define ETH_DMAIER_TIE

#define ETH_DMAMFBOCR_OFOC

#define ETH_DMAMFBOCR_MFA

#define ETH_DMAMFBOCR_OMFC

#define ETH_DMAMFBOCR_MFC

#define ETH_DMACHTDR_HTDAP

#define ETH_DMACHRDR_HRDAP

#define ETH_DMACHTBAR_HTBAP

#define ETH_DMACHRBAR_HRBAP

@addtogroup Exported_macro * @{

#define SET_BIT( REG, BIT )

#define CLEAR_BIT( REG, BIT )

#define READ_BIT( REG, BIT )

#define CLEAR_REG( REG )

#define WRITE_REG( REG, VAL )

#define READ_REG( REG )

#define MODIFY_REG( REG, CLEARMASK, SETMASK )


Typedef IRQn_Type

* @brief STM32F2XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section

typedef enum IRQn IRQn_Type

enum IRQn  
   {  
      NonMaskableInt_IRQn;  
      MemoryManagement_IRQn;  
      BusFault_IRQn;  
      UsageFault_IRQn;  
      SVCall_IRQn;  
      DebugMonitor_IRQn;  
      PendSV_IRQn;  
      SysTick_IRQn;  
      WWDG_IRQn;  
      PVD_IRQn;  
      TAMP_STAMP_IRQn;  
      RTC_WKUP_IRQn;  
      FLASH_IRQn;  
      RCC_IRQn;  
      EXTI0_IRQn;  
      EXTI1_IRQn;  
      EXTI2_IRQn;  
      EXTI3_IRQn;  
      EXTI4_IRQn;  
      DMA1_Stream0_IRQn;  
      DMA1_Stream1_IRQn;  
      DMA1_Stream2_IRQn;  
      DMA1_Stream3_IRQn;  
      DMA1_Stream4_IRQn;  
      DMA1_Stream5_IRQn;  
      DMA1_Stream6_IRQn;  
      ADC_IRQn;  
      CAN1_TX_IRQn;  
      CAN1_RX0_IRQn;  
      CAN1_RX1_IRQn;  
      CAN1_SCE_IRQn;  
      EXTI9_5_IRQn;  
      TIM1_BRK_TIM9_IRQn;  
      TIM1_UP_TIM10_IRQn;  
      TIM1_TRG_COM_TIM11_IRQn;  
      TIM1_CC_IRQn;  
      TIM2_IRQn;  
      TIM3_IRQn;  
      TIM4_IRQn;  
      I2C1_EV_IRQn;  
      I2C1_ER_IRQn;  
      I2C2_EV_IRQn;  
      I2C2_ER_IRQn;  
      SPI1_IRQn;  
      SPI2_IRQn;  
      USART1_IRQn;  
      USART2_IRQn;  
      USART3_IRQn;  
      EXTI15_10_IRQn;  
      RTC_Alarm_IRQn;  
      OTG_FS_WKUP_IRQn;  
      TIM8_BRK_TIM12_IRQn;  
      TIM8_UP_TIM13_IRQn;  
      TIM8_TRG_COM_TIM14_IRQn;  
      TIM8_CC_IRQn;  
      DMA1_Stream7_IRQn;  
      FSMC_IRQn;  
      SDIO_IRQn;  
      TIM5_IRQn;  
      SPI3_IRQn;  
      UART4_IRQn;  
      UART5_IRQn;  
      TIM6_DAC_IRQn;  
      TIM7_IRQn;  
      DMA2_Stream0_IRQn;  
      DMA2_Stream1_IRQn;  
      DMA2_Stream2_IRQn;  
      DMA2_Stream3_IRQn;  
      DMA2_Stream4_IRQn;  
      ETH_IRQn;  
      ETH_WKUP_IRQn;  
      CAN2_TX_IRQn;  
      CAN2_RX0_IRQn;  
      CAN2_RX1_IRQn;  
      CAN2_SCE_IRQn;  
      OTG_FS_IRQn;  
      DMA2_Stream5_IRQn;  
      DMA2_Stream6_IRQn;  
      DMA2_Stream7_IRQn;  
      USART6_IRQn;  
      I2C3_EV_IRQn;  
      I2C3_ER_IRQn;  
      OTG_HS_EP1_OUT_IRQn;  
      OTG_HS_EP1_IN_IRQn;  
      OTG_HS_WKUP_IRQn;  
      OTG_HS_IRQn;  
      DCMI_IRQn;  
      CRYP_IRQn;  
      HASH_RNG_IRQn;  
      IRQn_MAX;  
   }  

Typedef s32

@addtogroup Exported_types * @{

typedef int32_t s32


Typedef s16

typedef int16_t s16

Typedef s8

typedef int8_t s8

Typedef sc32

typedef const int32_t sc32

Typedef sc16

typedef const int16_t sc16

Typedef sc8

typedef const int8_t sc8

Typedef vs32

typedef volatile int32_t vs32

Typedef vs16

typedef volatile int16_t vs16

Typedef vs8

typedef volatile int8_t vs8

Typedef vsc32

typedef volatile const int32_t vsc32

Typedef vsc16

typedef volatile const int16_t vsc16

Typedef vsc8

typedef volatile const int8_t vsc8

Typedef u32

typedef uint32_t u32

Typedef u16

typedef uint16_t u16

Typedef u8

typedef uint8_t u8

Typedef uc32

typedef const uint32_t uc32

Typedef uc16

typedef const uint16_t uc16

Typedef uc8

typedef const uint8_t uc8

Typedef vu32

typedef volatile uint32_t vu32

Typedef vu16

typedef volatile uint16_t vu16

Typedef vu8

typedef volatile uint8_t vu8

Typedef vuc32

typedef volatile const uint32_t vuc32

Typedef vuc16

typedef volatile const uint16_t vuc16

Typedef vuc8

typedef volatile const uint8_t vuc8

Typedef bool

typedef enum {...} bool
enum  
   {  
      FALSE;  
      TRUE;  
   }  

Typedef FlagStatus

typedef enum {...} FlagStatus
enum  
   {  
      RESET;  
      SET;  
   }  

Typedef ITStatus

typedef enum {...} ITStatus
See: Typedef FlagStatus

Typedef FunctionalState

typedef enum {...} FunctionalState
enum  
   {  
      DISABLE;  
      ENABLE;  
   }  

Typedef ErrorStatus

typedef enum {...} ErrorStatus
enum  
   {  
      ERROR;  
      SUCCESS;  
   }  

Typedef ADC_TypeDef

* @brief Analog to Digital Converter

typedef struct {...} ADC_TypeDef

struct  
   {  
      volatile uint32_t SR;  
      volatile uint32_t CR1;  
      volatile uint32_t CR2;  
      volatile uint32_t SMPR1;  
      volatile uint32_t SMPR2;  
      volatile uint32_t JOFR1;  
      volatile uint32_t JOFR2;  
      volatile uint32_t JOFR3;  
      volatile uint32_t JOFR4;  
      volatile uint32_t HTR;  
      volatile uint32_t LTR;  
      volatile uint32_t SQR1;  
      volatile uint32_t SQR2;  
      volatile uint32_t SQR3;  
      volatile uint32_t JSQR;  
      volatile uint32_t JDR1;  
      volatile uint32_t JDR2;  
      volatile uint32_t JDR3;  
      volatile uint32_t JDR4;  
      volatile uint32_t DR;  
   }  

Typedef ADC_Common_TypeDef

typedef struct {...} ADC_Common_TypeDef
struct  
   {  
      volatile uint32_t CSR;  
      volatile uint32_t CCR;  
      volatile uint32_t CDR;  
   }  

Typedef CAN_TxMailBox_TypeDef

* @brief Controller Area Network TxMailBox

typedef struct {...} CAN_TxMailBox_TypeDef

struct  
   {  
      volatile uint32_t TIR;  
      volatile uint32_t TDTR;  
      volatile uint32_t TDLR;  
      volatile uint32_t TDHR;  
   }  

Typedef CAN_FIFOMailBox_TypeDef

* @brief Controller Area Network FIFOMailBox

typedef struct {...} CAN_FIFOMailBox_TypeDef

struct  
   {  
      volatile uint32_t RIR;  
      volatile uint32_t RDTR;  
      volatile uint32_t RDLR;  
      volatile uint32_t RDHR;  
   }  

Typedef CAN_FilterRegister_TypeDef

* @brief Controller Area Network FilterRegister

typedef struct {...} CAN_FilterRegister_TypeDef

struct  
   {  
      volatile uint32_t FR1;  
      volatile uint32_t FR2;  
   }  

Typedef CAN_TypeDef

* @brief Controller Area Network

typedef struct {...} CAN_TypeDef

struct  
   {  
      volatile uint32_t MCR;  
      volatile uint32_t MSR;  
      volatile uint32_t TSR;  
      volatile uint32_t RF0R;  
      volatile uint32_t RF1R;  
      volatile uint32_t IER;  
      volatile uint32_t ESR;  
      volatile uint32_t BTR;  
      uint32_t RESERVED0[88];  
      CAN_TxMailBox_TypeDef sTxMailBox[3];  
      CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];  
      uint32_t RESERVED1[12];  
      volatile uint32_t FMR;  
      volatile uint32_t FM1R;  
      uint32_t RESERVED2;  
      volatile uint32_t FS1R;  
      uint32_t RESERVED3;  
      volatile uint32_t FFA1R;  
      uint32_t RESERVED4;  
      volatile uint32_t FA1R;  
      uint32_t RESERVED5[8];  
      CAN_FilterRegister_TypeDef sFilterRegister[28];  
   }  

Typedef CRC_TypeDef

* @brief CRC calculation unit

typedef struct {...} CRC_TypeDef

struct  
   {  
      volatile uint32_t DR;  
      volatile uint8_t IDR;  
      uint8_t RESERVED0;  
      uint16_t RESERVED1;  
      volatile uint32_t CR;  
   }  

Typedef DAC_TypeDef

* @brief Digital to Analog Converter

typedef struct {...} DAC_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t SWTRIGR;  
      volatile uint32_t DHR12R1;  
      volatile uint32_t DHR12L1;  
      volatile uint32_t DHR8R1;  
      volatile uint32_t DHR12R2;  
      volatile uint32_t DHR12L2;  
      volatile uint32_t DHR8R2;  
      volatile uint32_t DHR12RD;  
      volatile uint32_t DHR12LD;  
      volatile uint32_t DHR8RD;  
      volatile uint32_t DOR1;  
      volatile uint32_t DOR2;  
      volatile uint32_t SR;  
   }  

Typedef DBGMCU_TypeDef

* @brief Debug MCU

typedef struct {...} DBGMCU_TypeDef

struct  
   {  
      volatile uint32_t IDCODE;  
      volatile uint32_t CR;  
      volatile uint32_t APB1FZ;  
      volatile uint32_t APB2FZ;  
   }  

Typedef DCMI_TypeDef

* @brief DCMI

typedef struct {...} DCMI_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t SR;  
      volatile uint32_t RISR;  
      volatile uint32_t IER;  
      volatile uint32_t MISR;  
      volatile uint32_t ICR;  
      volatile uint32_t ESCR;  
      volatile uint32_t ESUR;  
      volatile uint32_t CWSTRTR;  
      volatile uint32_t CWSIZER;  
      volatile uint32_t DR;  
   }  

Typedef DMA_Stream_TypeDef

* @brief DMA Controller

typedef struct {...} DMA_Stream_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t NDTR;  
      volatile uint32_t PAR;  
      volatile uint32_t M0AR;  
      volatile uint32_t M1AR;  
      volatile uint32_t FCR;  
   }  

Typedef DMA_TypeDef

typedef struct {...} DMA_TypeDef
struct  
   {  
      volatile uint32_t LISR;  
      volatile uint32_t HISR;  
      volatile uint32_t LIFCR;  
      volatile uint32_t HIFCR;  
   }  

Typedef ETH_TypeDef

* @brief Ethernet MAC

typedef struct {...} ETH_TypeDef

struct  
   {  
      volatile uint32_t MACCR;  
      volatile uint32_t MACFFR;  
      volatile uint32_t MACHTHR;  
      volatile uint32_t MACHTLR;  
      volatile uint32_t MACMIIAR;  
      volatile uint32_t MACMIIDR;  
      volatile uint32_t MACFCR;  
      volatile uint32_t MACVLANTR;  
      uint32_t RESERVED0[2];  
      volatile uint32_t MACRWUFFR;  
      volatile uint32_t MACPMTCSR;  
      uint32_t RESERVED1[2];  
      volatile uint32_t MACSR;  
      volatile uint32_t MACIMR;  
      volatile uint32_t MACA0HR;  
      volatile uint32_t MACA0LR;  
      volatile uint32_t MACA1HR;  
      volatile uint32_t MACA1LR;  
      volatile uint32_t MACA2HR;  
      volatile uint32_t MACA2LR;  
      volatile uint32_t MACA3HR;  
      volatile uint32_t MACA3LR;  
      uint32_t RESERVED2[40];  
      volatile uint32_t MMCCR;  
      volatile uint32_t MMCRIR;  
      volatile uint32_t MMCTIR;  
      volatile uint32_t MMCRIMR;  
      volatile uint32_t MMCTIMR;  
      uint32_t RESERVED3[14];  
      volatile uint32_t MMCTGFSCCR;  
      volatile uint32_t MMCTGFMSCCR;  
      uint32_t RESERVED4[5];  
      volatile uint32_t MMCTGFCR;  
      uint32_t RESERVED5[10];  
      volatile uint32_t MMCRFCECR;  
      volatile uint32_t MMCRFAECR;  
      uint32_t RESERVED6[10];  
      volatile uint32_t MMCRGUFCR;  
      uint32_t RESERVED7[334];  
      volatile uint32_t PTPTSCR;  
      volatile uint32_t PTPSSIR;  
      volatile uint32_t PTPTSHR;  
      volatile uint32_t PTPTSLR;  
      volatile uint32_t PTPTSHUR;  
      volatile uint32_t PTPTSLUR;  
      volatile uint32_t PTPTSAR;  
      volatile uint32_t PTPTTHR;  
      volatile uint32_t PTPTTLR;  
      volatile uint32_t RESERVED8;  
      volatile uint32_t PTPTSSR;  
      uint32_t RESERVED9[565];  
      volatile uint32_t DMABMR;  
      volatile uint32_t DMATPDR;  
      volatile uint32_t DMARPDR;  
      volatile uint32_t DMARDLAR;  
      volatile uint32_t DMATDLAR;  
      volatile uint32_t DMASR;  
      volatile uint32_t DMAOMR;  
      volatile uint32_t DMAIER;  
      volatile uint32_t DMAMFBOCR;  
      volatile uint32_t DMARSWTR;  
      uint32_t RESERVED10[8];  
      volatile uint32_t DMACHTDR;  
      volatile uint32_t DMACHRDR;  
      volatile uint32_t DMACHTBAR;  
      volatile uint32_t DMACHRBAR;  
   }  

Typedef EXTI_TypeDef

* @brief External Interrupt/Event Controller

typedef struct {...} EXTI_TypeDef

struct  
   {  
      volatile uint32_t IMR;  
      volatile uint32_t EMR;  
      volatile uint32_t RTSR;  
      volatile uint32_t FTSR;  
      volatile uint32_t SWIER;  
      volatile uint32_t PR;  
   }  

Typedef FLASH_TypeDef

* @brief FLASH Registers

typedef struct {...} FLASH_TypeDef

struct  
   {  
      volatile uint32_t ACR;  
      volatile uint32_t KEYR;  
      volatile uint32_t OPTKEYR;  
      volatile uint32_t SR;  
      volatile uint32_t CR;  
      volatile uint32_t OPTCR;  
   }  

Typedef FSMC_Bank1_TypeDef

* @brief Flexible Static Memory Controller

typedef struct {...} FSMC_Bank1_TypeDef

struct  
   {  
      volatile uint32_t BTCR[8];  
   }  

Typedef FSMC_Bank1E_TypeDef

* @brief Flexible Static Memory Controller Bank1E

typedef struct {...} FSMC_Bank1E_TypeDef

struct  
   {  
      volatile uint32_t BWTR[7];  
   }  

Typedef FSMC_Bank2_TypeDef

* @brief Flexible Static Memory Controller Bank2

typedef struct {...} FSMC_Bank2_TypeDef

struct  
   {  
      volatile uint32_t PCR2;  
      volatile uint32_t SR2;  
      volatile uint32_t PMEM2;  
      volatile uint32_t PATT2;  
      uint32_t RESERVED0;  
      volatile uint32_t ECCR2;  
   }  

Typedef FSMC_Bank3_TypeDef

* @brief Flexible Static Memory Controller Bank3

typedef struct {...} FSMC_Bank3_TypeDef

struct  
   {  
      volatile uint32_t PCR3;  
      volatile uint32_t SR3;  
      volatile uint32_t PMEM3;  
      volatile uint32_t PATT3;  
      uint32_t RESERVED0;  
      volatile uint32_t ECCR3;  
   }  

Typedef FSMC_Bank4_TypeDef

* @brief Flexible Static Memory Controller Bank4

typedef struct {...} FSMC_Bank4_TypeDef

struct  
   {  
      volatile uint32_t PCR4;  
      volatile uint32_t SR4;  
      volatile uint32_t PMEM4;  
      volatile uint32_t PATT4;  
      volatile uint32_t PIO4;  
   }  

Typedef GPIO_TypeDef

* @brief General Purpose I/O

typedef struct {...} GPIO_TypeDef

struct  
   {  
      volatile uint32_t MODER;  
      volatile uint32_t OTYPER;  
      volatile uint32_t OSPEEDR;  
      volatile uint32_t PUPDR;  
      volatile uint32_t IDR;  
      volatile uint32_t ODR;  
      volatile uint16_t BSRRL;  
      volatile uint16_t BSRRH;  
      volatile uint32_t LCKR;  
      volatile uint32_t AFR[2];  
   }  

Typedef SYSCFG_TypeDef

* @brief System configuration controller

typedef struct {...} SYSCFG_TypeDef

struct  
   {  
      volatile uint32_t MEMRMP;  
      volatile uint32_t PMC;  
      volatile uint32_t EXTICR[4];  
      uint32_t RESERVED[2];  
      volatile uint32_t CMPCR;  
   }  

Typedef I2C_TypeDef

* @brief Inter-integrated Circuit Interface

typedef struct {...} I2C_TypeDef

struct  
   {  
      volatile uint16_t CR1;  
      uint16_t RESERVED0;  
      volatile uint16_t CR2;  
      uint16_t RESERVED1;  
      volatile uint16_t OAR1;  
      uint16_t RESERVED2;  
      volatile uint16_t OAR2;  
      uint16_t RESERVED3;  
      volatile uint16_t DR;  
      uint16_t RESERVED4;  
      volatile uint16_t SR1;  
      uint16_t RESERVED5;  
      volatile uint16_t SR2;  
      uint16_t RESERVED6;  
      volatile uint16_t CCR;  
      uint16_t RESERVED7;  
      volatile uint16_t TRISE;  
      uint16_t RESERVED8;  
   }  

Typedef IWDG_TypeDef

* @brief Independent WATCHDOG

typedef struct {...} IWDG_TypeDef

struct  
   {  
      volatile uint32_t KR;  
      volatile uint32_t PR;  
      volatile uint32_t RLR;  
      volatile uint32_t SR;  
   }  

Typedef PWR_TypeDef

* @brief Power Control

typedef struct {...} PWR_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t CSR;  
   }  

Typedef RCC_TypeDef

* @brief Reset and Clock Control

typedef struct {...} RCC_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t PLLCFGR;  
      volatile uint32_t CFGR;  
      volatile uint32_t CIR;  
      volatile uint32_t AHB1RSTR;  
      volatile uint32_t AHB2RSTR;  
      volatile uint32_t AHB3RSTR;  
      uint32_t RESERVED0;  
      volatile uint32_t APB1RSTR;  
      volatile uint32_t APB2RSTR;  
      uint32_t RESERVED1[2];  
      volatile uint32_t AHB1ENR;  
      volatile uint32_t AHB2ENR;  
      volatile uint32_t AHB3ENR;  
      uint32_t RESERVED2;  
      volatile uint32_t APB1ENR;  
      volatile uint32_t APB2ENR;  
      uint32_t RESERVED3[2];  
      volatile uint32_t AHB1LPENR;  
      volatile uint32_t AHB2LPENR;  
      volatile uint32_t AHB3LPENR;  
      uint32_t RESERVED4;  
      volatile uint32_t APB1LPENR;  
      volatile uint32_t APB2LPENR;  
      uint32_t RESERVED5[2];  
      volatile uint32_t BDCR;  
      volatile uint32_t CSR;  
      uint32_t RESERVED6[2];  
      volatile uint32_t SSCGR;  
      volatile uint32_t PLLI2SCFGR;  
   }  

Typedef RTC_TypeDef

* @brief Real-Time Clock

typedef struct {...} RTC_TypeDef

struct  
   {  
      volatile uint32_t TR;  
      volatile uint32_t DR;  
      volatile uint32_t CR;  
      volatile uint32_t ISR;  
      volatile uint32_t PRER;  
      volatile uint32_t WUTR;  
      volatile uint32_t CALIBR;  
      volatile uint32_t ALRMAR;  
      volatile uint32_t ALRMBR;  
      volatile uint32_t WPR;  
      uint32_t RESERVED1;  
      uint32_t RESERVED2;  
      volatile uint32_t TSTR;  
      volatile uint32_t TSDR;  
      uint32_t RESERVED3;  
      uint32_t RESERVED4;  
      volatile uint32_t TAFCR;  
      uint32_t RESERVED5;  
      uint32_t RESERVED6;  
      uint32_t RESERVED7;  
      volatile uint32_t BKP0R;  
      volatile uint32_t BKP1R;  
      volatile uint32_t BKP2R;  
      volatile uint32_t BKP3R;  
      volatile uint32_t BKP4R;  
      volatile uint32_t BKP5R;  
      volatile uint32_t BKP6R;  
      volatile uint32_t BKP7R;  
      volatile uint32_t BKP8R;  
      volatile uint32_t BKP9R;  
      volatile uint32_t BKP10R;  
      volatile uint32_t BKP11R;  
      volatile uint32_t BKP12R;  
      volatile uint32_t BKP13R;  
      volatile uint32_t BKP14R;  
      volatile uint32_t BKP15R;  
      volatile uint32_t BKP16R;  
      volatile uint32_t BKP17R;  
      volatile uint32_t BKP18R;  
      volatile uint32_t BKP19R;  
   }  

Typedef SDIO_TypeDef

* @brief SD host Interface

typedef struct {...} SDIO_TypeDef

struct  
   {  
      volatile uint32_t POWER;  
      volatile uint32_t CLKCR;  
      volatile uint32_t ARG;  
      volatile uint32_t CMD;  
      volatile const uint32_t RESPCMD;  
      volatile const uint32_t RESP1;  
      volatile const uint32_t RESP2;  
      volatile const uint32_t RESP3;  
      volatile const uint32_t RESP4;  
      volatile uint32_t DTIMER;  
      volatile uint32_t DLEN;  
      volatile uint32_t DCTRL;  
      volatile const uint32_t DCOUNT;  
      volatile const uint32_t STA;  
      volatile uint32_t ICR;  
      volatile uint32_t MASK;  
      uint32_t RESERVED0[2];  
      volatile const uint32_t FIFOCNT;  
      uint32_t RESERVED1[13];  
      volatile uint32_t FIFO;  
   }  

Typedef SPI_TypeDef

* @brief Serial Peripheral Interface

typedef struct {...} SPI_TypeDef

struct  
   {  
      volatile uint16_t CR1;  
      uint16_t RESERVED0;  
      volatile uint16_t CR2;  
      uint16_t RESERVED1;  
      volatile uint16_t SR;  
      uint16_t RESERVED2;  
      volatile uint16_t DR;  
      uint16_t RESERVED3;  
      volatile uint16_t CRCPR;  
      uint16_t RESERVED4;  
      volatile uint16_t RXCRCR;  
      uint16_t RESERVED5;  
      volatile uint16_t TXCRCR;  
      uint16_t RESERVED6;  
      volatile uint16_t I2SCFGR;  
      uint16_t RESERVED7;  
      volatile uint16_t I2SPR;  
      uint16_t RESERVED8;  
   }  

Typedef TIM_TypeDef

* @brief TIM

typedef struct {...} TIM_TypeDef

struct  
   {  
      volatile uint16_t CR1;  
      uint16_t RESERVED0;  
      volatile uint16_t CR2;  
      uint16_t RESERVED1;  
      volatile uint16_t SMCR;  
      uint16_t RESERVED2;  
      volatile uint16_t DIER;  
      uint16_t RESERVED3;  
      volatile uint16_t SR;  
      uint16_t RESERVED4;  
      volatile uint16_t EGR;  
      uint16_t RESERVED5;  
      volatile uint16_t CCMR1;  
      uint16_t RESERVED6;  
      volatile uint16_t CCMR2;  
      uint16_t RESERVED7;  
      volatile uint16_t CCER;  
      uint16_t RESERVED8;  
      volatile uint32_t CNT;  
      volatile uint16_t PSC;  
      uint16_t RESERVED9;  
      volatile uint32_t ARR;  
      volatile uint16_t RCR;  
      uint16_t RESERVED10;  
      volatile uint32_t CCR1;  
      volatile uint32_t CCR2;  
      volatile uint32_t CCR3;  
      volatile uint32_t CCR4;  
      volatile uint16_t BDTR;  
      uint16_t RESERVED11;  
      volatile uint16_t DCR;  
      uint16_t RESERVED12;  
      volatile uint16_t DMAR;  
      uint16_t RESERVED13;  
      volatile uint16_t OR;  
      uint16_t RESERVED14;  
   }  

Typedef USART_TypeDef

* @brief Universal Synchronous Asynchronous Receiver Transmitter

typedef struct {...} USART_TypeDef

struct  
   {  
      volatile uint16_t SR;  
      uint16_t RESERVED0;  
      volatile uint16_t DR;  
      uint16_t RESERVED1;  
      volatile uint16_t BRR;  
      uint16_t RESERVED2;  
      volatile uint16_t CR1;  
      uint16_t RESERVED3;  
      volatile uint16_t CR2;  
      uint16_t RESERVED4;  
      volatile uint16_t CR3;  
      uint16_t RESERVED5;  
      volatile uint16_t GTPR;  
      uint16_t RESERVED6;  
   }  

Typedef WWDG_TypeDef

* @brief Window WATCHDOG

typedef struct {...} WWDG_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t CFR;  
      volatile uint32_t SR;  
   }  

Typedef CRYP_TypeDef

* @brief Crypto Processor

typedef struct {...} CRYP_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t SR;  
      volatile uint32_t DR;  
      volatile uint32_t DOUT;  
      volatile uint32_t DMACR;  
      volatile uint32_t IMSCR;  
      volatile uint32_t RISR;  
      volatile uint32_t MISR;  
      volatile uint32_t K0LR;  
      volatile uint32_t K0RR;  
      volatile uint32_t K1LR;  
      volatile uint32_t K1RR;  
      volatile uint32_t K2LR;  
      volatile uint32_t K2RR;  
      volatile uint32_t K3LR;  
      volatile uint32_t K3RR;  
      volatile uint32_t IV0LR;  
      volatile uint32_t IV0RR;  
      volatile uint32_t IV1LR;  
      volatile uint32_t IV1RR;  
   }  

Typedef HASH_TypeDef

* @brief HASH

typedef struct {...} HASH_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t DIN;  
      volatile uint32_t STR;  
      volatile uint32_t HR[5];  
      volatile uint32_t IMR;  
      volatile uint32_t SR;  
      uint32_t RESERVED[52];  
      volatile uint32_t CSR[51];  
   }  

Typedef RNG_TypeDef

* @brief HASH

typedef struct {...} RNG_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t SR;  
      volatile uint32_t DR;  
   }