File nut/include/arch/cm3/stm/stm32f2xx_rcc.h

(C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE

Included Files

Preprocessor definitions

****************************************************************************** * @file stm32f2xx_rcc.h * @author MCD Application Team * @version V1.0.0 * @date 18-April-2011 * @brief This file contains all the functions prototypes for the RCC firmware library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2> ******************************************************************************

#define __STM32F2xx_RCC_H

@defgroup RCC_HSE_configuration * @{

#define RCC_HSE_OFF

#define RCC_HSE_ON

#define RCC_HSE_Bypass

#define IS_RCC_HSE( HSE )

@defgroup RCC_PLL_Clock_Source * @{

#define RCC_PLLSource_HSI

#define RCC_PLLSource_HSE

#define IS_RCC_PLL_SOURCE( SOURCE )

#define IS_RCC_PLLM_VALUE( VALUE )

#define IS_RCC_PLLN_VALUE( VALUE )

#define IS_RCC_PLLP_VALUE( VALUE )

#define IS_RCC_PLLQ_VALUE( VALUE )

#define IS_RCC_PLLI2SN_VALUE( VALUE )

#define IS_RCC_PLLI2SR_VALUE( VALUE )

@defgroup RCC_System_Clock_Source * @{

#define RCC_SYSCLKSource_HSI

#define RCC_SYSCLKSource_HSE

#define RCC_SYSCLKSource_PLLCLK

#define IS_RCC_SYSCLK_SOURCE( SOURCE )

@defgroup RCC_AHB_Clock_Source * @{

#define RCC_SYSCLK_Div1

#define RCC_SYSCLK_Div2

#define RCC_SYSCLK_Div4

#define RCC_SYSCLK_Div8

#define RCC_SYSCLK_Div16

#define RCC_SYSCLK_Div64

#define RCC_SYSCLK_Div128

#define RCC_SYSCLK_Div256

#define RCC_SYSCLK_Div512

#define IS_RCC_HCLK( HCLK )

@defgroup RCC_APB1_APB2_Clock_Source * @{

#define RCC_HCLK_Div1

#define RCC_HCLK_Div2

#define RCC_HCLK_Div4

#define RCC_HCLK_Div8

#define RCC_HCLK_Div16

#define IS_RCC_PCLK( PCLK )

@defgroup RCC_Interrupt_Source * @{

#define RCC_IT_LSIRDY

#define RCC_IT_LSERDY

#define RCC_IT_HSIRDY

#define RCC_IT_HSERDY

#define RCC_IT_PLLRDY

#define RCC_IT_PLLI2SRDY

#define RCC_IT_CSS

#define IS_RCC_IT( IT )

#define IS_RCC_GET_IT( IT )

#define IS_RCC_CLEAR_IT( IT )

@defgroup RCC_LSE_Configuration * @{

#define RCC_LSE_OFF

#define RCC_LSE_ON

#define RCC_LSE_Bypass

#define IS_RCC_LSE( LSE )

@defgroup RCC_RTC_Clock_Source * @{

#define RCC_RTCCLKSource_LSE

#define RCC_RTCCLKSource_LSI

#define RCC_RTCCLKSource_HSE_Div2

#define RCC_RTCCLKSource_HSE_Div3

#define RCC_RTCCLKSource_HSE_Div4

#define RCC_RTCCLKSource_HSE_Div5

#define RCC_RTCCLKSource_HSE_Div6

#define RCC_RTCCLKSource_HSE_Div7

#define RCC_RTCCLKSource_HSE_Div8

#define RCC_RTCCLKSource_HSE_Div9

#define RCC_RTCCLKSource_HSE_Div10

#define RCC_RTCCLKSource_HSE_Div11

#define RCC_RTCCLKSource_HSE_Div12

#define RCC_RTCCLKSource_HSE_Div13

#define RCC_RTCCLKSource_HSE_Div14

#define RCC_RTCCLKSource_HSE_Div15

#define RCC_RTCCLKSource_HSE_Div16

#define RCC_RTCCLKSource_HSE_Div17

#define RCC_RTCCLKSource_HSE_Div18

#define RCC_RTCCLKSource_HSE_Div19

#define RCC_RTCCLKSource_HSE_Div20

#define RCC_RTCCLKSource_HSE_Div21

#define RCC_RTCCLKSource_HSE_Div22

#define RCC_RTCCLKSource_HSE_Div23

#define RCC_RTCCLKSource_HSE_Div24

#define RCC_RTCCLKSource_HSE_Div25

#define RCC_RTCCLKSource_HSE_Div26

#define RCC_RTCCLKSource_HSE_Div27

#define RCC_RTCCLKSource_HSE_Div28

#define RCC_RTCCLKSource_HSE_Div29

#define RCC_RTCCLKSource_HSE_Div30

#define RCC_RTCCLKSource_HSE_Div31

#define IS_RCC_RTCCLK_SOURCE( SOURCE )

@defgroup RCC_I2S_Clock_Source * @{

#define RCC_I2S2CLKSource_PLLI2S

#define RCC_I2S2CLKSource_Ext

#define IS_RCC_I2SCLK_SOURCE( SOURCE )

@defgroup RCC_AHB1_Peripherals * @{

#define RCC_AHB1Periph_GPIOA

#define RCC_AHB1Periph_GPIOB

#define RCC_AHB1Periph_GPIOC

#define RCC_AHB1Periph_GPIOD

#define RCC_AHB1Periph_GPIOE

#define RCC_AHB1Periph_GPIOF

#define RCC_AHB1Periph_GPIOG

#define RCC_AHB1Periph_GPIOH

#define RCC_AHB1Periph_GPIOI

#define RCC_AHB1Periph_CRC

#define RCC_AHB1Periph_FLITF

#define RCC_AHB1Periph_SRAM1

#define RCC_AHB1Periph_SRAM2

#define RCC_AHB1Periph_BKPSRAM

#define RCC_AHB1Periph_DMA1

#define RCC_AHB1Periph_DMA2

#define RCC_AHB1Periph_ETH_MAC

#define RCC_AHB1Periph_ETH_MAC_Tx

#define RCC_AHB1Periph_ETH_MAC_Rx

#define RCC_AHB1Periph_ETH_MAC_PTP

#define RCC_AHB1Periph_OTG_HS

#define RCC_AHB1Periph_OTG_HS_ULPI

#define IS_RCC_AHB1_CLOCK_PERIPH( PERIPH )

#define IS_RCC_AHB1_RESET_PERIPH( PERIPH )

#define IS_RCC_AHB1_LPMODE_PERIPH( PERIPH )

@defgroup RCC_AHB2_Peripherals * @{

#define RCC_AHB2Periph_DCMI

#define RCC_AHB2Periph_CRYP

#define RCC_AHB2Periph_HASH

#define RCC_AHB2Periph_RNG

#define RCC_AHB2Periph_OTG_FS

#define IS_RCC_AHB2_PERIPH( PERIPH )

@defgroup RCC_AHB3_Peripherals * @{

#define RCC_AHB3Periph_FSMC

#define IS_RCC_AHB3_PERIPH( PERIPH )

@defgroup RCC_APB1_Peripherals * @{

#define RCC_APB1Periph_TIM2

#define RCC_APB1Periph_TIM3

#define RCC_APB1Periph_TIM4

#define RCC_APB1Periph_TIM5

#define RCC_APB1Periph_TIM6

#define RCC_APB1Periph_TIM7

#define RCC_APB1Periph_TIM12

#define RCC_APB1Periph_TIM13

#define RCC_APB1Periph_TIM14

#define RCC_APB1Periph_WWDG

#define RCC_APB1Periph_SPI2

#define RCC_APB1Periph_SPI3

#define RCC_APB1Periph_USART2

#define RCC_APB1Periph_USART3

#define RCC_APB1Periph_UART4

#define RCC_APB1Periph_UART5

#define RCC_APB1Periph_I2C1

#define RCC_APB1Periph_I2C2

#define RCC_APB1Periph_I2C3

#define RCC_APB1Periph_CAN1

#define RCC_APB1Periph_CAN2

#define RCC_APB1Periph_PWR

#define RCC_APB1Periph_DAC

#define IS_RCC_APB1_PERIPH( PERIPH )

@defgroup RCC_APB2_Peripherals * @{

#define RCC_APB2Periph_TIM1

#define RCC_APB2Periph_TIM8

#define RCC_APB2Periph_USART1

#define RCC_APB2Periph_USART6

#define RCC_APB2Periph_ADC

#define RCC_APB2Periph_ADC1

#define RCC_APB2Periph_ADC2

#define RCC_APB2Periph_ADC3

#define RCC_APB2Periph_SDIO

#define RCC_APB2Periph_SPI1

#define RCC_APB2Periph_SYSCFG

#define RCC_APB2Periph_TIM9

#define RCC_APB2Periph_TIM10

#define RCC_APB2Periph_TIM11

#define IS_RCC_APB2_PERIPH( PERIPH )

#define IS_RCC_APB2_RESET_PERIPH( PERIPH )

@defgroup RCC_MCO1_Clock_Source_Prescaler * @{

#define RCC_MCO1Source_HSI

#define RCC_MCO1Source_LSE

#define RCC_MCO1Source_HSE

#define RCC_MCO1Source_PLLCLK

#define RCC_MCO1Div_1

#define RCC_MCO1Div_2

#define RCC_MCO1Div_3

#define RCC_MCO1Div_4

#define RCC_MCO1Div_5

#define IS_RCC_MCO1SOURCE( SOURCE )

#define IS_RCC_MCO1DIV( DIV )

@defgroup RCC_MCO2_Clock_Source_Prescaler * @{

#define RCC_MCO2Source_SYSCLK

#define RCC_MCO2Source_PLLI2SCLK

#define RCC_MCO2Source_HSE

#define RCC_MCO2Source_PLLCLK

#define RCC_MCO2Div_1

#define RCC_MCO2Div_2

#define RCC_MCO2Div_3

#define RCC_MCO2Div_4

#define RCC_MCO2Div_5

#define IS_RCC_MCO2SOURCE( SOURCE )

#define IS_RCC_MCO2DIV( DIV )

@defgroup RCC_Flag * @{

#define RCC_FLAG_HSIRDY

#define RCC_FLAG_HSERDY

#define RCC_FLAG_PLLRDY

#define RCC_FLAG_PLLI2SRDY

#define RCC_FLAG_LSERDY

#define RCC_FLAG_LSIRDY

#define RCC_FLAG_BORRST

#define RCC_FLAG_PINRST

#define RCC_FLAG_PORRST

#define RCC_FLAG_SFTRST

#define RCC_FLAG_IWDGRST

#define RCC_FLAG_WWDGRST

#define RCC_FLAG_LPWRRST

#define IS_RCC_FLAG( FLAG )

#define IS_RCC_CALIBRATION_VALUE( VALUE )

Typedef RCC_ClocksTypeDef

@addtogroup RCC * @{

typedef struct {...} RCC_ClocksTypeDef

struct  
   {  
      uint32_t SYSCLK_Frequency;  
      uint32_t HCLK_Frequency;  
      uint32_t PCLK1_Frequency;  
      uint32_t PCLK2_Frequency;  
   }