File nut/include/arch/cm3/stm/stm32l1xx.h

Cortex-M3 Processor Exceptions Numbers

Included Files

@addtogroup stm32l1xx * @{

* @}

Preprocessor definitions

#define __STM32L1XX_H

@addtogroup Library_configuration_section * @{

#define STM32L1XX_HD

* @brief In the following line adjust the value of External High Speed oscillator (HSE) used in your application
Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor.

#define HSE_VALUE

* @brief In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value

#define HSE_STARTUP_TIMEOUT

* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup Timeout value

#define HSI_STARTUP_TIMEOUT

#define HSI_VALUE

#define LSI_VALUE

#define LSE_VALUE

* @brief STM32L1xx Standard Peripheral Library version number V1.1.1

#define __STM32L1XX_STDPERIPH_VERSION_MAIN 0x01

#define __STM32L1XX_STDPERIPH_VERSION_SUB1 0x01

#define __STM32L1XX_STDPERIPH_VERSION_SUB2 0x01

#define __STM32L1XX_STDPERIPH_VERSION_RC 0x00

#define __STM32L1XX_STDPERIPH_VERSION

* @brief STM32L1xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section

#define __CM3_REV 0x200

#define __MPU_PRESENT 1

#define __NVIC_PRIO_BITS 4

#define __Vendor_SysTickConfig 0

#define IS_FUNCTIONAL_STATE( STATE )

#define __RAM_FUNC

@addtogroup Peripheral_memory_map * @{

#define FLASH_BASE

#define SRAM_BASE

#define PERIPH_BASE

#define SRAM_BB_BASE

#define PERIPH_BB_BASE

#define FSMC_R_BASE

#define APB1PERIPH_BASE PERIPH_BASE

#define APB2PERIPH_BASE

#define AHBPERIPH_BASE

#define TIM2_BASE

#define TIM3_BASE

#define TIM4_BASE

#define TIM5_BASE

#define TIM6_BASE

#define TIM7_BASE

#define LCD_BASE

#define RTC_BASE

#define WWDG_BASE

#define IWDG_BASE

#define SPI2_BASE

#define SPI3_BASE

#define USART2_BASE

#define USART3_BASE

#define UART4_BASE

#define UART5_BASE

#define I2C1_BASE

#define I2C2_BASE

#define PWR_BASE

#define DAC_BASE

#define COMP_BASE

#define RI_BASE

#define OPAMP_BASE

#define SYSCFG_BASE

#define EXTI_BASE

#define TIM9_BASE

#define TIM10_BASE

#define TIM11_BASE

#define ADC1_BASE

#define ADC_BASE

#define SDIO_BASE

#define SPI1_BASE

#define USART1_BASE

#define GPIOA_BASE

#define GPIOB_BASE

#define GPIOC_BASE

#define GPIOD_BASE

#define GPIOE_BASE

#define GPIOH_BASE

#define GPIOF_BASE

#define GPIOG_BASE

#define CRC_BASE

#define RCC_BASE

#define FLASH_R_BASE

#define OB_BASE

#define DMA1_BASE

#define DMA1_Channel1_BASE

#define DMA1_Channel2_BASE

#define DMA1_Channel3_BASE

#define DMA1_Channel4_BASE

#define DMA1_Channel5_BASE

#define DMA1_Channel6_BASE

#define DMA1_Channel7_BASE

#define DMA2_BASE

#define DMA2_Channel1_BASE

#define DMA2_Channel2_BASE

#define DMA2_Channel3_BASE

#define DMA2_Channel4_BASE

#define DMA2_Channel5_BASE

#define AES_BASE

#define FSMC_Bank1_R_BASE

#define FSMC_Bank1E_R_BASE

#define DBGMCU_BASE

@addtogroup Peripheral_declaration * @{

#define TIM2

#define TIM3

#define TIM4

#define TIM5

#define TIM6

#define TIM7

#define LCD

#define RTC

#define WWDG

#define IWDG

#define SPI2

#define SPI3

#define USART2

#define USART3

#define UART4

#define UART5

#define I2C1

#define I2C2

#define PWR

#define DAC

#define COMP

#define RI

#define OPAMP

#define SYSCFG

#define EXTI

#define ADC1

#define ADC

#define SDIO

#define TIM9

#define TIM10

#define TIM11

#define SPI1

#define USART1

#define DMA1

#define DMA1_Channel1

#define DMA1_Channel2

#define DMA1_Channel3

#define DMA1_Channel4

#define DMA1_Channel5

#define DMA1_Channel6

#define DMA1_Channel7

#define DMA2

#define DMA2_Channel1

#define DMA2_Channel2

#define DMA2_Channel3

#define DMA2_Channel4

#define DMA2_Channel5

#define RCC

#define CRC

#define GPIOA

#define GPIOB

#define GPIOC

#define GPIOD

#define GPIOE

#define GPIOH

#define GPIOF

#define GPIOG

#define FLASH

#define OB

#define AES

#define FSMC_Bank1

#define FSMC_Bank1E

#define DBGMCU

#define ADC_SR_AWD

#define ADC_SR_EOC

#define ADC_SR_JEOC

#define ADC_SR_JSTRT

#define ADC_SR_STRT

#define ADC_SR_OVR

#define ADC_SR_ADONS

#define ADC_SR_RCNR

#define ADC_SR_JCNR

#define ADC_CR1_AWDCH

#define ADC_CR1_AWDCH_0

#define ADC_CR1_AWDCH_1

#define ADC_CR1_AWDCH_2

#define ADC_CR1_AWDCH_3

#define ADC_CR1_AWDCH_4

#define ADC_CR1_EOCIE

#define ADC_CR1_AWDIE

#define ADC_CR1_JEOCIE

#define ADC_CR1_SCAN

#define ADC_CR1_AWDSGL

#define ADC_CR1_JAUTO

#define ADC_CR1_DISCEN

#define ADC_CR1_JDISCEN

#define ADC_CR1_DISCNUM

#define ADC_CR1_DISCNUM_0

#define ADC_CR1_DISCNUM_1

#define ADC_CR1_DISCNUM_2

#define ADC_CR1_PDD

#define ADC_CR1_PDI

#define ADC_CR1_JAWDEN

#define ADC_CR1_AWDEN

#define ADC_CR1_RES

#define ADC_CR1_RES_0

#define ADC_CR1_RES_1

#define ADC_CR1_OVRIE

#define ADC_CR2_ADON

#define ADC_CR2_CONT

#define ADC_CR2_CFG

#define ADC_CR2_DELS

#define ADC_CR2_DELS_0

#define ADC_CR2_DELS_1

#define ADC_CR2_DELS_2

#define ADC_CR2_DMA

#define ADC_CR2_DDS

#define ADC_CR2_EOCS

#define ADC_CR2_ALIGN

#define ADC_CR2_JEXTSEL

#define ADC_CR2_JEXTSEL_0

#define ADC_CR2_JEXTSEL_1

#define ADC_CR2_JEXTSEL_2

#define ADC_CR2_JEXTSEL_3

#define ADC_CR2_JEXTEN

#define ADC_CR2_JEXTEN_0

#define ADC_CR2_JEXTEN_1

#define ADC_CR2_JSWSTART

#define ADC_CR2_EXTSEL

#define ADC_CR2_EXTSEL_0

#define ADC_CR2_EXTSEL_1

#define ADC_CR2_EXTSEL_2

#define ADC_CR2_EXTSEL_3

#define ADC_CR2_EXTEN

#define ADC_CR2_EXTEN_0

#define ADC_CR2_EXTEN_1

#define ADC_CR2_SWSTART

#define ADC_SMPR1_SMP20

#define ADC_SMPR1_SMP20_0

#define ADC_SMPR1_SMP20_1

#define ADC_SMPR1_SMP20_2

#define ADC_SMPR1_SMP21

#define ADC_SMPR1_SMP21_0

#define ADC_SMPR1_SMP21_1

#define ADC_SMPR1_SMP21_2

#define ADC_SMPR1_SMP22

#define ADC_SMPR1_SMP22_0

#define ADC_SMPR1_SMP22_1

#define ADC_SMPR1_SMP22_2

#define ADC_SMPR1_SMP23

#define ADC_SMPR1_SMP23_0

#define ADC_SMPR1_SMP23_1

#define ADC_SMPR1_SMP23_2

#define ADC_SMPR1_SMP24

#define ADC_SMPR1_SMP24_0

#define ADC_SMPR1_SMP24_1

#define ADC_SMPR1_SMP24_2

#define ADC_SMPR1_SMP25

#define ADC_SMPR1_SMP25_0

#define ADC_SMPR1_SMP25_1

#define ADC_SMPR1_SMP25_2

#define ADC_SMPR1_SMP26

#define ADC_SMPR1_SMP26_0

#define ADC_SMPR1_SMP26_1

#define ADC_SMPR1_SMP26_2

#define ADC_SMPR1_SMP27

#define ADC_SMPR1_SMP27_0

#define ADC_SMPR1_SMP27_1

#define ADC_SMPR1_SMP27_2

#define ADC_SMPR1_SMP28

#define ADC_SMPR1_SMP28_0

#define ADC_SMPR1_SMP28_1

#define ADC_SMPR1_SMP28_2

#define ADC_SMPR1_SMP29

#define ADC_SMPR1_SMP29_0

#define ADC_SMPR1_SMP29_1

#define ADC_SMPR1_SMP29_2

#define ADC_SMPR2_SMP10

#define ADC_SMPR2_SMP10_0

#define ADC_SMPR2_SMP10_1

#define ADC_SMPR2_SMP10_2

#define ADC_SMPR2_SMP11

#define ADC_SMPR2_SMP11_0

#define ADC_SMPR2_SMP11_1

#define ADC_SMPR2_SMP11_2

#define ADC_SMPR2_SMP12

#define ADC_SMPR2_SMP12_0

#define ADC_SMPR2_SMP12_1

#define ADC_SMPR2_SMP12_2

#define ADC_SMPR2_SMP13

#define ADC_SMPR2_SMP13_0

#define ADC_SMPR2_SMP13_1

#define ADC_SMPR2_SMP13_2

#define ADC_SMPR2_SMP14

#define ADC_SMPR2_SMP14_0

#define ADC_SMPR2_SMP14_1

#define ADC_SMPR2_SMP14_2

#define ADC_SMPR2_SMP15

#define ADC_SMPR2_SMP15_0

#define ADC_SMPR2_SMP15_1

#define ADC_SMPR2_SMP15_2

#define ADC_SMPR2_SMP16

#define ADC_SMPR2_SMP16_0

#define ADC_SMPR2_SMP16_1

#define ADC_SMPR2_SMP16_2

#define ADC_SMPR2_SMP17

#define ADC_SMPR2_SMP17_0

#define ADC_SMPR2_SMP17_1

#define ADC_SMPR2_SMP17_2

#define ADC_SMPR2_SMP18

#define ADC_SMPR2_SMP18_0

#define ADC_SMPR2_SMP18_1

#define ADC_SMPR2_SMP18_2

#define ADC_SMPR2_SMP19

#define ADC_SMPR2_SMP19_0

#define ADC_SMPR2_SMP19_1

#define ADC_SMPR2_SMP19_2

#define ADC_SMPR3_SMP0

#define ADC_SMPR3_SMP0_0

#define ADC_SMPR3_SMP0_1

#define ADC_SMPR3_SMP0_2

#define ADC_SMPR3_SMP1

#define ADC_SMPR3_SMP1_0

#define ADC_SMPR3_SMP1_1

#define ADC_SMPR3_SMP1_2

#define ADC_SMPR3_SMP2

#define ADC_SMPR3_SMP2_0

#define ADC_SMPR3_SMP2_1

#define ADC_SMPR3_SMP2_2

#define ADC_SMPR3_SMP3

#define ADC_SMPR3_SMP3_0

#define ADC_SMPR3_SMP3_1

#define ADC_SMPR3_SMP3_2

#define ADC_SMPR3_SMP4

#define ADC_SMPR3_SMP4_0

#define ADC_SMPR3_SMP4_1

#define ADC_SMPR3_SMP4_2

#define ADC_SMPR3_SMP5

#define ADC_SMPR3_SMP5_0

#define ADC_SMPR3_SMP5_1

#define ADC_SMPR3_SMP5_2

#define ADC_SMPR3_SMP6

#define ADC_SMPR3_SMP6_0

#define ADC_SMPR3_SMP6_1

#define ADC_SMPR3_SMP6_2

#define ADC_SMPR3_SMP7

#define ADC_SMPR3_SMP7_0

#define ADC_SMPR3_SMP7_1

#define ADC_SMPR3_SMP7_2

#define ADC_SMPR3_SMP8

#define ADC_SMPR3_SMP8_0

#define ADC_SMPR3_SMP8_1

#define ADC_SMPR3_SMP8_2

#define ADC_SMPR3_SMP9

#define ADC_SMPR3_SMP9_0

#define ADC_SMPR3_SMP9_1

#define ADC_SMPR3_SMP9_2

#define ADC_JOFR1_JOFFSET1

#define ADC_JOFR2_JOFFSET2

#define ADC_JOFR3_JOFFSET3

#define ADC_JOFR4_JOFFSET4

#define ADC_HTR_HT

#define ADC_LTR_LT

#define ADC_SQR1_L

#define ADC_SQR1_L_0

#define ADC_SQR1_L_1

#define ADC_SQR1_L_2

#define ADC_SQR1_L_3

#define ADC_SQR1_SQ28

#define ADC_SQR1_SQ28_0

#define ADC_SQR1_SQ28_1

#define ADC_SQR1_SQ28_2

#define ADC_SQR1_SQ28_3

#define ADC_SQR1_SQ28_4

#define ADC_SQR1_SQ27

#define ADC_SQR1_SQ27_0

#define ADC_SQR1_SQ27_1

#define ADC_SQR1_SQ27_2

#define ADC_SQR1_SQ27_3

#define ADC_SQR1_SQ27_4

#define ADC_SQR1_SQ26

#define ADC_SQR1_SQ26_0

#define ADC_SQR1_SQ26_1

#define ADC_SQR1_SQ26_2

#define ADC_SQR1_SQ26_3

#define ADC_SQR1_SQ26_4

#define ADC_SQR1_SQ25

#define ADC_SQR1_SQ25_0

#define ADC_SQR1_SQ25_1

#define ADC_SQR1_SQ25_2

#define ADC_SQR1_SQ25_3

#define ADC_SQR1_SQ25_4

#define ADC_SQR2_SQ19

#define ADC_SQR2_SQ19_0

#define ADC_SQR2_SQ19_1

#define ADC_SQR2_SQ19_2

#define ADC_SQR2_SQ19_3

#define ADC_SQR2_SQ19_4

#define ADC_SQR2_SQ20

#define ADC_SQR2_SQ20_0

#define ADC_SQR2_SQ20_1

#define ADC_SQR2_SQ20_2

#define ADC_SQR2_SQ20_3

#define ADC_SQR2_SQ20_4

#define ADC_SQR2_SQ21

#define ADC_SQR2_SQ21_0

#define ADC_SQR2_SQ21_1

#define ADC_SQR2_SQ21_2

#define ADC_SQR2_SQ21_3

#define ADC_SQR2_SQ21_4

#define ADC_SQR2_SQ22

#define ADC_SQR2_SQ22_0

#define ADC_SQR2_SQ22_1

#define ADC_SQR2_SQ22_2

#define ADC_SQR2_SQ22_3

#define ADC_SQR2_SQ22_4

#define ADC_SQR2_SQ23

#define ADC_SQR2_SQ23_0

#define ADC_SQR2_SQ23_1

#define ADC_SQR2_SQ23_2

#define ADC_SQR2_SQ23_3

#define ADC_SQR2_SQ23_4

#define ADC_SQR2_SQ24

#define ADC_SQR2_SQ24_0

#define ADC_SQR2_SQ24_1

#define ADC_SQR2_SQ24_2

#define ADC_SQR2_SQ24_3

#define ADC_SQR2_SQ24_4

#define ADC_SQR3_SQ13

#define ADC_SQR3_SQ13_0

#define ADC_SQR3_SQ13_1

#define ADC_SQR3_SQ13_2

#define ADC_SQR3_SQ13_3

#define ADC_SQR3_SQ13_4

#define ADC_SQR3_SQ14

#define ADC_SQR3_SQ14_0

#define ADC_SQR3_SQ14_1

#define ADC_SQR3_SQ14_2

#define ADC_SQR3_SQ14_3

#define ADC_SQR3_SQ14_4

#define ADC_SQR3_SQ15

#define ADC_SQR3_SQ15_0

#define ADC_SQR3_SQ15_1

#define ADC_SQR3_SQ15_2

#define ADC_SQR3_SQ15_3

#define ADC_SQR3_SQ15_4

#define ADC_SQR3_SQ16

#define ADC_SQR3_SQ16_0

#define ADC_SQR3_SQ16_1

#define ADC_SQR3_SQ16_2

#define ADC_SQR3_SQ16_3

#define ADC_SQR3_SQ16_4

#define ADC_SQR3_SQ17

#define ADC_SQR3_SQ17_0

#define ADC_SQR3_SQ17_1

#define ADC_SQR3_SQ17_2

#define ADC_SQR3_SQ17_3

#define ADC_SQR3_SQ17_4

#define ADC_SQR3_SQ18

#define ADC_SQR3_SQ18_0

#define ADC_SQR3_SQ18_1

#define ADC_SQR3_SQ18_2

#define ADC_SQR3_SQ18_3

#define ADC_SQR3_SQ18_4

#define ADC_SQR4_SQ7

#define ADC_SQR4_SQ7_0

#define ADC_SQR4_SQ7_1

#define ADC_SQR4_SQ7_2

#define ADC_SQR4_SQ7_3

#define ADC_SQR4_SQ7_4

#define ADC_SQR4_SQ8

#define ADC_SQR4_SQ8_0

#define ADC_SQR4_SQ8_1

#define ADC_SQR4_SQ8_2

#define ADC_SQR4_SQ8_3

#define ADC_SQR4_SQ8_4

#define ADC_SQR4_SQ9

#define ADC_SQR4_SQ9_0

#define ADC_SQR4_SQ9_1

#define ADC_SQR4_SQ9_2

#define ADC_SQR4_SQ9_3

#define ADC_SQR4_SQ9_4

#define ADC_SQR4_SQ10

#define ADC_SQR4_SQ10_0

#define ADC_SQR4_SQ10_1

#define ADC_SQR4_SQ10_2

#define ADC_SQR4_SQ10_3

#define ADC_SQR4_SQ10_4

#define ADC_SQR4_SQ11

#define ADC_SQR4_SQ11_0

#define ADC_SQR4_SQ11_1

#define ADC_SQR4_SQ11_2

#define ADC_SQR4_SQ11_3

#define ADC_SQR4_SQ11_4

#define ADC_SQR4_SQ12

#define ADC_SQR4_SQ12_0

#define ADC_SQR4_SQ12_1

#define ADC_SQR4_SQ12_2

#define ADC_SQR4_SQ12_3

#define ADC_SQR4_SQ12_4

#define ADC_SQR5_SQ1

#define ADC_SQR5_SQ1_0

#define ADC_SQR5_SQ1_1

#define ADC_SQR5_SQ1_2

#define ADC_SQR5_SQ1_3

#define ADC_SQR5_SQ1_4

#define ADC_SQR5_SQ2

#define ADC_SQR5_SQ2_0

#define ADC_SQR5_SQ2_1

#define ADC_SQR5_SQ2_2

#define ADC_SQR5_SQ2_3

#define ADC_SQR5_SQ2_4

#define ADC_SQR5_SQ3

#define ADC_SQR5_SQ3_0

#define ADC_SQR5_SQ3_1

#define ADC_SQR5_SQ3_2

#define ADC_SQR5_SQ3_3

#define ADC_SQR5_SQ3_4

#define ADC_SQR5_SQ4

#define ADC_SQR5_SQ4_0

#define ADC_SQR5_SQ4_1

#define ADC_SQR5_SQ4_2

#define ADC_SQR5_SQ4_3

#define ADC_SQR5_SQ4_4

#define ADC_SQR5_SQ5

#define ADC_SQR5_SQ5_0

#define ADC_SQR5_SQ5_1

#define ADC_SQR5_SQ5_2

#define ADC_SQR5_SQ5_3

#define ADC_SQR5_SQ5_4

#define ADC_SQR5_SQ6

#define ADC_SQR5_SQ6_0

#define ADC_SQR5_SQ6_1

#define ADC_SQR5_SQ6_2

#define ADC_SQR5_SQ6_3

#define ADC_SQR5_SQ6_4

#define ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_4

#define ADC_JSQR_JL

#define ADC_JSQR_JL_0

#define ADC_JSQR_JL_1

#define ADC_JDR1_JDATA

#define ADC_JDR2_JDATA

#define ADC_JDR3_JDATA

#define ADC_JDR4_JDATA

#define ADC_DR_DATA

#define ADC_SMPR3_SMP30

#define ADC_SMPR3_SMP30_0

#define ADC_SMPR3_SMP30_1

#define ADC_SMPR3_SMP30_2

#define ADC_SMPR3_SMP31

#define ADC_SMPR3_SMP31_0

#define ADC_SMPR3_SMP31_1

#define ADC_SMPR3_SMP31_2

#define ADC_CSR_AWD1

#define ADC_CSR_EOC1

#define ADC_CSR_JEOC1

#define ADC_CSR_JSTRT1

#define ADC_CSR_STRT1

#define ADC_CSR_OVR1

#define ADC_CSR_ADONS1

#define ADC_CCR_ADCPRE

#define ADC_CCR_ADCPRE_0

#define ADC_CCR_ADCPRE_1

#define ADC_CCR_TSVREFE

#define AES_CR_EN

#define AES_CR_DATATYPE

#define AES_CR_DATATYPE_0

#define AES_CR_DATATYPE_1

#define AES_CR_MODE

#define AES_CR_MODE_0

#define AES_CR_MODE_1

#define AES_CR_CHMOD

#define AES_CR_CHMOD_0

#define AES_CR_CHMOD_1

#define AES_CR_CCFC

#define AES_CR_ERRC

#define AES_CR_CCIE

#define AES_CR_ERRIE

#define AES_CR_DMAINEN

#define AES_CR_DMAOUTEN

#define AES_SR_CCF

#define AES_SR_RDERR

#define AES_SR_WRERR

#define AES_DINR

#define AES_DOUTR

#define AES_KEYR0

#define AES_KEYR1

#define AES_KEYR2

#define AES_KEYR3

#define AES_IVR0

#define AES_IVR1

#define AES_IVR2

#define AES_IVR3

#define COMP_CSR_10KPU

#define COMP_CSR_400KPU

#define COMP_CSR_10KPD

#define COMP_CSR_400KPD

#define COMP_CSR_CMP1EN

#define COMP_CSR_SW1

#define COMP_CSR_CMP1OUT

#define COMP_CSR_SPEED

#define COMP_CSR_CMP2OUT

#define COMP_CSR_VREFOUTEN

#define COMP_CSR_WNDWE

#define COMP_CSR_INSEL

#define COMP_CSR_INSEL_0

#define COMP_CSR_INSEL_1

#define COMP_CSR_INSEL_2

#define COMP_CSR_OUTSEL

#define COMP_CSR_OUTSEL_0

#define COMP_CSR_OUTSEL_1

#define COMP_CSR_OUTSEL_2

#define COMP_CSR_FCH3

#define COMP_CSR_FCH8

#define COMP_CSR_RCH13

#define COMP_CSR_CAIE

#define COMP_CSR_CAIF

#define COMP_CSR_TSUSP

#define OPAMP_CSR_OPA1PD

#define OPAMP_CSR_S3SEL1

#define OPAMP_CSR_S4SEL1

#define OPAMP_CSR_S5SEL1

#define OPAMP_CSR_S6SEL1

#define OPAMP_CSR_OPA1CAL_L

#define OPAMP_CSR_OPA1CAL_H

#define OPAMP_CSR_OPA1LPM

#define OPAMP_CSR_OPA2PD

#define OPAMP_CSR_S3SEL2

#define OPAMP_CSR_S4SEL2

#define OPAMP_CSR_S5SEL2

#define OPAMP_CSR_S6SEL2

#define OPAMP_CSR_OPA2CAL_L

#define OPAMP_CSR_OPA2CAL_H

#define OPAMP_CSR_OPA2LPM

#define OPAMP_CSR_OPA3PD

#define OPAMP_CSR_S3SEL3

#define OPAMP_CSR_S4SEL3

#define OPAMP_CSR_S5SEL3

#define OPAMP_CSR_S6SEL3

#define OPAMP_CSR_OPA3CAL_L

#define OPAMP_CSR_OPA3CAL_H

#define OPAMP_CSR_OPA3LPM

#define OPAMP_CSR_ANAWSEL1

#define OPAMP_CSR_ANAWSEL2

#define OPAMP_CSR_ANAWSEL3

#define OPAMP_CSR_S7SEL2

#define OPAMP_CSR_AOP_RANGE

#define OPAMP_CSR_OPA1CALOUT

#define OPAMP_CSR_OPA2CALOUT

#define OPAMP_CSR_OPA3CALOUT

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM

#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM

#define OPAMP_OTR_OT_USER

#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP

#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP

#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP

#define CRC_DR_DR

#define CRC_IDR_IDR

#define CRC_CR_RESET

#define DAC_CR_EN1

#define DAC_CR_BOFF1

#define DAC_CR_TEN1

#define DAC_CR_TSEL1

#define DAC_CR_TSEL1_0

#define DAC_CR_TSEL1_1

#define DAC_CR_TSEL1_2

#define DAC_CR_WAVE1

#define DAC_CR_WAVE1_0

#define DAC_CR_WAVE1_1

#define DAC_CR_MAMP1

#define DAC_CR_MAMP1_0

#define DAC_CR_MAMP1_1

#define DAC_CR_MAMP1_2

#define DAC_CR_MAMP1_3

#define DAC_CR_DMAEN1

#define DAC_CR_DMAUDRIE1

#define DAC_CR_EN2

#define DAC_CR_BOFF2

#define DAC_CR_TEN2

#define DAC_CR_TSEL2

#define DAC_CR_TSEL2_0

#define DAC_CR_TSEL2_1

#define DAC_CR_TSEL2_2

#define DAC_CR_WAVE2

#define DAC_CR_WAVE2_0

#define DAC_CR_WAVE2_1

#define DAC_CR_MAMP2

#define DAC_CR_MAMP2_0

#define DAC_CR_MAMP2_1

#define DAC_CR_MAMP2_2

#define DAC_CR_MAMP2_3

#define DAC_CR_DMAEN2

#define DAC_CR_DMAUDRIE2

#define DAC_SWTRIGR_SWTRIG1

#define DAC_SWTRIGR_SWTRIG2

#define DAC_DHR12R1_DACC1DHR

#define DAC_DHR12L1_DACC1DHR

#define DAC_DHR8R1_DACC1DHR

#define DAC_DHR12R2_DACC2DHR

#define DAC_DHR12L2_DACC2DHR

#define DAC_DHR8R2_DACC2DHR

#define DAC_DHR12RD_DACC1DHR

#define DAC_DHR12RD_DACC2DHR

#define DAC_DHR12LD_DACC1DHR

#define DAC_DHR12LD_DACC2DHR

#define DAC_DHR8RD_DACC1DHR

#define DAC_DHR8RD_DACC2DHR

#define DAC_DOR1_DACC1DOR

#define DAC_DOR2_DACC2DOR

#define DAC_SR_DMAUDR1

#define DAC_SR_DMAUDR2

#define DBGMCU_IDCODE_DEV_ID

#define DBGMCU_IDCODE_REV_ID

#define DBGMCU_IDCODE_REV_ID_0

#define DBGMCU_IDCODE_REV_ID_1

#define DBGMCU_IDCODE_REV_ID_2

#define DBGMCU_IDCODE_REV_ID_3

#define DBGMCU_IDCODE_REV_ID_4

#define DBGMCU_IDCODE_REV_ID_5

#define DBGMCU_IDCODE_REV_ID_6

#define DBGMCU_IDCODE_REV_ID_7

#define DBGMCU_IDCODE_REV_ID_8

#define DBGMCU_IDCODE_REV_ID_9

#define DBGMCU_IDCODE_REV_ID_10

#define DBGMCU_IDCODE_REV_ID_11

#define DBGMCU_IDCODE_REV_ID_12

#define DBGMCU_IDCODE_REV_ID_13

#define DBGMCU_IDCODE_REV_ID_14

#define DBGMCU_IDCODE_REV_ID_15

#define DBGMCU_CR_DBG_SLEEP

#define DBGMCU_CR_DBG_STOP

#define DBGMCU_CR_DBG_STANDBY

#define DBGMCU_CR_TRACE_IOEN

#define DBGMCU_CR_TRACE_MODE

#define DBGMCU_CR_TRACE_MODE_0

#define DBGMCU_CR_TRACE_MODE_1

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP

#define DBGMCU_APB1_FZ_DBG_RTC_STOP

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP

#define DMA_ISR_GIF1

#define DMA_ISR_TCIF1

#define DMA_ISR_HTIF1

#define DMA_ISR_TEIF1

#define DMA_ISR_GIF2

#define DMA_ISR_TCIF2

#define DMA_ISR_HTIF2

#define DMA_ISR_TEIF2

#define DMA_ISR_GIF3

#define DMA_ISR_TCIF3

#define DMA_ISR_HTIF3

#define DMA_ISR_TEIF3

#define DMA_ISR_GIF4

#define DMA_ISR_TCIF4

#define DMA_ISR_HTIF4

#define DMA_ISR_TEIF4

#define DMA_ISR_GIF5

#define DMA_ISR_TCIF5

#define DMA_ISR_HTIF5

#define DMA_ISR_TEIF5

#define DMA_ISR_GIF6

#define DMA_ISR_TCIF6

#define DMA_ISR_HTIF6

#define DMA_ISR_TEIF6

#define DMA_ISR_GIF7

#define DMA_ISR_TCIF7

#define DMA_ISR_HTIF7

#define DMA_ISR_TEIF7

#define DMA_IFCR_CGIF1

#define DMA_IFCR_CTCIF1

#define DMA_IFCR_CHTIF1

#define DMA_IFCR_CTEIF1

#define DMA_IFCR_CGIF2

#define DMA_IFCR_CTCIF2

#define DMA_IFCR_CHTIF2

#define DMA_IFCR_CTEIF2

#define DMA_IFCR_CGIF3

#define DMA_IFCR_CTCIF3

#define DMA_IFCR_CHTIF3

#define DMA_IFCR_CTEIF3

#define DMA_IFCR_CGIF4

#define DMA_IFCR_CTCIF4

#define DMA_IFCR_CHTIF4

#define DMA_IFCR_CTEIF4

#define DMA_IFCR_CGIF5

#define DMA_IFCR_CTCIF5

#define DMA_IFCR_CHTIF5

#define DMA_IFCR_CTEIF5

#define DMA_IFCR_CGIF6

#define DMA_IFCR_CTCIF6

#define DMA_IFCR_CHTIF6

#define DMA_IFCR_CTEIF6

#define DMA_IFCR_CGIF7

#define DMA_IFCR_CTCIF7

#define DMA_IFCR_CHTIF7

#define DMA_IFCR_CTEIF7

#define DMA_CCR1_EN

#define DMA_CCR1_TCIE

#define DMA_CCR1_HTIE

#define DMA_CCR1_TEIE

#define DMA_CCR1_DIR

#define DMA_CCR1_CIRC

#define DMA_CCR1_PINC

#define DMA_CCR1_MINC

#define DMA_CCR1_PSIZE

#define DMA_CCR1_PSIZE_0

#define DMA_CCR1_PSIZE_1

#define DMA_CCR1_MSIZE

#define DMA_CCR1_MSIZE_0

#define DMA_CCR1_MSIZE_1

#define DMA_CCR1_PL

#define DMA_CCR1_PL_0

#define DMA_CCR1_PL_1

#define DMA_CCR1_MEM2MEM

#define DMA_CCR2_EN

#define DMA_CCR2_TCIE

#define DMA_CCR2_HTIE

#define DMA_CCR2_TEIE

#define DMA_CCR2_DIR

#define DMA_CCR2_CIRC

#define DMA_CCR2_PINC

#define DMA_CCR2_MINC

#define DMA_CCR2_PSIZE

#define DMA_CCR2_PSIZE_0

#define DMA_CCR2_PSIZE_1

#define DMA_CCR2_MSIZE

#define DMA_CCR2_MSIZE_0

#define DMA_CCR2_MSIZE_1

#define DMA_CCR2_PL

#define DMA_CCR2_PL_0

#define DMA_CCR2_PL_1

#define DMA_CCR2_MEM2MEM

#define DMA_CCR3_EN

#define DMA_CCR3_TCIE

#define DMA_CCR3_HTIE

#define DMA_CCR3_TEIE

#define DMA_CCR3_DIR

#define DMA_CCR3_CIRC

#define DMA_CCR3_PINC

#define DMA_CCR3_MINC

#define DMA_CCR3_PSIZE

#define DMA_CCR3_PSIZE_0

#define DMA_CCR3_PSIZE_1

#define DMA_CCR3_MSIZE

#define DMA_CCR3_MSIZE_0

#define DMA_CCR3_MSIZE_1

#define DMA_CCR3_PL

#define DMA_CCR3_PL_0

#define DMA_CCR3_PL_1

#define DMA_CCR3_MEM2MEM

#define DMA_CCR4_EN

#define DMA_CCR4_TCIE

#define DMA_CCR4_HTIE

#define DMA_CCR4_TEIE

#define DMA_CCR4_DIR

#define DMA_CCR4_CIRC

#define DMA_CCR4_PINC

#define DMA_CCR4_MINC

#define DMA_CCR4_PSIZE

#define DMA_CCR4_PSIZE_0

#define DMA_CCR4_PSIZE_1

#define DMA_CCR4_MSIZE

#define DMA_CCR4_MSIZE_0

#define DMA_CCR4_MSIZE_1

#define DMA_CCR4_PL

#define DMA_CCR4_PL_0

#define DMA_CCR4_PL_1

#define DMA_CCR4_MEM2MEM

#define DMA_CCR5_EN

#define DMA_CCR5_TCIE

#define DMA_CCR5_HTIE

#define DMA_CCR5_TEIE

#define DMA_CCR5_DIR

#define DMA_CCR5_CIRC

#define DMA_CCR5_PINC

#define DMA_CCR5_MINC

#define DMA_CCR5_PSIZE

#define DMA_CCR5_PSIZE_0

#define DMA_CCR5_PSIZE_1

#define DMA_CCR5_MSIZE

#define DMA_CCR5_MSIZE_0

#define DMA_CCR5_MSIZE_1

#define DMA_CCR5_PL

#define DMA_CCR5_PL_0

#define DMA_CCR5_PL_1

#define DMA_CCR5_MEM2MEM

#define DMA_CCR6_EN

#define DMA_CCR6_TCIE

#define DMA_CCR6_HTIE

#define DMA_CCR6_TEIE

#define DMA_CCR6_DIR

#define DMA_CCR6_CIRC

#define DMA_CCR6_PINC

#define DMA_CCR6_MINC

#define DMA_CCR6_PSIZE

#define DMA_CCR6_PSIZE_0

#define DMA_CCR6_PSIZE_1

#define DMA_CCR6_MSIZE

#define DMA_CCR6_MSIZE_0

#define DMA_CCR6_MSIZE_1

#define DMA_CCR6_PL

#define DMA_CCR6_PL_0

#define DMA_CCR6_PL_1

#define DMA_CCR6_MEM2MEM

#define DMA_CCR7_EN

#define DMA_CCR7_TCIE

#define DMA_CCR7_HTIE

#define DMA_CCR7_TEIE

#define DMA_CCR7_DIR

#define DMA_CCR7_CIRC

#define DMA_CCR7_PINC

#define DMA_CCR7_MINC

#define DMA_CCR7_PSIZE

#define DMA_CCR7_PSIZE_0

#define DMA_CCR7_PSIZE_1

#define DMA_CCR7_MSIZE

#define DMA_CCR7_MSIZE_0

#define DMA_CCR7_MSIZE_1

#define DMA_CCR7_PL

#define DMA_CCR7_PL_0

#define DMA_CCR7_PL_1

#define DMA_CCR7_MEM2MEM

#define DMA_CNDTR1_NDT

#define DMA_CNDTR2_NDT

#define DMA_CNDTR3_NDT

#define DMA_CNDTR4_NDT

#define DMA_CNDTR5_NDT

#define DMA_CNDTR6_NDT

#define DMA_CNDTR7_NDT

#define DMA_CPAR1_PA

#define DMA_CPAR2_PA

#define DMA_CPAR3_PA

#define DMA_CPAR4_PA

#define DMA_CPAR5_PA

#define DMA_CPAR6_PA

#define DMA_CPAR7_PA

#define DMA_CMAR1_MA

#define DMA_CMAR2_MA

#define DMA_CMAR3_MA

#define DMA_CMAR4_MA

#define DMA_CMAR5_MA

#define DMA_CMAR6_MA

#define DMA_CMAR7_MA

#define EXTI_IMR_MR0

#define EXTI_IMR_MR1

#define EXTI_IMR_MR2

#define EXTI_IMR_MR3

#define EXTI_IMR_MR4

#define EXTI_IMR_MR5

#define EXTI_IMR_MR6

#define EXTI_IMR_MR7

#define EXTI_IMR_MR8

#define EXTI_IMR_MR9

#define EXTI_IMR_MR10

#define EXTI_IMR_MR11

#define EXTI_IMR_MR12

#define EXTI_IMR_MR13

#define EXTI_IMR_MR14

#define EXTI_IMR_MR15

#define EXTI_IMR_MR16

#define EXTI_IMR_MR17

#define EXTI_IMR_MR18

#define EXTI_IMR_MR19

#define EXTI_IMR_MR20

#define EXTI_IMR_MR21

#define EXTI_IMR_MR22

#define EXTI_IMR_MR23

#define EXTI_EMR_MR0

#define EXTI_EMR_MR1

#define EXTI_EMR_MR2

#define EXTI_EMR_MR3

#define EXTI_EMR_MR4

#define EXTI_EMR_MR5

#define EXTI_EMR_MR6

#define EXTI_EMR_MR7

#define EXTI_EMR_MR8

#define EXTI_EMR_MR9

#define EXTI_EMR_MR10

#define EXTI_EMR_MR11

#define EXTI_EMR_MR12

#define EXTI_EMR_MR13

#define EXTI_EMR_MR14

#define EXTI_EMR_MR15

#define EXTI_EMR_MR16

#define EXTI_EMR_MR17

#define EXTI_EMR_MR18

#define EXTI_EMR_MR19

#define EXTI_EMR_MR20

#define EXTI_EMR_MR21

#define EXTI_EMR_MR22

#define EXTI_EMR_MR23

#define EXTI_RTSR_TR0

#define EXTI_RTSR_TR1

#define EXTI_RTSR_TR2

#define EXTI_RTSR_TR3

#define EXTI_RTSR_TR4

#define EXTI_RTSR_TR5

#define EXTI_RTSR_TR6

#define EXTI_RTSR_TR7

#define EXTI_RTSR_TR8

#define EXTI_RTSR_TR9

#define EXTI_RTSR_TR10

#define EXTI_RTSR_TR11

#define EXTI_RTSR_TR12

#define EXTI_RTSR_TR13

#define EXTI_RTSR_TR14

#define EXTI_RTSR_TR15

#define EXTI_RTSR_TR16

#define EXTI_RTSR_TR17

#define EXTI_RTSR_TR18

#define EXTI_RTSR_TR19

#define EXTI_RTSR_TR20

#define EXTI_RTSR_TR21

#define EXTI_RTSR_TR22

#define EXTI_RTSR_TR23

#define EXTI_FTSR_TR0

#define EXTI_FTSR_TR1

#define EXTI_FTSR_TR2

#define EXTI_FTSR_TR3

#define EXTI_FTSR_TR4

#define EXTI_FTSR_TR5

#define EXTI_FTSR_TR6

#define EXTI_FTSR_TR7

#define EXTI_FTSR_TR8

#define EXTI_FTSR_TR9

#define EXTI_FTSR_TR10

#define EXTI_FTSR_TR11

#define EXTI_FTSR_TR12

#define EXTI_FTSR_TR13

#define EXTI_FTSR_TR14

#define EXTI_FTSR_TR15

#define EXTI_FTSR_TR16

#define EXTI_FTSR_TR17

#define EXTI_FTSR_TR18

#define EXTI_FTSR_TR19

#define EXTI_FTSR_TR20

#define EXTI_FTSR_TR21

#define EXTI_FTSR_TR22

#define EXTI_FTSR_TR23

#define EXTI_SWIER_SWIER0

#define EXTI_SWIER_SWIER1

#define EXTI_SWIER_SWIER2

#define EXTI_SWIER_SWIER3

#define EXTI_SWIER_SWIER4

#define EXTI_SWIER_SWIER5

#define EXTI_SWIER_SWIER6

#define EXTI_SWIER_SWIER7

#define EXTI_SWIER_SWIER8

#define EXTI_SWIER_SWIER9

#define EXTI_SWIER_SWIER10

#define EXTI_SWIER_SWIER11

#define EXTI_SWIER_SWIER12

#define EXTI_SWIER_SWIER13

#define EXTI_SWIER_SWIER14

#define EXTI_SWIER_SWIER15

#define EXTI_SWIER_SWIER16

#define EXTI_SWIER_SWIER17

#define EXTI_SWIER_SWIER18

#define EXTI_SWIER_SWIER19

#define EXTI_SWIER_SWIER20

#define EXTI_SWIER_SWIER21

#define EXTI_SWIER_SWIER22

#define EXTI_SWIER_SWIER23

#define EXTI_PR_PR0

#define EXTI_PR_PR1

#define EXTI_PR_PR2

#define EXTI_PR_PR3

#define EXTI_PR_PR4

#define EXTI_PR_PR5

#define EXTI_PR_PR6

#define EXTI_PR_PR7

#define EXTI_PR_PR8

#define EXTI_PR_PR9

#define EXTI_PR_PR10

#define EXTI_PR_PR11

#define EXTI_PR_PR12

#define EXTI_PR_PR13

#define EXTI_PR_PR14

#define EXTI_PR_PR15

#define EXTI_PR_PR16

#define EXTI_PR_PR17

#define EXTI_PR_PR18

#define EXTI_PR_PR19

#define EXTI_PR_PR20

#define EXTI_PR_PR21

#define EXTI_PR_PR22

#define EXTI_PR_PR23

#define FLASH_ACR_LATENCY

#define FLASH_ACR_PRFTEN

#define FLASH_ACR_ACC64

#define FLASH_ACR_SLEEP_PD

#define FLASH_ACR_RUN_PD

#define FLASH_PECR_PELOCK

#define FLASH_PECR_PRGLOCK

#define FLASH_PECR_OPTLOCK

#define FLASH_PECR_PROG

#define FLASH_PECR_DATA

#define FLASH_PECR_FTDW

#define FLASH_PECR_ERASE

#define FLASH_PECR_FPRG

#define FLASH_PECR_PARALLBANK

#define FLASH_PECR_EOPIE

#define FLASH_PECR_ERRIE

#define FLASH_PECR_OBL_LAUNCH

#define FLASH_PDKEYR_PDKEYR

#define FLASH_PEKEYR_PEKEYR

#define FLASH_PRGKEYR_PRGKEYR

#define FLASH_OPTKEYR_OPTKEYR

#define FLASH_SR_BSY

#define FLASH_SR_EOP

#define FLASH_SR_ENHV

#define FLASH_SR_READY

#define FLASH_SR_WRPERR

#define FLASH_SR_PGAERR

#define FLASH_SR_SIZERR

#define FLASH_SR_OPTVERR

#define FLASH_SR_OPTVERRUSR

#define FLASH_OBR_RDPRT

#define FLASH_OBR_BOR_LEV

#define FLASH_OBR_USER

#define FLASH_OBR_IWDG_SW

#define FLASH_OBR_nRST_STOP

#define FLASH_OBR_nRST_STDBY

#define FLASH_OBR_nRST_BFB2

#define FLASH_WRPR_WRP

#define FLASH_WRPR1_WRP

#define FLASH_WRPR2_WRP

#define FSMC_BCR1_MBKEN

#define FSMC_BCR1_MUXEN

#define FSMC_BCR1_MTYP

#define FSMC_BCR1_MTYP_0

#define FSMC_BCR1_MTYP_1

#define FSMC_BCR1_MWID

#define FSMC_BCR1_MWID_0

#define FSMC_BCR1_MWID_1

#define FSMC_BCR1_FACCEN

#define FSMC_BCR1_BURSTEN

#define FSMC_BCR1_WAITPOL

#define FSMC_BCR1_WRAPMOD

#define FSMC_BCR1_WAITCFG

#define FSMC_BCR1_WREN

#define FSMC_BCR1_WAITEN

#define FSMC_BCR1_EXTMOD

#define FSMC_BCR1_ASYNCWAIT

#define FSMC_BCR1_CBURSTRW

#define FSMC_BCR2_MBKEN

#define FSMC_BCR2_MUXEN

#define FSMC_BCR2_MTYP

#define FSMC_BCR2_MTYP_0

#define FSMC_BCR2_MTYP_1

#define FSMC_BCR2_MWID

#define FSMC_BCR2_MWID_0

#define FSMC_BCR2_MWID_1

#define FSMC_BCR2_FACCEN

#define FSMC_BCR2_BURSTEN

#define FSMC_BCR2_WAITPOL

#define FSMC_BCR2_WRAPMOD

#define FSMC_BCR2_WAITCFG

#define FSMC_BCR2_WREN

#define FSMC_BCR2_WAITEN

#define FSMC_BCR2_EXTMOD

#define FSMC_BCR2_ASYNCWAIT

#define FSMC_BCR2_CBURSTRW

#define FSMC_BCR3_MBKEN

#define FSMC_BCR3_MUXEN

#define FSMC_BCR3_MTYP

#define FSMC_BCR3_MTYP_0

#define FSMC_BCR3_MTYP_1

#define FSMC_BCR3_MWID

#define FSMC_BCR3_MWID_0

#define FSMC_BCR3_MWID_1

#define FSMC_BCR3_FACCEN

#define FSMC_BCR3_BURSTEN

#define FSMC_BCR3_WAITPOL

#define FSMC_BCR3_WRAPMOD

#define FSMC_BCR3_WAITCFG

#define FSMC_BCR3_WREN

#define FSMC_BCR3_WAITEN

#define FSMC_BCR3_EXTMOD

#define FSMC_BCR3_ASYNCWAIT

#define FSMC_BCR3_CBURSTRW

#define FSMC_BCR4_MBKEN

#define FSMC_BCR4_MUXEN

#define FSMC_BCR4_MTYP

#define FSMC_BCR4_MTYP_0

#define FSMC_BCR4_MTYP_1

#define FSMC_BCR4_MWID

#define FSMC_BCR4_MWID_0

#define FSMC_BCR4_MWID_1

#define FSMC_BCR4_FACCEN

#define FSMC_BCR4_BURSTEN

#define FSMC_BCR4_WAITPOL

#define FSMC_BCR4_WRAPMOD

#define FSMC_BCR4_WAITCFG

#define FSMC_BCR4_WREN

#define FSMC_BCR4_WAITEN

#define FSMC_BCR4_EXTMOD

#define FSMC_BCR4_ASYNCWAIT

#define FSMC_BCR4_CBURSTRW

#define FSMC_BTR1_ADDSET

#define FSMC_BTR1_ADDSET_0

#define FSMC_BTR1_ADDSET_1

#define FSMC_BTR1_ADDSET_2

#define FSMC_BTR1_ADDSET_3

#define FSMC_BTR1_ADDHLD

#define FSMC_BTR1_ADDHLD_0

#define FSMC_BTR1_ADDHLD_1

#define FSMC_BTR1_ADDHLD_2

#define FSMC_BTR1_ADDHLD_3

#define FSMC_BTR1_DATAST

#define FSMC_BTR1_DATAST_0

#define FSMC_BTR1_DATAST_1

#define FSMC_BTR1_DATAST_2

#define FSMC_BTR1_DATAST_3

#define FSMC_BTR1_BUSTURN

#define FSMC_BTR1_BUSTURN_0

#define FSMC_BTR1_BUSTURN_1

#define FSMC_BTR1_BUSTURN_2

#define FSMC_BTR1_BUSTURN_3

#define FSMC_BTR1_CLKDIV

#define FSMC_BTR1_CLKDIV_0

#define FSMC_BTR1_CLKDIV_1

#define FSMC_BTR1_CLKDIV_2

#define FSMC_BTR1_CLKDIV_3

#define FSMC_BTR1_DATLAT

#define FSMC_BTR1_DATLAT_0

#define FSMC_BTR1_DATLAT_1

#define FSMC_BTR1_DATLAT_2

#define FSMC_BTR1_DATLAT_3

#define FSMC_BTR1_ACCMOD

#define FSMC_BTR1_ACCMOD_0

#define FSMC_BTR1_ACCMOD_1

#define FSMC_BTR2_ADDSET

#define FSMC_BTR2_ADDSET_0

#define FSMC_BTR2_ADDSET_1

#define FSMC_BTR2_ADDSET_2

#define FSMC_BTR2_ADDSET_3

#define FSMC_BTR2_ADDHLD

#define FSMC_BTR2_ADDHLD_0

#define FSMC_BTR2_ADDHLD_1

#define FSMC_BTR2_ADDHLD_2

#define FSMC_BTR2_ADDHLD_3

#define FSMC_BTR2_DATAST

#define FSMC_BTR2_DATAST_0

#define FSMC_BTR2_DATAST_1

#define FSMC_BTR2_DATAST_2

#define FSMC_BTR2_DATAST_3

#define FSMC_BTR2_BUSTURN

#define FSMC_BTR2_BUSTURN_0

#define FSMC_BTR2_BUSTURN_1

#define FSMC_BTR2_BUSTURN_2

#define FSMC_BTR2_BUSTURN_3

#define FSMC_BTR2_CLKDIV

#define FSMC_BTR2_CLKDIV_0

#define FSMC_BTR2_CLKDIV_1

#define FSMC_BTR2_CLKDIV_2

#define FSMC_BTR2_CLKDIV_3

#define FSMC_BTR2_DATLAT

#define FSMC_BTR2_DATLAT_0

#define FSMC_BTR2_DATLAT_1

#define FSMC_BTR2_DATLAT_2

#define FSMC_BTR2_DATLAT_3

#define FSMC_BTR2_ACCMOD

#define FSMC_BTR2_ACCMOD_0

#define FSMC_BTR2_ACCMOD_1

#define FSMC_BTR3_ADDSET

#define FSMC_BTR3_ADDSET_0

#define FSMC_BTR3_ADDSET_1

#define FSMC_BTR3_ADDSET_2

#define FSMC_BTR3_ADDSET_3

#define FSMC_BTR3_ADDHLD

#define FSMC_BTR3_ADDHLD_0

#define FSMC_BTR3_ADDHLD_1

#define FSMC_BTR3_ADDHLD_2

#define FSMC_BTR3_ADDHLD_3

#define FSMC_BTR3_DATAST

#define FSMC_BTR3_DATAST_0

#define FSMC_BTR3_DATAST_1

#define FSMC_BTR3_DATAST_2

#define FSMC_BTR3_DATAST_3

#define FSMC_BTR3_BUSTURN

#define FSMC_BTR3_BUSTURN_0

#define FSMC_BTR3_BUSTURN_1

#define FSMC_BTR3_BUSTURN_2

#define FSMC_BTR3_BUSTURN_3

#define FSMC_BTR3_CLKDIV

#define FSMC_BTR3_CLKDIV_0

#define FSMC_BTR3_CLKDIV_1

#define FSMC_BTR3_CLKDIV_2

#define FSMC_BTR3_CLKDIV_3

#define FSMC_BTR3_DATLAT

#define FSMC_BTR3_DATLAT_0

#define FSMC_BTR3_DATLAT_1

#define FSMC_BTR3_DATLAT_2

#define FSMC_BTR3_DATLAT_3

#define FSMC_BTR3_ACCMOD

#define FSMC_BTR3_ACCMOD_0

#define FSMC_BTR3_ACCMOD_1

#define FSMC_BTR4_ADDSET

#define FSMC_BTR4_ADDSET_0

#define FSMC_BTR4_ADDSET_1

#define FSMC_BTR4_ADDSET_2

#define FSMC_BTR4_ADDSET_3

#define FSMC_BTR4_ADDHLD

#define FSMC_BTR4_ADDHLD_0

#define FSMC_BTR4_ADDHLD_1

#define FSMC_BTR4_ADDHLD_2

#define FSMC_BTR4_ADDHLD_3

#define FSMC_BTR4_DATAST

#define FSMC_BTR4_DATAST_0

#define FSMC_BTR4_DATAST_1

#define FSMC_BTR4_DATAST_2

#define FSMC_BTR4_DATAST_3

#define FSMC_BTR4_BUSTURN

#define FSMC_BTR4_BUSTURN_0

#define FSMC_BTR4_BUSTURN_1

#define FSMC_BTR4_BUSTURN_2

#define FSMC_BTR4_BUSTURN_3

#define FSMC_BTR4_CLKDIV

#define FSMC_BTR4_CLKDIV_0

#define FSMC_BTR4_CLKDIV_1

#define FSMC_BTR4_CLKDIV_2

#define FSMC_BTR4_CLKDIV_3

#define FSMC_BTR4_DATLAT

#define FSMC_BTR4_DATLAT_0

#define FSMC_BTR4_DATLAT_1

#define FSMC_BTR4_DATLAT_2

#define FSMC_BTR4_DATLAT_3

#define FSMC_BTR4_ACCMOD

#define FSMC_BTR4_ACCMOD_0

#define FSMC_BTR4_ACCMOD_1

#define FSMC_BWTR1_ADDSET

#define FSMC_BWTR1_ADDSET_0

#define FSMC_BWTR1_ADDSET_1

#define FSMC_BWTR1_ADDSET_2

#define FSMC_BWTR1_ADDSET_3

#define FSMC_BWTR1_ADDHLD

#define FSMC_BWTR1_ADDHLD_0

#define FSMC_BWTR1_ADDHLD_1

#define FSMC_BWTR1_ADDHLD_2

#define FSMC_BWTR1_ADDHLD_3

#define FSMC_BWTR1_DATAST

#define FSMC_BWTR1_DATAST_0

#define FSMC_BWTR1_DATAST_1

#define FSMC_BWTR1_DATAST_2

#define FSMC_BWTR1_DATAST_3

#define FSMC_BWTR1_CLKDIV

#define FSMC_BWTR1_CLKDIV_0

#define FSMC_BWTR1_CLKDIV_1

#define FSMC_BWTR1_CLKDIV_2

#define FSMC_BWTR1_CLKDIV_3

#define FSMC_BWTR1_DATLAT

#define FSMC_BWTR1_DATLAT_0

#define FSMC_BWTR1_DATLAT_1

#define FSMC_BWTR1_DATLAT_2

#define FSMC_BWTR1_DATLAT_3

#define FSMC_BWTR1_ACCMOD

#define FSMC_BWTR1_ACCMOD_0

#define FSMC_BWTR1_ACCMOD_1

#define FSMC_BWTR2_ADDSET

#define FSMC_BWTR2_ADDSET_0

#define FSMC_BWTR2_ADDSET_1

#define FSMC_BWTR2_ADDSET_2

#define FSMC_BWTR2_ADDSET_3

#define FSMC_BWTR2_ADDHLD

#define FSMC_BWTR2_ADDHLD_0

#define FSMC_BWTR2_ADDHLD_1

#define FSMC_BWTR2_ADDHLD_2

#define FSMC_BWTR2_ADDHLD_3

#define FSMC_BWTR2_DATAST

#define FSMC_BWTR2_DATAST_0

#define FSMC_BWTR2_DATAST_1

#define FSMC_BWTR2_DATAST_2

#define FSMC_BWTR2_DATAST_3

#define FSMC_BWTR2_CLKDIV

#define FSMC_BWTR2_CLKDIV_0

#define FSMC_BWTR2_CLKDIV_1

#define FSMC_BWTR2_CLKDIV_2

#define FSMC_BWTR2_CLKDIV_3

#define FSMC_BWTR2_DATLAT

#define FSMC_BWTR2_DATLAT_0

#define FSMC_BWTR2_DATLAT_1

#define FSMC_BWTR2_DATLAT_2

#define FSMC_BWTR2_DATLAT_3

#define FSMC_BWTR2_ACCMOD

#define FSMC_BWTR2_ACCMOD_0

#define FSMC_BWTR2_ACCMOD_1

#define FSMC_BWTR3_ADDSET

#define FSMC_BWTR3_ADDSET_0

#define FSMC_BWTR3_ADDSET_1

#define FSMC_BWTR3_ADDSET_2

#define FSMC_BWTR3_ADDSET_3

#define FSMC_BWTR3_ADDHLD

#define FSMC_BWTR3_ADDHLD_0

#define FSMC_BWTR3_ADDHLD_1

#define FSMC_BWTR3_ADDHLD_2

#define FSMC_BWTR3_ADDHLD_3

#define FSMC_BWTR3_DATAST

#define FSMC_BWTR3_DATAST_0

#define FSMC_BWTR3_DATAST_1

#define FSMC_BWTR3_DATAST_2

#define FSMC_BWTR3_DATAST_3

#define FSMC_BWTR3_CLKDIV

#define FSMC_BWTR3_CLKDIV_0

#define FSMC_BWTR3_CLKDIV_1

#define FSMC_BWTR3_CLKDIV_2

#define FSMC_BWTR3_CLKDIV_3

#define FSMC_BWTR3_DATLAT

#define FSMC_BWTR3_DATLAT_0

#define FSMC_BWTR3_DATLAT_1

#define FSMC_BWTR3_DATLAT_2

#define FSMC_BWTR3_DATLAT_3

#define FSMC_BWTR3_ACCMOD

#define FSMC_BWTR3_ACCMOD_0

#define FSMC_BWTR3_ACCMOD_1

#define FSMC_BWTR4_ADDSET

#define FSMC_BWTR4_ADDSET_0

#define FSMC_BWTR4_ADDSET_1

#define FSMC_BWTR4_ADDSET_2

#define FSMC_BWTR4_ADDSET_3

#define FSMC_BWTR4_ADDHLD

#define FSMC_BWTR4_ADDHLD_0

#define FSMC_BWTR4_ADDHLD_1

#define FSMC_BWTR4_ADDHLD_2

#define FSMC_BWTR4_ADDHLD_3

#define FSMC_BWTR4_DATAST

#define FSMC_BWTR4_DATAST_0

#define FSMC_BWTR4_DATAST_1

#define FSMC_BWTR4_DATAST_2

#define FSMC_BWTR4_DATAST_3

#define FSMC_BWTR4_CLKDIV

#define FSMC_BWTR4_CLKDIV_0

#define FSMC_BWTR4_CLKDIV_1

#define FSMC_BWTR4_CLKDIV_2

#define FSMC_BWTR4_CLKDIV_3

#define FSMC_BWTR4_DATLAT

#define FSMC_BWTR4_DATLAT_0

#define FSMC_BWTR4_DATLAT_1

#define FSMC_BWTR4_DATLAT_2

#define FSMC_BWTR4_DATLAT_3

#define FSMC_BWTR4_ACCMOD

#define FSMC_BWTR4_ACCMOD_0

#define FSMC_BWTR4_ACCMOD_1

#define GPIO_MODER_MODER0

#define GPIO_MODER_MODER0_0

#define GPIO_MODER_MODER0_1

#define GPIO_MODER_MODER1

#define GPIO_MODER_MODER1_0

#define GPIO_MODER_MODER1_1

#define GPIO_MODER_MODER2

#define GPIO_MODER_MODER2_0

#define GPIO_MODER_MODER2_1

#define GPIO_MODER_MODER3

#define GPIO_MODER_MODER3_0

#define GPIO_MODER_MODER3_1

#define GPIO_MODER_MODER4

#define GPIO_MODER_MODER4_0

#define GPIO_MODER_MODER4_1

#define GPIO_MODER_MODER5

#define GPIO_MODER_MODER5_0

#define GPIO_MODER_MODER5_1

#define GPIO_MODER_MODER6

#define GPIO_MODER_MODER6_0

#define GPIO_MODER_MODER6_1

#define GPIO_MODER_MODER7

#define GPIO_MODER_MODER7_0

#define GPIO_MODER_MODER7_1

#define GPIO_MODER_MODER8

#define GPIO_MODER_MODER8_0

#define GPIO_MODER_MODER8_1

#define GPIO_MODER_MODER9

#define GPIO_MODER_MODER9_0

#define GPIO_MODER_MODER9_1

#define GPIO_MODER_MODER10

#define GPIO_MODER_MODER10_0

#define GPIO_MODER_MODER10_1

#define GPIO_MODER_MODER11

#define GPIO_MODER_MODER11_0

#define GPIO_MODER_MODER11_1

#define GPIO_MODER_MODER12

#define GPIO_MODER_MODER12_0

#define GPIO_MODER_MODER12_1

#define GPIO_MODER_MODER13

#define GPIO_MODER_MODER13_0

#define GPIO_MODER_MODER13_1

#define GPIO_MODER_MODER14

#define GPIO_MODER_MODER14_0

#define GPIO_MODER_MODER14_1

#define GPIO_MODER_MODER15

#define GPIO_MODER_MODER15_0

#define GPIO_MODER_MODER15_1

#define GPIO_OTYPER_OT_0

#define GPIO_OTYPER_OT_1

#define GPIO_OTYPER_OT_2

#define GPIO_OTYPER_OT_3

#define GPIO_OTYPER_OT_4

#define GPIO_OTYPER_OT_5

#define GPIO_OTYPER_OT_6

#define GPIO_OTYPER_OT_7

#define GPIO_OTYPER_OT_8

#define GPIO_OTYPER_OT_9

#define GPIO_OTYPER_OT_10

#define GPIO_OTYPER_OT_11

#define GPIO_OTYPER_OT_12

#define GPIO_OTYPER_OT_13

#define GPIO_OTYPER_OT_14

#define GPIO_OTYPER_OT_15

#define GPIO_OSPEEDER_OSPEEDR0

#define GPIO_OSPEEDER_OSPEEDR0_0

#define GPIO_OSPEEDER_OSPEEDR0_1

#define GPIO_OSPEEDER_OSPEEDR1

#define GPIO_OSPEEDER_OSPEEDR1_0

#define GPIO_OSPEEDER_OSPEEDR1_1

#define GPIO_OSPEEDER_OSPEEDR2

#define GPIO_OSPEEDER_OSPEEDR2_0

#define GPIO_OSPEEDER_OSPEEDR2_1

#define GPIO_OSPEEDER_OSPEEDR3

#define GPIO_OSPEEDER_OSPEEDR3_0

#define GPIO_OSPEEDER_OSPEEDR3_1

#define GPIO_OSPEEDER_OSPEEDR4

#define GPIO_OSPEEDER_OSPEEDR4_0

#define GPIO_OSPEEDER_OSPEEDR4_1

#define GPIO_OSPEEDER_OSPEEDR5

#define GPIO_OSPEEDER_OSPEEDR5_0

#define GPIO_OSPEEDER_OSPEEDR5_1

#define GPIO_OSPEEDER_OSPEEDR6

#define GPIO_OSPEEDER_OSPEEDR6_0

#define GPIO_OSPEEDER_OSPEEDR6_1

#define GPIO_OSPEEDER_OSPEEDR7

#define GPIO_OSPEEDER_OSPEEDR7_0

#define GPIO_OSPEEDER_OSPEEDR7_1

#define GPIO_OSPEEDER_OSPEEDR8

#define GPIO_OSPEEDER_OSPEEDR8_0

#define GPIO_OSPEEDER_OSPEEDR8_1

#define GPIO_OSPEEDER_OSPEEDR9

#define GPIO_OSPEEDER_OSPEEDR9_0

#define GPIO_OSPEEDER_OSPEEDR9_1

#define GPIO_OSPEEDER_OSPEEDR10

#define GPIO_OSPEEDER_OSPEEDR10_0

#define GPIO_OSPEEDER_OSPEEDR10_1

#define GPIO_OSPEEDER_OSPEEDR11

#define GPIO_OSPEEDER_OSPEEDR11_0

#define GPIO_OSPEEDER_OSPEEDR11_1

#define GPIO_OSPEEDER_OSPEEDR12

#define GPIO_OSPEEDER_OSPEEDR12_0

#define GPIO_OSPEEDER_OSPEEDR12_1

#define GPIO_OSPEEDER_OSPEEDR13

#define GPIO_OSPEEDER_OSPEEDR13_0

#define GPIO_OSPEEDER_OSPEEDR13_1

#define GPIO_OSPEEDER_OSPEEDR14

#define GPIO_OSPEEDER_OSPEEDR14_0

#define GPIO_OSPEEDER_OSPEEDR14_1

#define GPIO_OSPEEDER_OSPEEDR15

#define GPIO_OSPEEDER_OSPEEDR15_0

#define GPIO_OSPEEDER_OSPEEDR15_1

#define GPIO_PUPDR_PUPDR0

#define GPIO_PUPDR_PUPDR0_0

#define GPIO_PUPDR_PUPDR0_1

#define GPIO_PUPDR_PUPDR1

#define GPIO_PUPDR_PUPDR1_0

#define GPIO_PUPDR_PUPDR1_1

#define GPIO_PUPDR_PUPDR2

#define GPIO_PUPDR_PUPDR2_0

#define GPIO_PUPDR_PUPDR2_1

#define GPIO_PUPDR_PUPDR3

#define GPIO_PUPDR_PUPDR3_0

#define GPIO_PUPDR_PUPDR3_1

#define GPIO_PUPDR_PUPDR4

#define GPIO_PUPDR_PUPDR4_0

#define GPIO_PUPDR_PUPDR4_1

#define GPIO_PUPDR_PUPDR5

#define GPIO_PUPDR_PUPDR5_0

#define GPIO_PUPDR_PUPDR5_1

#define GPIO_PUPDR_PUPDR6

#define GPIO_PUPDR_PUPDR6_0

#define GPIO_PUPDR_PUPDR6_1

#define GPIO_PUPDR_PUPDR7

#define GPIO_PUPDR_PUPDR7_0

#define GPIO_PUPDR_PUPDR7_1

#define GPIO_PUPDR_PUPDR8

#define GPIO_PUPDR_PUPDR8_0

#define GPIO_PUPDR_PUPDR8_1

#define GPIO_PUPDR_PUPDR9

#define GPIO_PUPDR_PUPDR9_0

#define GPIO_PUPDR_PUPDR9_1

#define GPIO_PUPDR_PUPDR10

#define GPIO_PUPDR_PUPDR10_0

#define GPIO_PUPDR_PUPDR10_1

#define GPIO_PUPDR_PUPDR11

#define GPIO_PUPDR_PUPDR11_0

#define GPIO_PUPDR_PUPDR11_1

#define GPIO_PUPDR_PUPDR12

#define GPIO_PUPDR_PUPDR12_0

#define GPIO_PUPDR_PUPDR12_1

#define GPIO_PUPDR_PUPDR13

#define GPIO_PUPDR_PUPDR13_0

#define GPIO_PUPDR_PUPDR13_1

#define GPIO_PUPDR_PUPDR14

#define GPIO_PUPDR_PUPDR14_0

#define GPIO_PUPDR_PUPDR14_1

#define GPIO_PUPDR_PUPDR15

#define GPIO_PUPDR_PUPDR15_0

#define GPIO_PUPDR_PUPDR15_1

#define GPIO_IDR_IDR_0

#define GPIO_IDR_IDR_1

#define GPIO_IDR_IDR_2

#define GPIO_IDR_IDR_3

#define GPIO_IDR_IDR_4

#define GPIO_IDR_IDR_5

#define GPIO_IDR_IDR_6

#define GPIO_IDR_IDR_7

#define GPIO_IDR_IDR_8

#define GPIO_IDR_IDR_9

#define GPIO_IDR_IDR_10

#define GPIO_IDR_IDR_11

#define GPIO_IDR_IDR_12

#define GPIO_IDR_IDR_13

#define GPIO_IDR_IDR_14

#define GPIO_IDR_IDR_15

#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0

#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1

#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2

#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3

#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4

#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5

#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6

#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7

#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8

#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9

#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10

#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11

#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12

#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13

#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14

#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15

#define GPIO_ODR_ODR_0

#define GPIO_ODR_ODR_1

#define GPIO_ODR_ODR_2

#define GPIO_ODR_ODR_3

#define GPIO_ODR_ODR_4

#define GPIO_ODR_ODR_5

#define GPIO_ODR_ODR_6

#define GPIO_ODR_ODR_7

#define GPIO_ODR_ODR_8

#define GPIO_ODR_ODR_9

#define GPIO_ODR_ODR_10

#define GPIO_ODR_ODR_11

#define GPIO_ODR_ODR_12

#define GPIO_ODR_ODR_13

#define GPIO_ODR_ODR_14

#define GPIO_ODR_ODR_15

#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0

#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1

#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2

#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3

#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4

#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5

#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6

#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7

#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8

#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9

#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10

#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11

#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12

#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13

#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14

#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15

#define GPIO_BSRR_BS_0

#define GPIO_BSRR_BS_1

#define GPIO_BSRR_BS_2

#define GPIO_BSRR_BS_3

#define GPIO_BSRR_BS_4

#define GPIO_BSRR_BS_5

#define GPIO_BSRR_BS_6

#define GPIO_BSRR_BS_7

#define GPIO_BSRR_BS_8

#define GPIO_BSRR_BS_9

#define GPIO_BSRR_BS_10

#define GPIO_BSRR_BS_11

#define GPIO_BSRR_BS_12

#define GPIO_BSRR_BS_13

#define GPIO_BSRR_BS_14

#define GPIO_BSRR_BS_15

#define GPIO_BSRR_BR_0

#define GPIO_BSRR_BR_1

#define GPIO_BSRR_BR_2

#define GPIO_BSRR_BR_3

#define GPIO_BSRR_BR_4

#define GPIO_BSRR_BR_5

#define GPIO_BSRR_BR_6

#define GPIO_BSRR_BR_7

#define GPIO_BSRR_BR_8

#define GPIO_BSRR_BR_9

#define GPIO_BSRR_BR_10

#define GPIO_BSRR_BR_11

#define GPIO_BSRR_BR_12

#define GPIO_BSRR_BR_13

#define GPIO_BSRR_BR_14

#define GPIO_BSRR_BR_15

#define GPIO_LCKR_LCK0

#define GPIO_LCKR_LCK1

#define GPIO_LCKR_LCK2

#define GPIO_LCKR_LCK3

#define GPIO_LCKR_LCK4

#define GPIO_LCKR_LCK5

#define GPIO_LCKR_LCK6

#define GPIO_LCKR_LCK7

#define GPIO_LCKR_LCK8

#define GPIO_LCKR_LCK9

#define GPIO_LCKR_LCK10

#define GPIO_LCKR_LCK11

#define GPIO_LCKR_LCK12

#define GPIO_LCKR_LCK13

#define GPIO_LCKR_LCK14

#define GPIO_LCKR_LCK15

#define GPIO_LCKR_LCKK

#define GPIO_AFRL_AFRL0

#define GPIO_AFRL_AFRL1

#define GPIO_AFRL_AFRL2

#define GPIO_AFRL_AFRL3

#define GPIO_AFRL_AFRL4

#define GPIO_AFRL_AFRL5

#define GPIO_AFRL_AFRL6

#define GPIO_AFRL_AFRL7

#define GPIO_AFRH_AFRH8

#define GPIO_AFRH_AFRH9

#define GPIO_AFRH_AFRH10

#define GPIO_AFRH_AFRH11

#define GPIO_AFRH_AFRH12

#define GPIO_AFRH_AFRH13

#define GPIO_AFRH_AFRH14

#define GPIO_AFRH_AFRH15

#define I2C_CR1_PE

#define I2C_CR1_SMBUS

#define I2C_CR1_SMBTYPE

#define I2C_CR1_ENARP

#define I2C_CR1_ENPEC

#define I2C_CR1_ENGC

#define I2C_CR1_NOSTRETCH

#define I2C_CR1_START

#define I2C_CR1_STOP

#define I2C_CR1_ACK

#define I2C_CR1_POS

#define I2C_CR1_PEC

#define I2C_CR1_ALERT

#define I2C_CR1_SWRST

#define I2C_CR2_FREQ

#define I2C_CR2_FREQ_0

#define I2C_CR2_FREQ_1

#define I2C_CR2_FREQ_2

#define I2C_CR2_FREQ_3

#define I2C_CR2_FREQ_4

#define I2C_CR2_FREQ_5

#define I2C_CR2_ITERREN

#define I2C_CR2_ITEVTEN

#define I2C_CR2_ITBUFEN

#define I2C_CR2_DMAEN

#define I2C_CR2_LAST

#define I2C_OAR1_ADD1_7

#define I2C_OAR1_ADD8_9

#define I2C_OAR1_ADD0

#define I2C_OAR1_ADD1

#define I2C_OAR1_ADD2

#define I2C_OAR1_ADD3

#define I2C_OAR1_ADD4

#define I2C_OAR1_ADD5

#define I2C_OAR1_ADD6

#define I2C_OAR1_ADD7

#define I2C_OAR1_ADD8

#define I2C_OAR1_ADD9

#define I2C_OAR1_ADDMODE

#define I2C_OAR2_ENDUAL

#define I2C_OAR2_ADD2

#define I2C_DR_DR

#define I2C_SR1_SB

#define I2C_SR1_ADDR

#define I2C_SR1_BTF

#define I2C_SR1_ADD10

#define I2C_SR1_STOPF

#define I2C_SR1_RXNE

#define I2C_SR1_TXE

#define I2C_SR1_BERR

#define I2C_SR1_ARLO

#define I2C_SR1_AF

#define I2C_SR1_OVR

#define I2C_SR1_PECERR

#define I2C_SR1_TIMEOUT

#define I2C_SR1_SMBALERT

#define I2C_SR2_MSL

#define I2C_SR2_BUSY

#define I2C_SR2_TRA

#define I2C_SR2_GENCALL

#define I2C_SR2_SMBDEFAULT

#define I2C_SR2_SMBHOST

#define I2C_SR2_DUALF

#define I2C_SR2_PEC

#define I2C_CCR_CCR

#define I2C_CCR_DUTY

#define I2C_CCR_FS

#define I2C_TRISE_TRISE

#define IWDG_KR_KEY

#define IWDG_PR_PR

#define IWDG_PR_PR_0

#define IWDG_PR_PR_1

#define IWDG_PR_PR_2

#define IWDG_RLR_RL

#define IWDG_SR_PVU

#define IWDG_SR_RVU

#define LCD_CR_LCDEN

#define LCD_CR_VSEL

#define LCD_CR_DUTY

#define LCD_CR_DUTY_0

#define LCD_CR_DUTY_1

#define LCD_CR_DUTY_2

#define LCD_CR_BIAS

#define LCD_CR_BIAS_0

#define LCD_CR_BIAS_1

#define LCD_CR_MUX_SEG

#define LCD_FCR_HD

#define LCD_FCR_SOFIE

#define LCD_FCR_UDDIE

#define LCD_FCR_PON

#define LCD_FCR_PON_0

#define LCD_FCR_PON_1

#define LCD_FCR_PON_2

#define LCD_FCR_DEAD

#define LCD_FCR_DEAD_0

#define LCD_FCR_DEAD_1

#define LCD_FCR_DEAD_2

#define LCD_FCR_CC

#define LCD_FCR_CC_0

#define LCD_FCR_CC_1

#define LCD_FCR_CC_2

#define LCD_FCR_BLINKF

#define LCD_FCR_BLINKF_0

#define LCD_FCR_BLINKF_1

#define LCD_FCR_BLINKF_2

#define LCD_FCR_BLINK

#define LCD_FCR_BLINK_0

#define LCD_FCR_BLINK_1

#define LCD_FCR_DIV

#define LCD_FCR_PS

#define LCD_SR_ENS

#define LCD_SR_SOF

#define LCD_SR_UDR

#define LCD_SR_UDD

#define LCD_SR_RDY

#define LCD_SR_FCRSR

#define LCD_CLR_SOFC

#define LCD_CLR_UDDC

#define LCD_RAM_SEGMENT_DATA

#define PWR_CR_LPSDSR

#define PWR_CR_PDDS

#define PWR_CR_CWUF

#define PWR_CR_CSBF

#define PWR_CR_PVDE

#define PWR_CR_PLS

#define PWR_CR_PLS_0

#define PWR_CR_PLS_1

#define PWR_CR_PLS_2

#define PWR_CR_PLS_LEV0

#define PWR_CR_PLS_LEV1

#define PWR_CR_PLS_LEV2

#define PWR_CR_PLS_LEV3

#define PWR_CR_PLS_LEV4

#define PWR_CR_PLS_LEV5

#define PWR_CR_PLS_LEV6

#define PWR_CR_PLS_LEV7

#define PWR_CR_DBP

#define PWR_CR_ULP

#define PWR_CR_FWU

#define PWR_CR_VOS

#define PWR_CR_VOS_0

#define PWR_CR_VOS_1

#define PWR_CR_LPRUN

#define PWR_CSR_WUF

#define PWR_CSR_SBF

#define PWR_CSR_PVDO

#define PWR_CSR_VREFINTRDYF

#define PWR_CSR_VOSF

#define PWR_CSR_REGLPF

#define PWR_CSR_EWUP1

#define PWR_CSR_EWUP2

#define PWR_CSR_EWUP3

#define RCC_CR_HSION

#define RCC_CR_HSIRDY

#define RCC_CR_MSION

#define RCC_CR_MSIRDY

#define RCC_CR_HSEON

#define RCC_CR_HSERDY

#define RCC_CR_HSEBYP

#define RCC_CR_PLLON

#define RCC_CR_PLLRDY

#define RCC_CR_CSSON

#define RCC_CR_RTCPRE

#define RCC_CR_RTCPRE_0

#define RCC_CR_RTCPRE_1

#define RCC_ICSCR_HSICAL

#define RCC_ICSCR_HSITRIM

#define RCC_ICSCR_MSIRANGE

#define RCC_ICSCR_MSIRANGE_0

#define RCC_ICSCR_MSIRANGE_1

#define RCC_ICSCR_MSIRANGE_2

#define RCC_ICSCR_MSIRANGE_3

#define RCC_ICSCR_MSIRANGE_4

#define RCC_ICSCR_MSIRANGE_5

#define RCC_ICSCR_MSIRANGE_6

#define RCC_ICSCR_MSICAL

#define RCC_ICSCR_MSITRIM

#define RCC_CFGR_SW

#define RCC_CFGR_SW_0

#define RCC_CFGR_SW_1

#define RCC_CFGR_SW_MSI

#define RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_PLL

#define RCC_CFGR_SWS

#define RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_MSI

#define RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_PLL

#define RCC_CFGR_HPRE

#define RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV2

#define RCC_CFGR_HPRE_DIV4

#define RCC_CFGR_HPRE_DIV8

#define RCC_CFGR_HPRE_DIV16

#define RCC_CFGR_HPRE_DIV64

#define RCC_CFGR_HPRE_DIV128

#define RCC_CFGR_HPRE_DIV256

#define RCC_CFGR_HPRE_DIV512

#define RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1_0

#define RCC_CFGR_PPRE1_1

#define RCC_CFGR_PPRE1_2

#define RCC_CFGR_PPRE1_DIV1

#define RCC_CFGR_PPRE1_DIV2

#define RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV8

#define RCC_CFGR_PPRE1_DIV16

#define RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2_0

#define RCC_CFGR_PPRE2_1

#define RCC_CFGR_PPRE2_2

#define RCC_CFGR_PPRE2_DIV1

#define RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV4

#define RCC_CFGR_PPRE2_DIV8

#define RCC_CFGR_PPRE2_DIV16

#define RCC_CFGR_PLLSRC

#define RCC_CFGR_PLLSRC_HSI

#define RCC_CFGR_PLLSRC_HSE

#define RCC_CFGR_PLLMUL

#define RCC_CFGR_PLLMUL_0

#define RCC_CFGR_PLLMUL_1

#define RCC_CFGR_PLLMUL_2

#define RCC_CFGR_PLLMUL_3

#define RCC_CFGR_PLLMUL3

#define RCC_CFGR_PLLMUL4

#define RCC_CFGR_PLLMUL6

#define RCC_CFGR_PLLMUL8

#define RCC_CFGR_PLLMUL12

#define RCC_CFGR_PLLMUL16

#define RCC_CFGR_PLLMUL24

#define RCC_CFGR_PLLMUL32

#define RCC_CFGR_PLLMUL48

#define RCC_CFGR_PLLDIV

#define RCC_CFGR_PLLDIV_0

#define RCC_CFGR_PLLDIV_1

#define RCC_CFGR_PLLDIV1

#define RCC_CFGR_PLLDIV2

#define RCC_CFGR_PLLDIV3

#define RCC_CFGR_PLLDIV4

#define RCC_CFGR_MCOSEL

#define RCC_CFGR_MCOSEL_0

#define RCC_CFGR_MCOSEL_1

#define RCC_CFGR_MCOSEL_2

#define RCC_CFGR_MCO_NOCLOCK

#define RCC_CFGR_MCO_SYSCLK

#define RCC_CFGR_MCO_HSI

#define RCC_CFGR_MCO_MSI

#define RCC_CFGR_MCO_HSE

#define RCC_CFGR_MCO_PLL

#define RCC_CFGR_MCO_LSI

#define RCC_CFGR_MCO_LSE

#define RCC_CFGR_MCOPRE

#define RCC_CFGR_MCOPRE_0

#define RCC_CFGR_MCOPRE_1

#define RCC_CFGR_MCOPRE_2

#define RCC_CFGR_MCO_DIV1

#define RCC_CFGR_MCO_DIV2

#define RCC_CFGR_MCO_DIV4

#define RCC_CFGR_MCO_DIV8

#define RCC_CFGR_MCO_DIV16

#define RCC_CIR_LSIRDYF

#define RCC_CIR_LSERDYF

#define RCC_CIR_HSIRDYF

#define RCC_CIR_HSERDYF

#define RCC_CIR_PLLRDYF

#define RCC_CIR_MSIRDYF

#define RCC_CIR_LSECSS

#define RCC_CIR_CSSF

#define RCC_CIR_LSIRDYIE

#define RCC_CIR_LSERDYIE

#define RCC_CIR_HSIRDYIE

#define RCC_CIR_HSERDYIE

#define RCC_CIR_PLLRDYIE

#define RCC_CIR_MSIRDYIE

#define RCC_CIR_LSECSSIE

#define RCC_CIR_LSIRDYC

#define RCC_CIR_LSERDYC

#define RCC_CIR_HSIRDYC

#define RCC_CIR_HSERDYC

#define RCC_CIR_PLLRDYC

#define RCC_CIR_MSIRDYC

#define RCC_CIR_LSECSSC

#define RCC_CIR_CSSC

#define RCC_AHBRSTR_GPIOARST

#define RCC_AHBRSTR_GPIOBRST

#define RCC_AHBRSTR_GPIOCRST

#define RCC_AHBRSTR_GPIODRST

#define RCC_AHBRSTR_GPIOERST

#define RCC_AHBRSTR_GPIOHRST

#define RCC_AHBRSTR_GPIOFRST

#define RCC_AHBRSTR_GPIOGRST

#define RCC_AHBRSTR_CRCRST

#define RCC_AHBRSTR_FLITFRST

#define RCC_AHBRSTR_DMA1RST

#define RCC_AHBRSTR_DMA2RST

#define RCC_AHBRSTR_AESRST

#define RCC_AHBRSTR_FSMCRST

#define RCC_APB2RSTR_SYSCFGRST

#define RCC_APB2RSTR_TIM9RST

#define RCC_APB2RSTR_TIM10RST

#define RCC_APB2RSTR_TIM11RST

#define RCC_APB2RSTR_ADC1RST

#define RCC_APB2RSTR_SDIORST

#define RCC_APB2RSTR_SPI1RST

#define RCC_APB2RSTR_USART1RST

#define RCC_APB1RSTR_TIM2RST

#define RCC_APB1RSTR_TIM3RST

#define RCC_APB1RSTR_TIM4RST

#define RCC_APB1RSTR_TIM5RST

#define RCC_APB1RSTR_TIM6RST

#define RCC_APB1RSTR_TIM7RST

#define RCC_APB1RSTR_LCDRST

#define RCC_APB1RSTR_WWDGRST

#define RCC_APB1RSTR_SPI2RST

#define RCC_APB1RSTR_SPI3RST

#define RCC_APB1RSTR_USART2RST

#define RCC_APB1RSTR_USART3RST

#define RCC_APB1RSTR_UART4RST

#define RCC_APB1RSTR_UART5RST

#define RCC_APB1RSTR_I2C1RST

#define RCC_APB1RSTR_I2C2RST

#define RCC_APB1RSTR_USBRST

#define RCC_APB1RSTR_PWRRST

#define RCC_APB1RSTR_DACRST

#define RCC_APB1RSTR_COMPRST

#define RCC_AHBENR_GPIOAEN

#define RCC_AHBENR_GPIOBEN

#define RCC_AHBENR_GPIOCEN

#define RCC_AHBENR_GPIODEN

#define RCC_AHBENR_GPIOEEN

#define RCC_AHBENR_GPIOHEN

#define RCC_AHBENR_GPIOFEN

#define RCC_AHBENR_GPIOGEN

#define RCC_AHBENR_CRCEN

#define RCC_AHBENR_FLITFEN

#define RCC_AHBENR_DMA1EN

#define RCC_AHBENR_DMA2EN

#define RCC_AHBENR_AESEN

#define RCC_AHBENR_FSMCEN

#define RCC_APB2ENR_SYSCFGEN

#define RCC_APB2ENR_TIM9EN

#define RCC_APB2ENR_TIM10EN

#define RCC_APB2ENR_TIM11EN

#define RCC_APB2ENR_ADC1EN

#define RCC_APB2ENR_SDIOEN

#define RCC_APB2ENR_SPI1EN

#define RCC_APB2ENR_USART1EN

#define RCC_APB1ENR_TIM2EN

#define RCC_APB1ENR_TIM3EN

#define RCC_APB1ENR_TIM4EN

#define RCC_APB1ENR_TIM5EN

#define RCC_APB1ENR_TIM6EN

#define RCC_APB1ENR_TIM7EN

#define RCC_APB1ENR_LCDEN

#define RCC_APB1ENR_WWDGEN

#define RCC_APB1ENR_SPI2EN

#define RCC_APB1ENR_SPI3EN

#define RCC_APB1ENR_USART2EN

#define RCC_APB1ENR_USART3EN

#define RCC_APB1ENR_UART4EN

#define RCC_APB1ENR_UART5EN

#define RCC_APB1ENR_I2C1EN

#define RCC_APB1ENR_I2C2EN

#define RCC_APB1ENR_USBEN

#define RCC_APB1ENR_PWREN

#define RCC_APB1ENR_DACEN

#define RCC_APB1ENR_COMPEN

#define RCC_AHBLPENR_GPIOALPEN

#define RCC_AHBLPENR_GPIOBLPEN

#define RCC_AHBLPENR_GPIOCLPEN

#define RCC_AHBLPENR_GPIODLPEN

#define RCC_AHBLPENR_GPIOELPEN

#define RCC_AHBLPENR_GPIOHLPEN

#define RCC_AHBLPENR_GPIOFLPEN

#define RCC_AHBLPENR_GPIOGLPEN

#define RCC_AHBLPENR_CRCLPEN

#define RCC_AHBLPENR_FLITFLPEN

#define RCC_AHBLPENR_SRAMLPEN

#define RCC_AHBLPENR_DMA1LPEN

#define RCC_AHBLPENR_DMA2LPEN

#define RCC_AHBLPENR_AESLPEN

#define RCC_AHBLPENR_FSMCLPEN

#define RCC_APB2LPENR_SYSCFGLPEN

#define RCC_APB2LPENR_TIM9LPEN

#define RCC_APB2LPENR_TIM10LPEN

#define RCC_APB2LPENR_TIM11LPEN

#define RCC_APB2LPENR_ADC1LPEN

#define RCC_APB2LPENR_SDIOLPEN

#define RCC_APB2LPENR_SPI1LPEN

#define RCC_APB2LPENR_USART1LPEN

#define RCC_APB1LPENR_TIM2LPEN

#define RCC_APB1LPENR_TIM3LPEN

#define RCC_APB1LPENR_TIM4LPEN

#define RCC_APB1LPENR_TIM5LPEN

#define RCC_APB1LPENR_TIM6LPEN

#define RCC_APB1LPENR_TIM7LPEN

#define RCC_APB1LPENR_LCDLPEN

#define RCC_APB1LPENR_WWDGLPEN

#define RCC_APB1LPENR_SPI2LPEN

#define RCC_APB1LPENR_SPI3LPEN

#define RCC_APB1LPENR_USART2LPEN

#define RCC_APB1LPENR_USART3LPEN

#define RCC_APB1LPENR_UART4LPEN

#define RCC_APB1LPENR_UART5LPEN

#define RCC_APB1LPENR_I2C1LPEN

#define RCC_APB1LPENR_I2C2LPEN

#define RCC_APB1LPENR_USBLPEN

#define RCC_APB1LPENR_PWRLPEN

#define RCC_APB1LPENR_DACLPEN

#define RCC_APB1LPENR_COMPLPEN

#define RCC_CSR_LSION

#define RCC_CSR_LSIRDY

#define RCC_CSR_LSEON

#define RCC_CSR_LSERDY

#define RCC_CSR_LSEBYP

#define RCC_CSR_LSECSSON

#define RCC_CSR_LSECSSD

#define RCC_CSR_RTCSEL

#define RCC_CSR_RTCSEL_0

#define RCC_CSR_RTCSEL_1

#define RCC_CSR_RTCSEL_NOCLOCK

#define RCC_CSR_RTCSEL_LSE

#define RCC_CSR_RTCSEL_LSI

#define RCC_CSR_RTCSEL_HSE

#define RCC_CSR_RTCEN

#define RCC_CSR_RTCRST

#define RCC_CSR_RMVF

#define RCC_CSR_OBLRSTF

#define RCC_CSR_PINRSTF

#define RCC_CSR_PORRSTF

#define RCC_CSR_SFTRSTF

#define RCC_CSR_IWDGRSTF

#define RCC_CSR_WWDGRSTF

#define RCC_CSR_LPWRRSTF

#define RTC_TR_PM

#define RTC_TR_HT

#define RTC_TR_HT_0

#define RTC_TR_HT_1

#define RTC_TR_HU

#define RTC_TR_HU_0

#define RTC_TR_HU_1

#define RTC_TR_HU_2

#define RTC_TR_HU_3

#define RTC_TR_MNT

#define RTC_TR_MNT_0

#define RTC_TR_MNT_1

#define RTC_TR_MNT_2

#define RTC_TR_MNU

#define RTC_TR_MNU_0

#define RTC_TR_MNU_1

#define RTC_TR_MNU_2

#define RTC_TR_MNU_3

#define RTC_TR_ST

#define RTC_TR_ST_0

#define RTC_TR_ST_1

#define RTC_TR_ST_2

#define RTC_TR_SU

#define RTC_TR_SU_0

#define RTC_TR_SU_1

#define RTC_TR_SU_2

#define RTC_TR_SU_3

#define RTC_DR_YT

#define RTC_DR_YT_0

#define RTC_DR_YT_1

#define RTC_DR_YT_2

#define RTC_DR_YT_3

#define RTC_DR_YU

#define RTC_DR_YU_0

#define RTC_DR_YU_1

#define RTC_DR_YU_2

#define RTC_DR_YU_3

#define RTC_DR_WDU

#define RTC_DR_WDU_0

#define RTC_DR_WDU_1

#define RTC_DR_WDU_2

#define RTC_DR_MT

#define RTC_DR_MU

#define RTC_DR_MU_0

#define RTC_DR_MU_1

#define RTC_DR_MU_2

#define RTC_DR_MU_3

#define RTC_DR_DT

#define RTC_DR_DT_0

#define RTC_DR_DT_1

#define RTC_DR_DU

#define RTC_DR_DU_0

#define RTC_DR_DU_1

#define RTC_DR_DU_2

#define RTC_DR_DU_3

#define RTC_CR_COE

#define RTC_CR_OSEL

#define RTC_CR_OSEL_0

#define RTC_CR_OSEL_1

#define RTC_CR_POL

#define RTC_CR_COSEL

#define RTC_CR_BCK

#define RTC_CR_SUB1H

#define RTC_CR_ADD1H

#define RTC_CR_TSIE

#define RTC_CR_WUTIE

#define RTC_CR_ALRBIE

#define RTC_CR_ALRAIE

#define RTC_CR_TSE

#define RTC_CR_WUTE

#define RTC_CR_ALRBE

#define RTC_CR_ALRAE

#define RTC_CR_DCE

#define RTC_CR_FMT

#define RTC_CR_BYPSHAD

#define RTC_CR_REFCKON

#define RTC_CR_TSEDGE

#define RTC_CR_WUCKSEL

#define RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_2

#define RTC_ISR_RECALPF

#define RTC_ISR_TAMP3F

#define RTC_ISR_TAMP2F

#define RTC_ISR_TAMP1F

#define RTC_ISR_TSOVF

#define RTC_ISR_TSF

#define RTC_ISR_WUTF

#define RTC_ISR_ALRBF

#define RTC_ISR_ALRAF

#define RTC_ISR_INIT

#define RTC_ISR_INITF

#define RTC_ISR_RSF

#define RTC_ISR_INITS

#define RTC_ISR_SHPF

#define RTC_ISR_WUTWF

#define RTC_ISR_ALRBWF

#define RTC_ISR_ALRAWF

#define RTC_PRER_PREDIV_A

#define RTC_PRER_PREDIV_S

#define RTC_WUTR_WUT

#define RTC_CALIBR_DCS

#define RTC_CALIBR_DC

#define RTC_ALRMAR_MSK4

#define RTC_ALRMAR_WDSEL

#define RTC_ALRMAR_DT

#define RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DU

#define RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_3

#define RTC_ALRMAR_MSK3

#define RTC_ALRMAR_PM

#define RTC_ALRMAR_HT

#define RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HU

#define RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_3

#define RTC_ALRMAR_MSK2

#define RTC_ALRMAR_MNT

#define RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNU

#define RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MSK1

#define RTC_ALRMAR_ST

#define RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_2

#define RTC_ALRMAR_SU

#define RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_3

#define RTC_ALRMBR_MSK4

#define RTC_ALRMBR_WDSEL

#define RTC_ALRMBR_DT

#define RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DU

#define RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_3

#define RTC_ALRMBR_MSK3

#define RTC_ALRMBR_PM

#define RTC_ALRMBR_HT

#define RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HU

#define RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_3

#define RTC_ALRMBR_MSK2

#define RTC_ALRMBR_MNT

#define RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNU

#define RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MSK1

#define RTC_ALRMBR_ST

#define RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_2

#define RTC_ALRMBR_SU

#define RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_3

#define RTC_WPR_KEY

#define RTC_SSR_SS

#define RTC_SHIFTR_SUBFS

#define RTC_SHIFTR_ADD1S

#define RTC_TSTR_PM

#define RTC_TSTR_HT

#define RTC_TSTR_HT_0

#define RTC_TSTR_HT_1

#define RTC_TSTR_HU

#define RTC_TSTR_HU_0

#define RTC_TSTR_HU_1

#define RTC_TSTR_HU_2

#define RTC_TSTR_HU_3

#define RTC_TSTR_MNT

#define RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_2

#define RTC_TSTR_MNU

#define RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_3

#define RTC_TSTR_ST

#define RTC_TSTR_ST_0

#define RTC_TSTR_ST_1

#define RTC_TSTR_ST_2

#define RTC_TSTR_SU

#define RTC_TSTR_SU_0

#define RTC_TSTR_SU_1

#define RTC_TSTR_SU_2

#define RTC_TSTR_SU_3

#define RTC_TSDR_WDU

#define RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_2

#define RTC_TSDR_MT

#define RTC_TSDR_MU

#define RTC_TSDR_MU_0

#define RTC_TSDR_MU_1

#define RTC_TSDR_MU_2

#define RTC_TSDR_MU_3

#define RTC_TSDR_DT

#define RTC_TSDR_DT_0

#define RTC_TSDR_DT_1

#define RTC_TSDR_DU

#define RTC_TSDR_DU_0

#define RTC_TSDR_DU_1

#define RTC_TSDR_DU_2

#define RTC_TSDR_DU_3

#define RTC_TSSSR_SS

#define RTC_CALR_CALP

#define RTC_CALR_CALW8

#define RTC_CALR_CALW16

#define RTC_CALR_CALM

#define RTC_CALR_CALM_0

#define RTC_CALR_CALM_1

#define RTC_CALR_CALM_2

#define RTC_CALR_CALM_3

#define RTC_CALR_CALM_4

#define RTC_CALR_CALM_5

#define RTC_CALR_CALM_6

#define RTC_CALR_CALM_7

#define RTC_CALR_CALM_8

#define RTC_TAFCR_ALARMOUTTYPE

#define RTC_TAFCR_TAMPPUDIS

#define RTC_TAFCR_TAMPPRCH

#define RTC_TAFCR_TAMPPRCH_0

#define RTC_TAFCR_TAMPPRCH_1

#define RTC_TAFCR_TAMPFLT

#define RTC_TAFCR_TAMPFLT_0

#define RTC_TAFCR_TAMPFLT_1

#define RTC_TAFCR_TAMPFREQ

#define RTC_TAFCR_TAMPFREQ_0

#define RTC_TAFCR_TAMPFREQ_1

#define RTC_TAFCR_TAMPFREQ_2

#define RTC_TAFCR_TAMPTS

#define RTC_TAFCR_TAMP3TRG

#define RTC_TAFCR_TAMP3E

#define RTC_TAFCR_TAMP2TRG

#define RTC_TAFCR_TAMP2E

#define RTC_TAFCR_TAMPIE

#define RTC_TAFCR_TAMP1TRG

#define RTC_TAFCR_TAMP1E

#define RTC_ALRMASSR_MASKSS

#define RTC_ALRMASSR_MASKSS_0

#define RTC_ALRMASSR_MASKSS_1

#define RTC_ALRMASSR_MASKSS_2

#define RTC_ALRMASSR_MASKSS_3

#define RTC_ALRMASSR_SS

#define RTC_ALRMBSSR_MASKSS

#define RTC_ALRMBSSR_MASKSS_0

#define RTC_ALRMBSSR_MASKSS_1

#define RTC_ALRMBSSR_MASKSS_2

#define RTC_ALRMBSSR_MASKSS_3

#define RTC_ALRMBSSR_SS

#define RTC_BKP0R

#define RTC_BKP1R

#define RTC_BKP2R

#define RTC_BKP3R

#define RTC_BKP4R

#define RTC_BKP5R

#define RTC_BKP6R

#define RTC_BKP7R

#define RTC_BKP8R

#define RTC_BKP9R

#define RTC_BKP10R

#define RTC_BKP11R

#define RTC_BKP12R

#define RTC_BKP13R

#define RTC_BKP14R

#define RTC_BKP15R

#define RTC_BKP16R

#define RTC_BKP17R

#define RTC_BKP18R

#define RTC_BKP19R

#define RTC_BKP20R

#define RTC_BKP21R

#define RTC_BKP22R

#define RTC_BKP23R

#define RTC_BKP24R

#define RTC_BKP25R

#define RTC_BKP26R

#define RTC_BKP27R

#define RTC_BKP28R

#define RTC_BKP29R

#define RTC_BKP30R

#define RTC_BKP31R

#define SDIO_POWER_PWRCTRL

#define SDIO_POWER_PWRCTRL_0

#define SDIO_POWER_PWRCTRL_1

#define SDIO_CLKCR_CLKDIV

#define SDIO_CLKCR_CLKEN

#define SDIO_CLKCR_PWRSAV

#define SDIO_CLKCR_BYPASS

#define SDIO_CLKCR_WIDBUS

#define SDIO_CLKCR_WIDBUS_0

#define SDIO_CLKCR_WIDBUS_1

#define SDIO_CLKCR_NEGEDGE

#define SDIO_CLKCR_HWFC_EN

#define SDIO_ARG_CMDARG

#define SDIO_CMD_CMDINDEX

#define SDIO_CMD_WAITRESP

#define SDIO_CMD_WAITRESP_0

#define SDIO_CMD_WAITRESP_1

#define SDIO_CMD_WAITINT

#define SDIO_CMD_WAITPEND

#define SDIO_CMD_CPSMEN

#define SDIO_CMD_SDIOSUSPEND

#define SDIO_CMD_ENCMDCOMPL

#define SDIO_CMD_NIEN

#define SDIO_CMD_CEATACMD

#define SDIO_RESPCMD_RESPCMD

#define SDIO_RESP0_CARDSTATUS0

#define SDIO_RESP1_CARDSTATUS1

#define SDIO_RESP2_CARDSTATUS2

#define SDIO_RESP3_CARDSTATUS3

#define SDIO_RESP4_CARDSTATUS4

#define SDIO_DTIMER_DATATIME

#define SDIO_DLEN_DATALENGTH

#define SDIO_DCTRL_DTEN

#define SDIO_DCTRL_DTDIR

#define SDIO_DCTRL_DTMODE

#define SDIO_DCTRL_DMAEN

#define SDIO_DCTRL_DBLOCKSIZE

#define SDIO_DCTRL_DBLOCKSIZE_0

#define SDIO_DCTRL_DBLOCKSIZE_1

#define SDIO_DCTRL_DBLOCKSIZE_2

#define SDIO_DCTRL_DBLOCKSIZE_3

#define SDIO_DCTRL_RWSTART

#define SDIO_DCTRL_RWSTOP

#define SDIO_DCTRL_RWMOD

#define SDIO_DCTRL_SDIOEN

#define SDIO_DCOUNT_DATACOUNT

#define SDIO_STA_CCRCFAIL

#define SDIO_STA_DCRCFAIL

#define SDIO_STA_CTIMEOUT

#define SDIO_STA_DTIMEOUT

#define SDIO_STA_TXUNDERR

#define SDIO_STA_RXOVERR

#define SDIO_STA_CMDREND

#define SDIO_STA_CMDSENT

#define SDIO_STA_DATAEND

#define SDIO_STA_STBITERR

#define SDIO_STA_DBCKEND

#define SDIO_STA_CMDACT

#define SDIO_STA_TXACT

#define SDIO_STA_RXACT

#define SDIO_STA_TXFIFOHE

#define SDIO_STA_RXFIFOHF

#define SDIO_STA_TXFIFOF

#define SDIO_STA_RXFIFOF

#define SDIO_STA_TXFIFOE

#define SDIO_STA_RXFIFOE

#define SDIO_STA_TXDAVL

#define SDIO_STA_RXDAVL

#define SDIO_STA_SDIOIT

#define SDIO_STA_CEATAEND

#define SDIO_ICR_CCRCFAILC

#define SDIO_ICR_DCRCFAILC

#define SDIO_ICR_CTIMEOUTC

#define SDIO_ICR_DTIMEOUTC

#define SDIO_ICR_TXUNDERRC

#define SDIO_ICR_RXOVERRC

#define SDIO_ICR_CMDRENDC

#define SDIO_ICR_CMDSENTC

#define SDIO_ICR_DATAENDC

#define SDIO_ICR_STBITERRC

#define SDIO_ICR_DBCKENDC

#define SDIO_ICR_SDIOITC

#define SDIO_ICR_CEATAENDC

#define SDIO_MASK_CCRCFAILIE

#define SDIO_MASK_DCRCFAILIE

#define SDIO_MASK_CTIMEOUTIE

#define SDIO_MASK_DTIMEOUTIE

#define SDIO_MASK_TXUNDERRIE

#define SDIO_MASK_RXOVERRIE

#define SDIO_MASK_CMDRENDIE

#define SDIO_MASK_CMDSENTIE

#define SDIO_MASK_DATAENDIE

#define SDIO_MASK_STBITERRIE

#define SDIO_MASK_DBCKENDIE

#define SDIO_MASK_CMDACTIE

#define SDIO_MASK_TXACTIE

#define SDIO_MASK_RXACTIE

#define SDIO_MASK_TXFIFOHEIE

#define SDIO_MASK_RXFIFOHFIE

#define SDIO_MASK_TXFIFOFIE

#define SDIO_MASK_RXFIFOFIE

#define SDIO_MASK_TXFIFOEIE

#define SDIO_MASK_RXFIFOEIE

#define SDIO_MASK_TXDAVLIE

#define SDIO_MASK_RXDAVLIE

#define SDIO_MASK_SDIOITIE

#define SDIO_MASK_CEATAENDIE

#define SDIO_FIFOCNT_FIFOCOUNT

#define SDIO_FIFO_FIFODATA

#define SPI_CR1_CPHA

#define SPI_CR1_CPOL

#define SPI_CR1_MSTR

#define SPI_CR1_BR

#define SPI_CR1_BR_0

#define SPI_CR1_BR_1

#define SPI_CR1_BR_2

#define SPI_CR1_SPE

#define SPI_CR1_LSBFIRST

#define SPI_CR1_SSI

#define SPI_CR1_SSM

#define SPI_CR1_RXONLY

#define SPI_CR1_DFF

#define SPI_CR1_CRCNEXT

#define SPI_CR1_CRCEN

#define SPI_CR1_BIDIOE

#define SPI_CR1_BIDIMODE

#define SPI_CR2_RXDMAEN

#define SPI_CR2_TXDMAEN

#define SPI_CR2_SSOE

#define SPI_CR2_FRF

#define SPI_CR2_ERRIE

#define SPI_CR2_RXNEIE

#define SPI_CR2_TXEIE

#define SPI_SR_RXNE

#define SPI_SR_TXE

#define SPI_SR_CHSIDE

#define SPI_SR_UDR

#define SPI_SR_CRCERR

#define SPI_SR_MODF

#define SPI_SR_OVR

#define SPI_SR_BSY

#define SPI_DR_DR

#define SPI_CRCPR_CRCPOLY

#define SPI_RXCRCR_RXCRC

#define SPI_TXCRCR_TXCRC

#define SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SMOD

#define SPI_I2SPR_I2SDIV

#define SPI_I2SPR_ODD

#define SPI_I2SPR_MCKOE

#define SYSCFG_MEMRMP_MEM_MODE

#define SYSCFG_MEMRMP_MEM_MODE_0

#define SYSCFG_MEMRMP_MEM_MODE_1

#define SYSCFG_MEMRMP_BOOT_MODE

#define SYSCFG_MEMRMP_BOOT_MODE_0

#define SYSCFG_MEMRMP_BOOT_MODE_1

#define SYSCFG_PMC_USB_PU

#define SYSCFG_EXTICR1_EXTI0

#define SYSCFG_EXTICR1_EXTI1

#define SYSCFG_EXTICR1_EXTI2

#define SYSCFG_EXTICR1_EXTI3

* @brief EXTI0 configuration

#define SYSCFG_EXTICR1_EXTI0_PA

#define SYSCFG_EXTICR1_EXTI0_PB

#define SYSCFG_EXTICR1_EXTI0_PC

#define SYSCFG_EXTICR1_EXTI0_PD

#define SYSCFG_EXTICR1_EXTI0_PE

#define SYSCFG_EXTICR1_EXTI0_PH

#define SYSCFG_EXTICR1_EXTI0_PF

#define SYSCFG_EXTICR1_EXTI0_PG

* @brief EXTI1 configuration

#define SYSCFG_EXTICR1_EXTI1_PA

#define SYSCFG_EXTICR1_EXTI1_PB

#define SYSCFG_EXTICR1_EXTI1_PC

#define SYSCFG_EXTICR1_EXTI1_PD

#define SYSCFG_EXTICR1_EXTI1_PE

#define SYSCFG_EXTICR1_EXTI1_PH

#define SYSCFG_EXTICR1_EXTI1_PF

#define SYSCFG_EXTICR1_EXTI1_PG

* @brief EXTI2 configuration

#define SYSCFG_EXTICR1_EXTI2_PA

#define SYSCFG_EXTICR1_EXTI2_PB

#define SYSCFG_EXTICR1_EXTI2_PC

#define SYSCFG_EXTICR1_EXTI2_PD

#define SYSCFG_EXTICR1_EXTI2_PE

#define SYSCFG_EXTICR1_EXTI2_PH

#define SYSCFG_EXTICR1_EXTI2_PF

#define SYSCFG_EXTICR1_EXTI2_PG

* @brief EXTI3 configuration

#define SYSCFG_EXTICR1_EXTI3_PA

#define SYSCFG_EXTICR1_EXTI3_PB

#define SYSCFG_EXTICR1_EXTI3_PC

#define SYSCFG_EXTICR1_EXTI3_PD

#define SYSCFG_EXTICR1_EXTI3_PE

#define SYSCFG_EXTICR1_EXTI3_PF

#define SYSCFG_EXTICR1_EXTI3_PG

#define SYSCFG_EXTICR2_EXTI4

#define SYSCFG_EXTICR2_EXTI5

#define SYSCFG_EXTICR2_EXTI6

#define SYSCFG_EXTICR2_EXTI7

* @brief EXTI4 configuration

#define SYSCFG_EXTICR2_EXTI4_PA

#define SYSCFG_EXTICR2_EXTI4_PB

#define SYSCFG_EXTICR2_EXTI4_PC

#define SYSCFG_EXTICR2_EXTI4_PD

#define SYSCFG_EXTICR2_EXTI4_PE

#define SYSCFG_EXTICR2_EXTI4_PF

#define SYSCFG_EXTICR2_EXTI4_PG

* @brief EXTI5 configuration

#define SYSCFG_EXTICR2_EXTI5_PA

#define SYSCFG_EXTICR2_EXTI5_PB

#define SYSCFG_EXTICR2_EXTI5_PC

#define SYSCFG_EXTICR2_EXTI5_PD

#define SYSCFG_EXTICR2_EXTI5_PE

#define SYSCFG_EXTICR2_EXTI5_PF

#define SYSCFG_EXTICR2_EXTI5_PG

* @brief EXTI6 configuration

#define SYSCFG_EXTICR2_EXTI6_PA

#define SYSCFG_EXTICR2_EXTI6_PB

#define SYSCFG_EXTICR2_EXTI6_PC

#define SYSCFG_EXTICR2_EXTI6_PD

#define SYSCFG_EXTICR2_EXTI6_PE

#define SYSCFG_EXTICR2_EXTI6_PF

#define SYSCFG_EXTICR2_EXTI6_PG

* @brief EXTI7 configuration

#define SYSCFG_EXTICR2_EXTI7_PA

#define SYSCFG_EXTICR2_EXTI7_PB

#define SYSCFG_EXTICR2_EXTI7_PC

#define SYSCFG_EXTICR2_EXTI7_PD

#define SYSCFG_EXTICR2_EXTI7_PE

#define SYSCFG_EXTICR2_EXTI7_PF

#define SYSCFG_EXTICR2_EXTI7_PG

#define SYSCFG_EXTICR3_EXTI8

#define SYSCFG_EXTICR3_EXTI9

#define SYSCFG_EXTICR3_EXTI10

#define SYSCFG_EXTICR3_EXTI11

* @brief EXTI8 configuration

#define SYSCFG_EXTICR3_EXTI8_PA

#define SYSCFG_EXTICR3_EXTI8_PB

#define SYSCFG_EXTICR3_EXTI8_PC

#define SYSCFG_EXTICR3_EXTI8_PD

#define SYSCFG_EXTICR3_EXTI8_PE

#define SYSCFG_EXTICR3_EXTI8_PF

#define SYSCFG_EXTICR3_EXTI8_PG

* @brief EXTI9 configuration

#define SYSCFG_EXTICR3_EXTI9_PA

#define SYSCFG_EXTICR3_EXTI9_PB

#define SYSCFG_EXTICR3_EXTI9_PC

#define SYSCFG_EXTICR3_EXTI9_PD

#define SYSCFG_EXTICR3_EXTI9_PE

#define SYSCFG_EXTICR3_EXTI9_PF

#define SYSCFG_EXTICR3_EXTI9_PG

* @brief EXTI10 configuration

#define SYSCFG_EXTICR3_EXTI10_PA

#define SYSCFG_EXTICR3_EXTI10_PB

#define SYSCFG_EXTICR3_EXTI10_PC

#define SYSCFG_EXTICR3_EXTI10_PD

#define SYSCFG_EXTICR3_EXTI10_PE

#define SYSCFG_EXTICR3_EXTI10_PF

#define SYSCFG_EXTICR3_EXTI10_PG

* @brief EXTI11 configuration

#define SYSCFG_EXTICR3_EXTI11_PA

#define SYSCFG_EXTICR3_EXTI11_PB

#define SYSCFG_EXTICR3_EXTI11_PC

#define SYSCFG_EXTICR3_EXTI11_PD

#define SYSCFG_EXTICR3_EXTI11_PE

#define SYSCFG_EXTICR3_EXTI11_PF

#define SYSCFG_EXTICR3_EXTI11_PG

#define SYSCFG_EXTICR4_EXTI12

#define SYSCFG_EXTICR4_EXTI13

#define SYSCFG_EXTICR4_EXTI14

#define SYSCFG_EXTICR4_EXTI15

* @brief EXTI12 configuration

#define SYSCFG_EXTICR4_EXTI12_PA

#define SYSCFG_EXTICR4_EXTI12_PB

#define SYSCFG_EXTICR4_EXTI12_PC

#define SYSCFG_EXTICR4_EXTI12_PD

#define SYSCFG_EXTICR4_EXTI12_PE

#define SYSCFG_EXTICR4_EXTI12_PF

#define SYSCFG_EXTICR4_EXTI12_PG

* @brief EXTI13 configuration

#define SYSCFG_EXTICR4_EXTI13_PA

#define SYSCFG_EXTICR4_EXTI13_PB

#define SYSCFG_EXTICR4_EXTI13_PC

#define SYSCFG_EXTICR4_EXTI13_PD

#define SYSCFG_EXTICR4_EXTI13_PE

#define SYSCFG_EXTICR4_EXTI13_PF

#define SYSCFG_EXTICR4_EXTI13_PG

* @brief EXTI14 configuration

#define SYSCFG_EXTICR4_EXTI14_PA

#define SYSCFG_EXTICR4_EXTI14_PB

#define SYSCFG_EXTICR4_EXTI14_PC

#define SYSCFG_EXTICR4_EXTI14_PD

#define SYSCFG_EXTICR4_EXTI14_PE

#define SYSCFG_EXTICR4_EXTI14_PF

#define SYSCFG_EXTICR4_EXTI14_PG

* @brief EXTI15 configuration

#define SYSCFG_EXTICR4_EXTI15_PA

#define SYSCFG_EXTICR4_EXTI15_PB

#define SYSCFG_EXTICR4_EXTI15_PC

#define SYSCFG_EXTICR4_EXTI15_PD

#define SYSCFG_EXTICR4_EXTI15_PE

#define SYSCFG_EXTICR4_EXTI15_PF

#define SYSCFG_EXTICR4_EXTI15_PG

#define RI_ICR_IC1Z

#define RI_ICR_IC1Z_0

#define RI_ICR_IC1Z_1

#define RI_ICR_IC1Z_2

#define RI_ICR_IC1Z_3

#define RI_ICR_IC2Z

#define RI_ICR_IC2Z_0

#define RI_ICR_IC2Z_1

#define RI_ICR_IC2Z_2

#define RI_ICR_IC2Z_3

#define RI_ICR_IC3Z

#define RI_ICR_IC3Z_0

#define RI_ICR_IC3Z_1

#define RI_ICR_IC3Z_2

#define RI_ICR_IC3Z_3

#define RI_ICR_IC4Z

#define RI_ICR_IC4Z_0

#define RI_ICR_IC4Z_1

#define RI_ICR_IC4Z_2

#define RI_ICR_IC4Z_3

#define RI_ICR_TIM

#define RI_ICR_TIM_0

#define RI_ICR_TIM_1

#define RI_ICR_IC1

#define RI_ICR_IC2

#define RI_ICR_IC3

#define RI_ICR_IC4

#define RI_ASCR1_CH

#define RI_ASCR1_CH_0

#define RI_ASCR1_CH_1

#define RI_ASCR1_CH_2

#define RI_ASCR1_CH_3

#define RI_ASCR1_CH_4

#define RI_ASCR1_CH_5

#define RI_ASCR1_CH_6

#define RI_ASCR1_CH_7

#define RI_ASCR1_CH_8

#define RI_ASCR1_CH_9

#define RI_ASCR1_CH_10

#define RI_ASCR1_CH_11

#define RI_ASCR1_CH_12

#define RI_ASCR1_CH_13

#define RI_ASCR1_CH_14

#define RI_ASCR1_CH_15

#define RI_ASCR1_CH_31

#define RI_ASCR1_CH_18

#define RI_ASCR1_CH_19

#define RI_ASCR1_CH_20

#define RI_ASCR1_CH_21

#define RI_ASCR1_CH_22

#define RI_ASCR1_CH_23

#define RI_ASCR1_CH_24

#define RI_ASCR1_CH_25

#define RI_ASCR1_VCOMP

#define RI_ASCR1_CH_27

#define RI_ASCR1_CH_28

#define RI_ASCR1_CH_29

#define RI_ASCR1_CH_30

#define RI_ASCR1_SCM

#define RI_ASCR2_GR10_1

#define RI_ASCR2_GR10_2

#define RI_ASCR2_GR10_3

#define RI_ASCR2_GR10_4

#define RI_ASCR2_GR6_1

#define RI_ASCR2_GR6_2

#define RI_ASCR2_GR5_1

#define RI_ASCR2_GR5_2

#define RI_ASCR2_GR5_3

#define RI_ASCR2_GR4_1

#define RI_ASCR2_GR4_2

#define RI_ASCR2_GR4_3

#define RI_ASCR2_GR4_4

#define RI_ASCR2_CH0b

#define RI_ASCR2_CH1b

#define RI_ASCR2_CH2b

#define RI_ASCR2_CH3b

#define RI_ASCR2_CH6b

#define RI_ASCR2_CH7b

#define RI_ASCR2_CH8b

#define RI_ASCR2_CH9b

#define RI_ASCR2_CH10b

#define RI_ASCR2_CH11b

#define RI_ASCR2_CH12b

#define RI_ASCR2_GR6_3

#define RI_ASCR2_GR6_4

#define RI_ASCR2_GR5_4

#define RI_HYSCR1_PA

#define RI_HYSCR1_PA_0

#define RI_HYSCR1_PA_1

#define RI_HYSCR1_PA_2

#define RI_HYSCR1_PA_3

#define RI_HYSCR1_PA_4

#define RI_HYSCR1_PA_5

#define RI_HYSCR1_PA_6

#define RI_HYSCR1_PA_7

#define RI_HYSCR1_PA_8

#define RI_HYSCR1_PA_9

#define RI_HYSCR1_PA_10

#define RI_HYSCR1_PA_11

#define RI_HYSCR1_PA_12

#define RI_HYSCR1_PA_13

#define RI_HYSCR1_PA_14

#define RI_HYSCR1_PA_15

#define RI_HYSCR1_PB

#define RI_HYSCR1_PB_0

#define RI_HYSCR1_PB_1

#define RI_HYSCR1_PB_2

#define RI_HYSCR1_PB_3

#define RI_HYSCR1_PB_4

#define RI_HYSCR1_PB_5

#define RI_HYSCR1_PB_6

#define RI_HYSCR1_PB_7

#define RI_HYSCR1_PB_8

#define RI_HYSCR1_PB_9

#define RI_HYSCR1_PB_10

#define RI_HYSCR1_PB_11

#define RI_HYSCR1_PB_12

#define RI_HYSCR1_PB_13

#define RI_HYSCR1_PB_14

#define RI_HYSCR1_PB_15

#define RI_HYSCR2_PC

#define RI_HYSCR2_PC_0

#define RI_HYSCR2_PC_1

#define RI_HYSCR2_PC_2

#define RI_HYSCR2_PC_3

#define RI_HYSCR2_PC_4

#define RI_HYSCR2_PC_5

#define RI_HYSCR2_PC_6

#define RI_HYSCR2_PC_7

#define RI_HYSCR2_PC_8

#define RI_HYSCR2_PC_9

#define RI_HYSCR2_PC_10

#define RI_HYSCR2_PC_11

#define RI_HYSCR2_PC_12

#define RI_HYSCR2_PC_13

#define RI_HYSCR2_PC_14

#define RI_HYSCR2_PC_15

#define RI_HYSCR2_PD

#define RI_HYSCR2_PD_0

#define RI_HYSCR2_PD_1

#define RI_HYSCR2_PD_2

#define RI_HYSCR2_PD_3

#define RI_HYSCR2_PD_4

#define RI_HYSCR2_PD_5

#define RI_HYSCR2_PD_6

#define RI_HYSCR2_PD_7

#define RI_HYSCR2_PD_8

#define RI_HYSCR2_PD_9

#define RI_HYSCR2_PD_10

#define RI_HYSCR2_PD_11

#define RI_HYSCR2_PD_12

#define RI_HYSCR2_PD_13

#define RI_HYSCR2_PD_14

#define RI_HYSCR2_PD_15

#define RI_HYSCR2_PE

#define RI_HYSCR2_PE_0

#define RI_HYSCR2_PE_1

#define RI_HYSCR2_PE_2

#define RI_HYSCR2_PE_3

#define RI_HYSCR2_PE_4

#define RI_HYSCR2_PE_5

#define RI_HYSCR2_PE_6

#define RI_HYSCR2_PE_7

#define RI_HYSCR2_PE_8

#define RI_HYSCR2_PE_9

#define RI_HYSCR2_PE_10

#define RI_HYSCR2_PE_11

#define RI_HYSCR2_PE_12

#define RI_HYSCR2_PE_13

#define RI_HYSCR2_PE_14

#define RI_HYSCR2_PE_15

#define RI_HYSCR3_PF

#define RI_HYSCR3_PF_0

#define RI_HYSCR3_PF_1

#define RI_HYSCR3_PF_2

#define RI_HYSCR3_PF_3

#define RI_HYSCR3_PF_4

#define RI_HYSCR3_PF_5

#define RI_HYSCR3_PF_6

#define RI_HYSCR3_PF_7

#define RI_HYSCR3_PF_8

#define RI_HYSCR3_PF_9

#define RI_HYSCR3_PF_10

#define RI_HYSCR3_PF_11

#define RI_HYSCR3_PF_12

#define RI_HYSCR3_PF_13

#define RI_HYSCR3_PF_14

#define RI_HYSCR3_PF_15

#define RI_HYSCR4_PG

#define RI_HYSCR4_PG_0

#define RI_HYSCR4_PG_1

#define RI_HYSCR4_PG_2

#define RI_HYSCR4_PG_3

#define RI_HYSCR4_PG_4

#define RI_HYSCR4_PG_5

#define RI_HYSCR4_PG_6

#define RI_HYSCR4_PG_7

#define RI_HYSCR4_PG_8

#define RI_HYSCR4_PG_9

#define RI_HYSCR4_PG_10

#define RI_HYSCR4_PG_11

#define RI_HYSCR4_PG_12

#define RI_HYSCR4_PG_13

#define RI_HYSCR4_PG_14

#define RI_HYSCR4_PG_15

#define TIM_CR1_CEN

#define TIM_CR1_UDIS

#define TIM_CR1_URS

#define TIM_CR1_OPM

#define TIM_CR1_DIR

#define TIM_CR1_CMS

#define TIM_CR1_CMS_0

#define TIM_CR1_CMS_1

#define TIM_CR1_ARPE

#define TIM_CR1_CKD

#define TIM_CR1_CKD_0

#define TIM_CR1_CKD_1

#define TIM_CR2_CCDS

#define TIM_CR2_MMS

#define TIM_CR2_MMS_0

#define TIM_CR2_MMS_1

#define TIM_CR2_MMS_2

#define TIM_CR2_TI1S

#define TIM_SMCR_SMS

#define TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_2

#define TIM_SMCR_OCCS

#define TIM_SMCR_TS

#define TIM_SMCR_TS_0

#define TIM_SMCR_TS_1

#define TIM_SMCR_TS_2

#define TIM_SMCR_MSM

#define TIM_SMCR_ETF

#define TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_3

#define TIM_SMCR_ETPS

#define TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_1

#define TIM_SMCR_ECE

#define TIM_SMCR_ETP

#define TIM_DIER_UIE

#define TIM_DIER_CC1IE

#define TIM_DIER_CC2IE

#define TIM_DIER_CC3IE

#define TIM_DIER_CC4IE

#define TIM_DIER_TIE

#define TIM_DIER_UDE

#define TIM_DIER_CC1DE

#define TIM_DIER_CC2DE

#define TIM_DIER_CC3DE

#define TIM_DIER_CC4DE

#define TIM_DIER_TDE

#define TIM_SR_UIF

#define TIM_SR_CC1IF

#define TIM_SR_CC2IF

#define TIM_SR_CC3IF

#define TIM_SR_CC4IF

#define TIM_SR_TIF

#define TIM_SR_CC1OF

#define TIM_SR_CC2OF

#define TIM_SR_CC3OF

#define TIM_SR_CC4OF

#define TIM_EGR_UG

#define TIM_EGR_CC1G

#define TIM_EGR_CC2G

#define TIM_EGR_CC3G

#define TIM_EGR_CC4G

#define TIM_EGR_TG

#define TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_1

#define TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1CE

#define TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_1

#define TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2CE

#define TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_3

#define TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_1

#define TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3CE

#define TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_1

#define TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4CE

#define TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_3

#define TIM_CCER_CC1E

#define TIM_CCER_CC1P

#define TIM_CCER_CC1NP

#define TIM_CCER_CC2E

#define TIM_CCER_CC2P

#define TIM_CCER_CC2NP

#define TIM_CCER_CC3E

#define TIM_CCER_CC3P

#define TIM_CCER_CC3NP

#define TIM_CCER_CC4E

#define TIM_CCER_CC4P

#define TIM_CCER_CC4NP

#define TIM_CNT_CNT

#define TIM_PSC_PSC

#define TIM_ARR_ARR

#define TIM_CCR1_CCR1

#define TIM_CCR2_CCR2

#define TIM_CCR3_CCR3

#define TIM_CCR4_CCR4

#define TIM_DCR_DBA

#define TIM_DCR_DBA_0

#define TIM_DCR_DBA_1

#define TIM_DCR_DBA_2

#define TIM_DCR_DBA_3

#define TIM_DCR_DBA_4

#define TIM_DCR_DBL

#define TIM_DCR_DBL_0

#define TIM_DCR_DBL_1

#define TIM_DCR_DBL_2

#define TIM_DCR_DBL_3

#define TIM_DCR_DBL_4

#define TIM_DMAR_DMAB

#define TIM_OR_TI1RMP

#define TIM_OR_TI1RMP_0

#define TIM_OR_TI1RMP_1

#define USART_SR_PE

#define USART_SR_FE

#define USART_SR_NE

#define USART_SR_ORE

#define USART_SR_IDLE

#define USART_SR_RXNE

#define USART_SR_TC

#define USART_SR_TXE

#define USART_SR_LBD

#define USART_SR_CTS

#define USART_DR_DR

#define USART_BRR_DIV_FRACTION

#define USART_BRR_DIV_MANTISSA

#define USART_CR1_SBK

#define USART_CR1_RWU

#define USART_CR1_RE

#define USART_CR1_TE

#define USART_CR1_IDLEIE

#define USART_CR1_RXNEIE

#define USART_CR1_TCIE

#define USART_CR1_TXEIE

#define USART_CR1_PEIE

#define USART_CR1_PS

#define USART_CR1_PCE

#define USART_CR1_WAKE

#define USART_CR1_M

#define USART_CR1_UE

#define USART_CR1_OVER8

#define USART_CR2_ADD

#define USART_CR2_LBDL

#define USART_CR2_LBDIE

#define USART_CR2_LBCL

#define USART_CR2_CPHA

#define USART_CR2_CPOL

#define USART_CR2_CLKEN

#define USART_CR2_STOP

#define USART_CR2_STOP_0

#define USART_CR2_STOP_1

#define USART_CR2_LINEN

#define USART_CR3_EIE

#define USART_CR3_IREN

#define USART_CR3_IRLP

#define USART_CR3_HDSEL

#define USART_CR3_NACK

#define USART_CR3_SCEN

#define USART_CR3_DMAR

#define USART_CR3_DMAT

#define USART_CR3_RTSE

#define USART_CR3_CTSE

#define USART_CR3_CTSIE

#define USART_CR3_ONEBIT

#define USART_GTPR_PSC

#define USART_GTPR_PSC_0

#define USART_GTPR_PSC_1

#define USART_GTPR_PSC_2

#define USART_GTPR_PSC_3

#define USART_GTPR_PSC_4

#define USART_GTPR_PSC_5

#define USART_GTPR_PSC_6

#define USART_GTPR_PSC_7

#define USART_GTPR_GT

#define USB_EP0R_EA

#define USB_EP0R_STAT_TX

#define USB_EP0R_STAT_TX_0

#define USB_EP0R_STAT_TX_1

#define USB_EP0R_DTOG_TX

#define USB_EP0R_CTR_TX

#define USB_EP0R_EP_KIND

#define USB_EP0R_EP_TYPE

#define USB_EP0R_EP_TYPE_0

#define USB_EP0R_EP_TYPE_1

#define USB_EP0R_SETUP

#define USB_EP0R_STAT_RX

#define USB_EP0R_STAT_RX_0

#define USB_EP0R_STAT_RX_1

#define USB_EP0R_DTOG_RX

#define USB_EP0R_CTR_RX

#define USB_EP1R_EA

#define USB_EP1R_STAT_TX

#define USB_EP1R_STAT_TX_0

#define USB_EP1R_STAT_TX_1

#define USB_EP1R_DTOG_TX

#define USB_EP1R_CTR_TX

#define USB_EP1R_EP_KIND

#define USB_EP1R_EP_TYPE

#define USB_EP1R_EP_TYPE_0

#define USB_EP1R_EP_TYPE_1

#define USB_EP1R_SETUP

#define USB_EP1R_STAT_RX

#define USB_EP1R_STAT_RX_0

#define USB_EP1R_STAT_RX_1

#define USB_EP1R_DTOG_RX

#define USB_EP1R_CTR_RX

#define USB_EP2R_EA

#define USB_EP2R_STAT_TX

#define USB_EP2R_STAT_TX_0

#define USB_EP2R_STAT_TX_1

#define USB_EP2R_DTOG_TX

#define USB_EP2R_CTR_TX

#define USB_EP2R_EP_KIND

#define USB_EP2R_EP_TYPE

#define USB_EP2R_EP_TYPE_0

#define USB_EP2R_EP_TYPE_1

#define USB_EP2R_SETUP

#define USB_EP2R_STAT_RX

#define USB_EP2R_STAT_RX_0

#define USB_EP2R_STAT_RX_1

#define USB_EP2R_DTOG_RX

#define USB_EP2R_CTR_RX

#define USB_EP3R_EA

#define USB_EP3R_STAT_TX

#define USB_EP3R_STAT_TX_0

#define USB_EP3R_STAT_TX_1

#define USB_EP3R_DTOG_TX

#define USB_EP3R_CTR_TX

#define USB_EP3R_EP_KIND

#define USB_EP3R_EP_TYPE

#define USB_EP3R_EP_TYPE_0

#define USB_EP3R_EP_TYPE_1

#define USB_EP3R_SETUP

#define USB_EP3R_STAT_RX

#define USB_EP3R_STAT_RX_0

#define USB_EP3R_STAT_RX_1

#define USB_EP3R_DTOG_RX

#define USB_EP3R_CTR_RX

#define USB_EP4R_EA

#define USB_EP4R_STAT_TX

#define USB_EP4R_STAT_TX_0

#define USB_EP4R_STAT_TX_1

#define USB_EP4R_DTOG_TX

#define USB_EP4R_CTR_TX

#define USB_EP4R_EP_KIND

#define USB_EP4R_EP_TYPE

#define USB_EP4R_EP_TYPE_0

#define USB_EP4R_EP_TYPE_1

#define USB_EP4R_SETUP

#define USB_EP4R_STAT_RX

#define USB_EP4R_STAT_RX_0

#define USB_EP4R_STAT_RX_1

#define USB_EP4R_DTOG_RX

#define USB_EP4R_CTR_RX

#define USB_EP5R_EA

#define USB_EP5R_STAT_TX

#define USB_EP5R_STAT_TX_0

#define USB_EP5R_STAT_TX_1

#define USB_EP5R_DTOG_TX

#define USB_EP5R_CTR_TX

#define USB_EP5R_EP_KIND

#define USB_EP5R_EP_TYPE

#define USB_EP5R_EP_TYPE_0

#define USB_EP5R_EP_TYPE_1

#define USB_EP5R_SETUP

#define USB_EP5R_STAT_RX

#define USB_EP5R_STAT_RX_0

#define USB_EP5R_STAT_RX_1

#define USB_EP5R_DTOG_RX

#define USB_EP5R_CTR_RX

#define USB_EP6R_EA

#define USB_EP6R_STAT_TX

#define USB_EP6R_STAT_TX_0

#define USB_EP6R_STAT_TX_1

#define USB_EP6R_DTOG_TX

#define USB_EP6R_CTR_TX

#define USB_EP6R_EP_KIND

#define USB_EP6R_EP_TYPE

#define USB_EP6R_EP_TYPE_0

#define USB_EP6R_EP_TYPE_1

#define USB_EP6R_SETUP

#define USB_EP6R_STAT_RX

#define USB_EP6R_STAT_RX_0

#define USB_EP6R_STAT_RX_1

#define USB_EP6R_DTOG_RX

#define USB_EP6R_CTR_RX

#define USB_EP7R_EA

#define USB_EP7R_STAT_TX

#define USB_EP7R_STAT_TX_0

#define USB_EP7R_STAT_TX_1

#define USB_EP7R_DTOG_TX

#define USB_EP7R_CTR_TX

#define USB_EP7R_EP_KIND

#define USB_EP7R_EP_TYPE

#define USB_EP7R_EP_TYPE_0

#define USB_EP7R_EP_TYPE_1

#define USB_EP7R_SETUP

#define USB_EP7R_STAT_RX

#define USB_EP7R_STAT_RX_0

#define USB_EP7R_STAT_RX_1

#define USB_EP7R_DTOG_RX

#define USB_EP7R_CTR_RX

#define USB_CNTR_FRES

#define USB_CNTR_PDWN

#define USB_CNTR_LP_MODE

#define USB_CNTR_FSUSP

#define USB_CNTR_RESUME

#define USB_CNTR_ESOFM

#define USB_CNTR_SOFM

#define USB_CNTR_RESETM

#define USB_CNTR_SUSPM

#define USB_CNTR_WKUPM

#define USB_CNTR_ERRM

#define USB_CNTR_PMAOVRM

#define USB_CNTR_CTRM

#define USB_ISTR_EP_ID

#define USB_ISTR_DIR

#define USB_ISTR_ESOF

#define USB_ISTR_SOF

#define USB_ISTR_RESET

#define USB_ISTR_SUSP

#define USB_ISTR_WKUP

#define USB_ISTR_ERR

#define USB_ISTR_PMAOVR

#define USB_ISTR_CTR

#define USB_FNR_FN

#define USB_FNR_LSOF

#define USB_FNR_LCK

#define USB_FNR_RXDM

#define USB_FNR_RXDP

#define USB_DADDR_ADD

#define USB_DADDR_ADD0

#define USB_DADDR_ADD1

#define USB_DADDR_ADD2

#define USB_DADDR_ADD3

#define USB_DADDR_ADD4

#define USB_DADDR_ADD5

#define USB_DADDR_ADD6

#define USB_DADDR_EF

#define USB_BTABLE_BTABLE

#define USB_ADDR0_TX_ADDR0_TX

#define USB_ADDR1_TX_ADDR1_TX

#define USB_ADDR2_TX_ADDR2_TX

#define USB_ADDR3_TX_ADDR3_TX

#define USB_ADDR4_TX_ADDR4_TX

#define USB_ADDR5_TX_ADDR5_TX

#define USB_ADDR6_TX_ADDR6_TX

#define USB_ADDR7_TX_ADDR7_TX

#define USB_COUNT0_TX_COUNT0_TX

#define USB_COUNT1_TX_COUNT1_TX

#define USB_COUNT2_TX_COUNT2_TX

#define USB_COUNT3_TX_COUNT3_TX

#define USB_COUNT4_TX_COUNT4_TX

#define USB_COUNT5_TX_COUNT5_TX

#define USB_COUNT6_TX_COUNT6_TX

#define USB_COUNT7_TX_COUNT7_TX

#define USB_COUNT0_TX_0_COUNT0_TX_0

#define USB_COUNT0_TX_1_COUNT0_TX_1

#define USB_COUNT1_TX_0_COUNT1_TX_0

#define USB_COUNT1_TX_1_COUNT1_TX_1

#define USB_COUNT2_TX_0_COUNT2_TX_0

#define USB_COUNT2_TX_1_COUNT2_TX_1

#define USB_COUNT3_TX_0_COUNT3_TX_0

#define USB_COUNT3_TX_1_COUNT3_TX_1

#define USB_COUNT4_TX_0_COUNT4_TX_0

#define USB_COUNT4_TX_1_COUNT4_TX_1

#define USB_COUNT5_TX_0_COUNT5_TX_0

#define USB_COUNT5_TX_1_COUNT5_TX_1

#define USB_COUNT6_TX_0_COUNT6_TX_0

#define USB_COUNT6_TX_1_COUNT6_TX_1

#define USB_COUNT7_TX_0_COUNT7_TX_0

#define USB_COUNT7_TX_1_COUNT7_TX_1

#define USB_ADDR0_RX_ADDR0_RX

#define USB_ADDR1_RX_ADDR1_RX

#define USB_ADDR2_RX_ADDR2_RX

#define USB_ADDR3_RX_ADDR3_RX

#define USB_ADDR4_RX_ADDR4_RX

#define USB_ADDR5_RX_ADDR5_RX

#define USB_ADDR6_RX_ADDR6_RX

#define USB_ADDR7_RX_ADDR7_RX

#define USB_COUNT0_RX_COUNT0_RX

#define USB_COUNT0_RX_NUM_BLOCK

#define USB_COUNT0_RX_NUM_BLOCK_0

#define USB_COUNT0_RX_NUM_BLOCK_1

#define USB_COUNT0_RX_NUM_BLOCK_2

#define USB_COUNT0_RX_NUM_BLOCK_3

#define USB_COUNT0_RX_NUM_BLOCK_4

#define USB_COUNT0_RX_BLSIZE

#define USB_COUNT1_RX_COUNT1_RX

#define USB_COUNT1_RX_NUM_BLOCK

#define USB_COUNT1_RX_NUM_BLOCK_0

#define USB_COUNT1_RX_NUM_BLOCK_1

#define USB_COUNT1_RX_NUM_BLOCK_2

#define USB_COUNT1_RX_NUM_BLOCK_3

#define USB_COUNT1_RX_NUM_BLOCK_4

#define USB_COUNT1_RX_BLSIZE

#define USB_COUNT2_RX_COUNT2_RX

#define USB_COUNT2_RX_NUM_BLOCK

#define USB_COUNT2_RX_NUM_BLOCK_0

#define USB_COUNT2_RX_NUM_BLOCK_1

#define USB_COUNT2_RX_NUM_BLOCK_2

#define USB_COUNT2_RX_NUM_BLOCK_3

#define USB_COUNT2_RX_NUM_BLOCK_4

#define USB_COUNT2_RX_BLSIZE

#define USB_COUNT3_RX_COUNT3_RX

#define USB_COUNT3_RX_NUM_BLOCK

#define USB_COUNT3_RX_NUM_BLOCK_0

#define USB_COUNT3_RX_NUM_BLOCK_1

#define USB_COUNT3_RX_NUM_BLOCK_2

#define USB_COUNT3_RX_NUM_BLOCK_3

#define USB_COUNT3_RX_NUM_BLOCK_4

#define USB_COUNT3_RX_BLSIZE

#define USB_COUNT4_RX_COUNT4_RX

#define USB_COUNT4_RX_NUM_BLOCK

#define USB_COUNT4_RX_NUM_BLOCK_0

#define USB_COUNT4_RX_NUM_BLOCK_1

#define USB_COUNT4_RX_NUM_BLOCK_2

#define USB_COUNT4_RX_NUM_BLOCK_3

#define USB_COUNT4_RX_NUM_BLOCK_4

#define USB_COUNT4_RX_BLSIZE

#define USB_COUNT5_RX_COUNT5_RX

#define USB_COUNT5_RX_NUM_BLOCK

#define USB_COUNT5_RX_NUM_BLOCK_0

#define USB_COUNT5_RX_NUM_BLOCK_1

#define USB_COUNT5_RX_NUM_BLOCK_2

#define USB_COUNT5_RX_NUM_BLOCK_3

#define USB_COUNT5_RX_NUM_BLOCK_4

#define USB_COUNT5_RX_BLSIZE

#define USB_COUNT6_RX_COUNT6_RX

#define USB_COUNT6_RX_NUM_BLOCK

#define USB_COUNT6_RX_NUM_BLOCK_0

#define USB_COUNT6_RX_NUM_BLOCK_1

#define USB_COUNT6_RX_NUM_BLOCK_2

#define USB_COUNT6_RX_NUM_BLOCK_3

#define USB_COUNT6_RX_NUM_BLOCK_4

#define USB_COUNT6_RX_BLSIZE

#define USB_COUNT7_RX_COUNT7_RX

#define USB_COUNT7_RX_NUM_BLOCK

#define USB_COUNT7_RX_NUM_BLOCK_0

#define USB_COUNT7_RX_NUM_BLOCK_1

#define USB_COUNT7_RX_NUM_BLOCK_2

#define USB_COUNT7_RX_NUM_BLOCK_3

#define USB_COUNT7_RX_NUM_BLOCK_4

#define USB_COUNT7_RX_BLSIZE

#define USB_COUNT0_RX_0_COUNT0_RX_0

#define USB_COUNT0_RX_0_NUM_BLOCK_0

#define USB_COUNT0_RX_0_NUM_BLOCK_0_0

#define USB_COUNT0_RX_0_NUM_BLOCK_0_1

#define USB_COUNT0_RX_0_NUM_BLOCK_0_2

#define USB_COUNT0_RX_0_NUM_BLOCK_0_3

#define USB_COUNT0_RX_0_NUM_BLOCK_0_4

#define USB_COUNT0_RX_0_BLSIZE_0

#define USB_COUNT0_RX_1_COUNT0_RX_1

#define USB_COUNT0_RX_1_NUM_BLOCK_1

#define USB_COUNT0_RX_1_NUM_BLOCK_1_0

#define USB_COUNT0_RX_1_NUM_BLOCK_1_1

#define USB_COUNT0_RX_1_NUM_BLOCK_1_2

#define USB_COUNT0_RX_1_NUM_BLOCK_1_3

#define USB_COUNT0_RX_1_NUM_BLOCK_1_4

#define USB_COUNT0_RX_1_BLSIZE_1

#define USB_COUNT1_RX_0_COUNT1_RX_0

#define USB_COUNT1_RX_0_NUM_BLOCK_0

#define USB_COUNT1_RX_0_NUM_BLOCK_0_0

#define USB_COUNT1_RX_0_NUM_BLOCK_0_1

#define USB_COUNT1_RX_0_NUM_BLOCK_0_2

#define USB_COUNT1_RX_0_NUM_BLOCK_0_3

#define USB_COUNT1_RX_0_NUM_BLOCK_0_4

#define USB_COUNT1_RX_0_BLSIZE_0

#define USB_COUNT1_RX_1_COUNT1_RX_1

#define USB_COUNT1_RX_1_NUM_BLOCK_1

#define USB_COUNT1_RX_1_NUM_BLOCK_1_0

#define USB_COUNT1_RX_1_NUM_BLOCK_1_1

#define USB_COUNT1_RX_1_NUM_BLOCK_1_2

#define USB_COUNT1_RX_1_NUM_BLOCK_1_3

#define USB_COUNT1_RX_1_NUM_BLOCK_1_4

#define USB_COUNT1_RX_1_BLSIZE_1

#define USB_COUNT2_RX_0_COUNT2_RX_0

#define USB_COUNT2_RX_0_NUM_BLOCK_0

#define USB_COUNT2_RX_0_NUM_BLOCK_0_0

#define USB_COUNT2_RX_0_NUM_BLOCK_0_1

#define USB_COUNT2_RX_0_NUM_BLOCK_0_2

#define USB_COUNT2_RX_0_NUM_BLOCK_0_3

#define USB_COUNT2_RX_0_NUM_BLOCK_0_4

#define USB_COUNT2_RX_0_BLSIZE_0

#define USB_COUNT2_RX_1_COUNT2_RX_1

#define USB_COUNT2_RX_1_NUM_BLOCK_1

#define USB_COUNT2_RX_1_NUM_BLOCK_1_0

#define USB_COUNT2_RX_1_NUM_BLOCK_1_1

#define USB_COUNT2_RX_1_NUM_BLOCK_1_2

#define USB_COUNT2_RX_1_NUM_BLOCK_1_3

#define USB_COUNT2_RX_1_NUM_BLOCK_1_4

#define USB_COUNT2_RX_1_BLSIZE_1

#define USB_COUNT3_RX_0_COUNT3_RX_0

#define USB_COUNT3_RX_0_NUM_BLOCK_0

#define USB_COUNT3_RX_0_NUM_BLOCK_0_0

#define USB_COUNT3_RX_0_NUM_BLOCK_0_1

#define USB_COUNT3_RX_0_NUM_BLOCK_0_2

#define USB_COUNT3_RX_0_NUM_BLOCK_0_3

#define USB_COUNT3_RX_0_NUM_BLOCK_0_4

#define USB_COUNT3_RX_0_BLSIZE_0

#define USB_COUNT3_RX_1_COUNT3_RX_1

#define USB_COUNT3_RX_1_NUM_BLOCK_1

#define USB_COUNT3_RX_1_NUM_BLOCK_1_0

#define USB_COUNT3_RX_1_NUM_BLOCK_1_1

#define USB_COUNT3_RX_1_NUM_BLOCK_1_2

#define USB_COUNT3_RX_1_NUM_BLOCK_1_3

#define USB_COUNT3_RX_1_NUM_BLOCK_1_4

#define USB_COUNT3_RX_1_BLSIZE_1

#define USB_COUNT4_RX_0_COUNT4_RX_0

#define USB_COUNT4_RX_0_NUM_BLOCK_0

#define USB_COUNT4_RX_0_NUM_BLOCK_0_0

#define USB_COUNT4_RX_0_NUM_BLOCK_0_1

#define USB_COUNT4_RX_0_NUM_BLOCK_0_2

#define USB_COUNT4_RX_0_NUM_BLOCK_0_3

#define USB_COUNT4_RX_0_NUM_BLOCK_0_4

#define USB_COUNT4_RX_0_BLSIZE_0

#define USB_COUNT4_RX_1_COUNT4_RX_1

#define USB_COUNT4_RX_1_NUM_BLOCK_1

#define USB_COUNT4_RX_1_NUM_BLOCK_1_0

#define USB_COUNT4_RX_1_NUM_BLOCK_1_1

#define USB_COUNT4_RX_1_NUM_BLOCK_1_2

#define USB_COUNT4_RX_1_NUM_BLOCK_1_3

#define USB_COUNT4_RX_1_NUM_BLOCK_1_4

#define USB_COUNT4_RX_1_BLSIZE_1

#define USB_COUNT5_RX_0_COUNT5_RX_0

#define USB_COUNT5_RX_0_NUM_BLOCK_0

#define USB_COUNT5_RX_0_NUM_BLOCK_0_0

#define USB_COUNT5_RX_0_NUM_BLOCK_0_1

#define USB_COUNT5_RX_0_NUM_BLOCK_0_2

#define USB_COUNT5_RX_0_NUM_BLOCK_0_3

#define USB_COUNT5_RX_0_NUM_BLOCK_0_4

#define USB_COUNT5_RX_0_BLSIZE_0

#define USB_COUNT5_RX_1_COUNT5_RX_1

#define USB_COUNT5_RX_1_NUM_BLOCK_1

#define USB_COUNT5_RX_1_NUM_BLOCK_1_0

#define USB_COUNT5_RX_1_NUM_BLOCK_1_1

#define USB_COUNT5_RX_1_NUM_BLOCK_1_2

#define USB_COUNT5_RX_1_NUM_BLOCK_1_3

#define USB_COUNT5_RX_1_NUM_BLOCK_1_4

#define USB_COUNT5_RX_1_BLSIZE_1

#define USB_COUNT6_RX_0_COUNT6_RX_0

#define USB_COUNT6_RX_0_NUM_BLOCK_0

#define USB_COUNT6_RX_0_NUM_BLOCK_0_0

#define USB_COUNT6_RX_0_NUM_BLOCK_0_1

#define USB_COUNT6_RX_0_NUM_BLOCK_0_2

#define USB_COUNT6_RX_0_NUM_BLOCK_0_3

#define USB_COUNT6_RX_0_NUM_BLOCK_0_4

#define USB_COUNT6_RX_0_BLSIZE_0

#define USB_COUNT6_RX_1_COUNT6_RX_1

#define USB_COUNT6_RX_1_NUM_BLOCK_1

#define USB_COUNT6_RX_1_NUM_BLOCK_1_0

#define USB_COUNT6_RX_1_NUM_BLOCK_1_1

#define USB_COUNT6_RX_1_NUM_BLOCK_1_2

#define USB_COUNT6_RX_1_NUM_BLOCK_1_3

#define USB_COUNT6_RX_1_NUM_BLOCK_1_4

#define USB_COUNT6_RX_1_BLSIZE_1

#define USB_COUNT7_RX_0_COUNT7_RX_0

#define USB_COUNT7_RX_0_NUM_BLOCK_0

#define USB_COUNT7_RX_0_NUM_BLOCK_0_0

#define USB_COUNT7_RX_0_NUM_BLOCK_0_1

#define USB_COUNT7_RX_0_NUM_BLOCK_0_2

#define USB_COUNT7_RX_0_NUM_BLOCK_0_3

#define USB_COUNT7_RX_0_NUM_BLOCK_0_4

#define USB_COUNT7_RX_0_BLSIZE_0

#define USB_COUNT7_RX_1_COUNT7_RX_1

#define USB_COUNT7_RX_1_NUM_BLOCK_1

#define USB_COUNT7_RX_1_NUM_BLOCK_1_0

#define USB_COUNT7_RX_1_NUM_BLOCK_1_1

#define USB_COUNT7_RX_1_NUM_BLOCK_1_2

#define USB_COUNT7_RX_1_NUM_BLOCK_1_3

#define USB_COUNT7_RX_1_NUM_BLOCK_1_4

#define USB_COUNT7_RX_1_BLSIZE_1

#define WWDG_CR_T

#define WWDG_CR_T0

#define WWDG_CR_T1

#define WWDG_CR_T2

#define WWDG_CR_T3

#define WWDG_CR_T4

#define WWDG_CR_T5

#define WWDG_CR_T6

#define WWDG_CR_WDGA

#define WWDG_CFR_W

#define WWDG_CFR_W0

#define WWDG_CFR_W1

#define WWDG_CFR_W2

#define WWDG_CFR_W3

#define WWDG_CFR_W4

#define WWDG_CFR_W5

#define WWDG_CFR_W6

#define WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB0

#define WWDG_CFR_WDGTB1

#define WWDG_CFR_EWI

#define WWDG_SR_EWIF

#define SysTick_CTRL_ENABLE

#define SysTick_CTRL_TICKINT

#define SysTick_CTRL_CLKSOURCE

#define SysTick_CTRL_COUNTFLAG

#define SysTick_LOAD_RELOAD

#define SysTick_VAL_CURRENT

#define SysTick_CALIB_TENMS

#define SysTick_CALIB_SKEW

#define SysTick_CALIB_NOREF

#define NVIC_ISER_SETENA

#define NVIC_ISER_SETENA_0

#define NVIC_ISER_SETENA_1

#define NVIC_ISER_SETENA_2

#define NVIC_ISER_SETENA_3

#define NVIC_ISER_SETENA_4

#define NVIC_ISER_SETENA_5

#define NVIC_ISER_SETENA_6

#define NVIC_ISER_SETENA_7

#define NVIC_ISER_SETENA_8

#define NVIC_ISER_SETENA_9

#define NVIC_ISER_SETENA_10

#define NVIC_ISER_SETENA_11

#define NVIC_ISER_SETENA_12

#define NVIC_ISER_SETENA_13

#define NVIC_ISER_SETENA_14

#define NVIC_ISER_SETENA_15

#define NVIC_ISER_SETENA_16

#define NVIC_ISER_SETENA_17

#define NVIC_ISER_SETENA_18

#define NVIC_ISER_SETENA_19

#define NVIC_ISER_SETENA_20

#define NVIC_ISER_SETENA_21

#define NVIC_ISER_SETENA_22

#define NVIC_ISER_SETENA_23

#define NVIC_ISER_SETENA_24

#define NVIC_ISER_SETENA_25

#define NVIC_ISER_SETENA_26

#define NVIC_ISER_SETENA_27

#define NVIC_ISER_SETENA_28

#define NVIC_ISER_SETENA_29

#define NVIC_ISER_SETENA_30

#define NVIC_ISER_SETENA_31

#define NVIC_ICER_CLRENA

#define NVIC_ICER_CLRENA_0

#define NVIC_ICER_CLRENA_1

#define NVIC_ICER_CLRENA_2

#define NVIC_ICER_CLRENA_3

#define NVIC_ICER_CLRENA_4

#define NVIC_ICER_CLRENA_5

#define NVIC_ICER_CLRENA_6

#define NVIC_ICER_CLRENA_7

#define NVIC_ICER_CLRENA_8

#define NVIC_ICER_CLRENA_9

#define NVIC_ICER_CLRENA_10

#define NVIC_ICER_CLRENA_11

#define NVIC_ICER_CLRENA_12

#define NVIC_ICER_CLRENA_13

#define NVIC_ICER_CLRENA_14

#define NVIC_ICER_CLRENA_15

#define NVIC_ICER_CLRENA_16

#define NVIC_ICER_CLRENA_17

#define NVIC_ICER_CLRENA_18

#define NVIC_ICER_CLRENA_19

#define NVIC_ICER_CLRENA_20

#define NVIC_ICER_CLRENA_21

#define NVIC_ICER_CLRENA_22

#define NVIC_ICER_CLRENA_23

#define NVIC_ICER_CLRENA_24

#define NVIC_ICER_CLRENA_25

#define NVIC_ICER_CLRENA_26

#define NVIC_ICER_CLRENA_27

#define NVIC_ICER_CLRENA_28

#define NVIC_ICER_CLRENA_29

#define NVIC_ICER_CLRENA_30

#define NVIC_ICER_CLRENA_31

#define NVIC_ISPR_SETPEND

#define NVIC_ISPR_SETPEND_0

#define NVIC_ISPR_SETPEND_1

#define NVIC_ISPR_SETPEND_2

#define NVIC_ISPR_SETPEND_3

#define NVIC_ISPR_SETPEND_4

#define NVIC_ISPR_SETPEND_5

#define NVIC_ISPR_SETPEND_6

#define NVIC_ISPR_SETPEND_7

#define NVIC_ISPR_SETPEND_8

#define NVIC_ISPR_SETPEND_9

#define NVIC_ISPR_SETPEND_10

#define NVIC_ISPR_SETPEND_11

#define NVIC_ISPR_SETPEND_12

#define NVIC_ISPR_SETPEND_13

#define NVIC_ISPR_SETPEND_14

#define NVIC_ISPR_SETPEND_15

#define NVIC_ISPR_SETPEND_16

#define NVIC_ISPR_SETPEND_17

#define NVIC_ISPR_SETPEND_18

#define NVIC_ISPR_SETPEND_19

#define NVIC_ISPR_SETPEND_20

#define NVIC_ISPR_SETPEND_21

#define NVIC_ISPR_SETPEND_22

#define NVIC_ISPR_SETPEND_23

#define NVIC_ISPR_SETPEND_24

#define NVIC_ISPR_SETPEND_25

#define NVIC_ISPR_SETPEND_26

#define NVIC_ISPR_SETPEND_27

#define NVIC_ISPR_SETPEND_28

#define NVIC_ISPR_SETPEND_29

#define NVIC_ISPR_SETPEND_30

#define NVIC_ISPR_SETPEND_31

#define NVIC_ICPR_CLRPEND

#define NVIC_ICPR_CLRPEND_0

#define NVIC_ICPR_CLRPEND_1

#define NVIC_ICPR_CLRPEND_2

#define NVIC_ICPR_CLRPEND_3

#define NVIC_ICPR_CLRPEND_4

#define NVIC_ICPR_CLRPEND_5

#define NVIC_ICPR_CLRPEND_6

#define NVIC_ICPR_CLRPEND_7

#define NVIC_ICPR_CLRPEND_8

#define NVIC_ICPR_CLRPEND_9

#define NVIC_ICPR_CLRPEND_10

#define NVIC_ICPR_CLRPEND_11

#define NVIC_ICPR_CLRPEND_12

#define NVIC_ICPR_CLRPEND_13

#define NVIC_ICPR_CLRPEND_14

#define NVIC_ICPR_CLRPEND_15

#define NVIC_ICPR_CLRPEND_16

#define NVIC_ICPR_CLRPEND_17

#define NVIC_ICPR_CLRPEND_18

#define NVIC_ICPR_CLRPEND_19

#define NVIC_ICPR_CLRPEND_20

#define NVIC_ICPR_CLRPEND_21

#define NVIC_ICPR_CLRPEND_22

#define NVIC_ICPR_CLRPEND_23

#define NVIC_ICPR_CLRPEND_24

#define NVIC_ICPR_CLRPEND_25

#define NVIC_ICPR_CLRPEND_26

#define NVIC_ICPR_CLRPEND_27

#define NVIC_ICPR_CLRPEND_28

#define NVIC_ICPR_CLRPEND_29

#define NVIC_ICPR_CLRPEND_30

#define NVIC_ICPR_CLRPEND_31

#define NVIC_IABR_ACTIVE

#define NVIC_IABR_ACTIVE_0

#define NVIC_IABR_ACTIVE_1

#define NVIC_IABR_ACTIVE_2

#define NVIC_IABR_ACTIVE_3

#define NVIC_IABR_ACTIVE_4

#define NVIC_IABR_ACTIVE_5

#define NVIC_IABR_ACTIVE_6

#define NVIC_IABR_ACTIVE_7

#define NVIC_IABR_ACTIVE_8

#define NVIC_IABR_ACTIVE_9

#define NVIC_IABR_ACTIVE_10

#define NVIC_IABR_ACTIVE_11

#define NVIC_IABR_ACTIVE_12

#define NVIC_IABR_ACTIVE_13

#define NVIC_IABR_ACTIVE_14

#define NVIC_IABR_ACTIVE_15

#define NVIC_IABR_ACTIVE_16

#define NVIC_IABR_ACTIVE_17

#define NVIC_IABR_ACTIVE_18

#define NVIC_IABR_ACTIVE_19

#define NVIC_IABR_ACTIVE_20

#define NVIC_IABR_ACTIVE_21

#define NVIC_IABR_ACTIVE_22

#define NVIC_IABR_ACTIVE_23

#define NVIC_IABR_ACTIVE_24

#define NVIC_IABR_ACTIVE_25

#define NVIC_IABR_ACTIVE_26

#define NVIC_IABR_ACTIVE_27

#define NVIC_IABR_ACTIVE_28

#define NVIC_IABR_ACTIVE_29

#define NVIC_IABR_ACTIVE_30

#define NVIC_IABR_ACTIVE_31

#define NVIC_IPR0_PRI_0

#define NVIC_IPR0_PRI_1

#define NVIC_IPR0_PRI_2

#define NVIC_IPR0_PRI_3

#define NVIC_IPR1_PRI_4

#define NVIC_IPR1_PRI_5

#define NVIC_IPR1_PRI_6

#define NVIC_IPR1_PRI_7

#define NVIC_IPR2_PRI_8

#define NVIC_IPR2_PRI_9

#define NVIC_IPR2_PRI_10

#define NVIC_IPR2_PRI_11

#define NVIC_IPR3_PRI_12

#define NVIC_IPR3_PRI_13

#define NVIC_IPR3_PRI_14

#define NVIC_IPR3_PRI_15

#define NVIC_IPR4_PRI_16

#define NVIC_IPR4_PRI_17

#define NVIC_IPR4_PRI_18

#define NVIC_IPR4_PRI_19

#define NVIC_IPR5_PRI_20

#define NVIC_IPR5_PRI_21

#define NVIC_IPR5_PRI_22

#define NVIC_IPR5_PRI_23

#define NVIC_IPR6_PRI_24

#define NVIC_IPR6_PRI_25

#define NVIC_IPR6_PRI_26

#define NVIC_IPR6_PRI_27

#define NVIC_IPR7_PRI_28

#define NVIC_IPR7_PRI_29

#define NVIC_IPR7_PRI_30

#define NVIC_IPR7_PRI_31

#define SCB_CPUID_REVISION

#define SCB_CPUID_PARTNO

#define SCB_CPUID_Constant

#define SCB_CPUID_VARIANT

#define SCB_CPUID_IMPLEMENTER

#define SCB_ICSR_VECTACTIVE

#define SCB_ICSR_RETTOBASE

#define SCB_ICSR_VECTPENDING

#define SCB_ICSR_ISRPENDING

#define SCB_ICSR_ISRPREEMPT

#define SCB_ICSR_PENDSTCLR

#define SCB_ICSR_PENDSTSET

#define SCB_ICSR_PENDSVCLR

#define SCB_ICSR_PENDSVSET

#define SCB_ICSR_NMIPENDSET

#define SCB_VTOR_TBLOFF

#define SCB_VTOR_TBLBASE

#define SCB_AIRCR_VECTRESET

#define SCB_AIRCR_VECTCLRACTIVE

#define SCB_AIRCR_SYSRESETREQ

#define SCB_AIRCR_PRIGROUP

#define SCB_AIRCR_PRIGROUP_0

#define SCB_AIRCR_PRIGROUP_1

#define SCB_AIRCR_PRIGROUP_2

#define SCB_AIRCR_PRIGROUP0

#define SCB_AIRCR_PRIGROUP1

#define SCB_AIRCR_PRIGROUP2

#define SCB_AIRCR_PRIGROUP3

#define SCB_AIRCR_PRIGROUP4

#define SCB_AIRCR_PRIGROUP5

#define SCB_AIRCR_PRIGROUP6

#define SCB_AIRCR_PRIGROUP7

#define SCB_AIRCR_ENDIANESS

#define SCB_AIRCR_VECTKEY

#define SCB_SCR_SLEEPONEXIT

#define SCB_SCR_SLEEPDEEP

#define SCB_SCR_SEVONPEND

#define SCB_CCR_NONBASETHRDENA

#define SCB_CCR_USERSETMPEND

#define SCB_CCR_UNALIGN_TRP

#define SCB_CCR_DIV_0_TRP

#define SCB_CCR_BFHFNMIGN

#define SCB_CCR_STKALIGN

#define SCB_SHPR_PRI_N

#define SCB_SHPR_PRI_N1

#define SCB_SHPR_PRI_N2

#define SCB_SHPR_PRI_N3

#define SCB_SHCSR_MEMFAULTACT

#define SCB_SHCSR_BUSFAULTACT

#define SCB_SHCSR_USGFAULTACT

#define SCB_SHCSR_SVCALLACT

#define SCB_SHCSR_MONITORACT

#define SCB_SHCSR_PENDSVACT

#define SCB_SHCSR_SYSTICKACT

#define SCB_SHCSR_USGFAULTPENDED

#define SCB_SHCSR_MEMFAULTPENDED

#define SCB_SHCSR_BUSFAULTPENDED

#define SCB_SHCSR_SVCALLPENDED

#define SCB_SHCSR_MEMFAULTENA

#define SCB_SHCSR_BUSFAULTENA

#define SCB_SHCSR_USGFAULTENA

#define SCB_CFSR_IACCVIOL

#define SCB_CFSR_DACCVIOL

#define SCB_CFSR_MUNSTKERR

#define SCB_CFSR_MSTKERR

#define SCB_CFSR_MMARVALID

#define SCB_CFSR_IBUSERR

#define SCB_CFSR_PRECISERR

#define SCB_CFSR_IMPRECISERR

#define SCB_CFSR_UNSTKERR

#define SCB_CFSR_STKERR

#define SCB_CFSR_BFARVALID

#define SCB_CFSR_UNDEFINSTR

#define SCB_CFSR_INVSTATE

#define SCB_CFSR_INVPC

#define SCB_CFSR_NOCP

#define SCB_CFSR_UNALIGNED

#define SCB_CFSR_DIVBYZERO

#define SCB_HFSR_VECTTBL

#define SCB_HFSR_FORCED

#define SCB_HFSR_DEBUGEVT

#define SCB_DFSR_HALTED

#define SCB_DFSR_BKPT

#define SCB_DFSR_DWTTRAP

#define SCB_DFSR_VCATCH

#define SCB_DFSR_EXTERNAL

#define SCB_MMFAR_ADDRESS

#define SCB_BFAR_ADDRESS

#define SCB_AFSR_IMPDEF

@addtogroup Exported_macro * @{

#define SET_BIT( REG, BIT )

#define CLEAR_BIT( REG, BIT )

#define READ_BIT( REG, BIT )

#define CLEAR_REG( REG )

#define WRITE_REG( REG, VAL )

#define READ_REG( REG )

#define MODIFY_REG( REG, CLEARMASK, SETMASK )

Typedef IRQn_Type

typedef enum IRQn IRQn_Type
enum IRQn  
   {  
      NonMaskableInt_IRQn;  
      MemoryManagement_IRQn;  
      BusFault_IRQn;  
      UsageFault_IRQn;  
      SVC_IRQn;  
      DebugMonitor_IRQn;  
      PendSV_IRQn;  
      SysTick_IRQn;  
      WWDG_IRQn;  
      PVD_IRQn;  
      TAMPER_STAMP_IRQn;  
      RTC_WKUP_IRQn;  
      FLASH_IRQn;  
      RCC_IRQn;  
      EXTI0_IRQn;  
      EXTI1_IRQn;  
      EXTI2_IRQn;  
      EXTI3_IRQn;  
      EXTI4_IRQn;  
      DMA1_Channel1_IRQn;  
      DMA1_Channel2_IRQn;  
      DMA1_Channel3_IRQn;  
      DMA1_Channel4_IRQn;  
      DMA1_Channel5_IRQn;  
      DMA1_Channel6_IRQn;  
      DMA1_Channel7_IRQn;  
      ADC1_IRQn;  
      USB_HP_IRQn;  
      USB_LP_IRQn;  
      DAC_IRQn;  
      COMP_IRQn;  
      EXTI9_5_IRQn;  
      LCD_IRQn;  
      TIM9_IRQn;  
      TIM10_IRQn;  
      TIM11_IRQn;  
      TIM2_IRQn;  
      TIM3_IRQn;  
      TIM4_IRQn;  
      I2C1_EV_IRQn;  
      I2C1_ER_IRQn;  
      I2C2_EV_IRQn;  
      I2C2_ER_IRQn;  
      SPI1_IRQn;  
      SPI2_IRQn;  
      USART1_IRQn;  
      USART2_IRQn;  
      USART3_IRQn;  
      EXTI15_10_IRQn;  
      RTC_Alarm_IRQn;  
      USB_FS_WKUP_IRQn;  
      TIM6_IRQn;  
      TIM7_IRQn;  
      SDIO_IRQn;  
      TIM5_IRQn;  
      SPI3_IRQn;  
      UART4_IRQn;  
      UART5_IRQn;  
      DMA2_Channel1_IRQn;  
      DMA2_Channel2_IRQn;  
      DMA2_Channel3_IRQn;  
      DMA2_Channel4_IRQn;  
      DMA2_Channel5_IRQn;  
      AES_IRQn;  
      COMP_ACQ_IRQn;  
      IRQn_MAX;  
   }  

Typedef FlagStatus

@addtogroup Exported_types * @{

typedef enum {...} FlagStatus

enum  
   {  
      RESET;  
      SET;  
   }  

Typedef ITStatus

@addtogroup Exported_types * @{

typedef enum {...} ITStatus

See: Typedef FlagStatus

Typedef FunctionalState

typedef enum {...} FunctionalState
enum  
   {  
      DISABLE;  
      ENABLE;  
   }  

Typedef ErrorStatus

typedef enum {...} ErrorStatus
enum  
   {  
      ERROR;  
      SUCCESS;  
   }  

Typedef ADC_TypeDef

* @brief Analog to Digital Converter

typedef struct {...} ADC_TypeDef

struct  
   {  
      volatile uint32_t SR;  
      volatile uint32_t CR1;  
      volatile uint32_t CR2;  
      volatile uint32_t SMPR1;  
      volatile uint32_t SMPR2;  
      volatile uint32_t SMPR3;  
      volatile uint32_t JOFR1;  
      volatile uint32_t JOFR2;  
      volatile uint32_t JOFR3;  
      volatile uint32_t JOFR4;  
      volatile uint32_t HTR;  
      volatile uint32_t LTR;  
      volatile uint32_t SQR1;  
      volatile uint32_t SQR2;  
      volatile uint32_t SQR3;  
      volatile uint32_t SQR4;  
      volatile uint32_t SQR5;  
      volatile uint32_t JSQR;  
      volatile uint32_t JDR1;  
      volatile uint32_t JDR2;  
      volatile uint32_t JDR3;  
      volatile uint32_t JDR4;  
      volatile uint32_t DR;  
      volatile uint32_t SMPR0;  
   }  

Typedef ADC_Common_TypeDef

typedef struct {...} ADC_Common_TypeDef
struct  
   {  
      volatile uint32_t CSR;  
      volatile uint32_t CCR;  
   }  

Typedef AES_TypeDef

* @brief AES hardware accelerator

typedef struct {...} AES_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t SR;  
      volatile uint32_t DINR;  
      volatile uint32_t DOUTR;  
      volatile uint32_t KEYR0;  
      volatile uint32_t KEYR1;  
      volatile uint32_t KEYR2;  
      volatile uint32_t KEYR3;  
      volatile uint32_t IVR0;  
      volatile uint32_t IVR1;  
      volatile uint32_t IVR2;  
      volatile uint32_t IVR3;  
   }  

Typedef COMP_TypeDef

* @brief Comparator

typedef struct {...} COMP_TypeDef

struct  
   {  
      volatile uint32_t CSR;  
   }  

Typedef CRC_TypeDef

* @brief CRC calculation unit

typedef struct {...} CRC_TypeDef

struct  
   {  
      volatile uint32_t DR;  
      volatile uint8_t IDR;  
      uint8_t RESERVED0;  
      uint16_t RESERVED1;  
      volatile uint32_t CR;  
   }  

Typedef DAC_TypeDef

* @brief Digital to Analog Converter

typedef struct {...} DAC_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t SWTRIGR;  
      volatile uint32_t DHR12R1;  
      volatile uint32_t DHR12L1;  
      volatile uint32_t DHR8R1;  
      volatile uint32_t DHR12R2;  
      volatile uint32_t DHR12L2;  
      volatile uint32_t DHR8R2;  
      volatile uint32_t DHR12RD;  
      volatile uint32_t DHR12LD;  
      volatile uint32_t DHR8RD;  
      volatile uint32_t DOR1;  
      volatile uint32_t DOR2;  
      volatile uint32_t SR;  
   }  

Typedef DBGMCU_TypeDef

* @brief Debug MCU

typedef struct {...} DBGMCU_TypeDef

struct  
   {  
      volatile uint32_t IDCODE;  
      volatile uint32_t CR;  
      volatile uint32_t APB1FZ;  
      volatile uint32_t APB2FZ;  
   }  

Typedef DMA_Channel_TypeDef

* @brief DMA Controller

typedef struct {...} DMA_Channel_TypeDef

struct  
   {  
      volatile uint32_t CCR;  
      volatile uint32_t CNDTR;  
      volatile uint32_t CPAR;  
      volatile uint32_t CMAR;  
   }  

Typedef DMA_TypeDef

typedef struct {...} DMA_TypeDef
struct  
   {  
      volatile uint32_t ISR;  
      volatile uint32_t IFCR;  
   }  

Typedef EXTI_TypeDef

* @brief External Interrupt/Event Controller

typedef struct {...} EXTI_TypeDef

struct  
   {  
      volatile uint32_t IMR;  
      volatile uint32_t EMR;  
      volatile uint32_t RTSR;  
      volatile uint32_t FTSR;  
      volatile uint32_t SWIER;  
      volatile uint32_t PR;  
   }  

Typedef FLASH_TypeDef

* @brief FLASH Registers

typedef struct {...} FLASH_TypeDef

struct  
   {  
      volatile uint32_t ACR;  
      volatile uint32_t PECR;  
      volatile uint32_t PDKEYR;  
      volatile uint32_t PEKEYR;  
      volatile uint32_t PRGKEYR;  
      volatile uint32_t OPTKEYR;  
      volatile uint32_t SR;  
      volatile uint32_t OBR;  
      volatile uint32_t WRPR;  
      uint32_t RESERVED[23];  
      volatile uint32_t WRPR1;  
      volatile uint32_t WRPR2;  
   }  

Typedef OB_TypeDef

* @brief Option Bytes Registers

typedef struct {...} OB_TypeDef

struct  
   {  
      volatile uint32_t RDP;  
      volatile uint32_t USER;  
      volatile uint32_t WRP01;  
      volatile uint32_t WRP23;  
      volatile uint32_t WRP45;  
      volatile uint32_t WRP67;  
      volatile uint32_t WRP89;  
      volatile uint32_t WRP1011;  
   }  

Typedef OPAMP_TypeDef

* @brief Operational Amplifier (OPAMP)

typedef struct {...} OPAMP_TypeDef

struct  
   {  
      volatile uint32_t CSR;  
      volatile uint32_t OTR;  
      volatile uint32_t LPOTR;  
   }  

Typedef FSMC_Bank1_TypeDef

* @brief Flexible Static Memory Controller

typedef struct {...} FSMC_Bank1_TypeDef

struct  
   {  
      volatile uint32_t BTCR[8];  
   }  

Typedef FSMC_Bank1E_TypeDef

* @brief Flexible Static Memory Controller Bank1E

typedef struct {...} FSMC_Bank1E_TypeDef

struct  
   {  
      volatile uint32_t BWTR[7];  
   }  

Typedef GPIO_TypeDef

* @brief General Purpose IO

typedef struct {...} GPIO_TypeDef

struct  
   {  
      volatile uint32_t MODER;  
      volatile uint16_t OTYPER;  
      uint16_t RESERVED0;  
      volatile uint32_t OSPEEDR;  
      volatile uint32_t PUPDR;  
      volatile uint16_t IDR;  
      uint16_t RESERVED1;  
      volatile uint16_t ODR;  
      uint16_t RESERVED2;  
      volatile uint16_t BSRRL;  
      volatile uint16_t BSRRH;  
      volatile uint32_t LCKR;  
      volatile uint32_t AFR[2];  
      volatile uint16_t BRR;  
      uint16_t RESERVED3;  
   }  

Typedef SYSCFG_TypeDef

* @brief SysTem Configuration

typedef struct {...} SYSCFG_TypeDef

struct  
   {  
      volatile uint32_t MEMRMP;  
      volatile uint32_t PMC;  
      volatile uint32_t EXTICR[4];  
   }  

Typedef I2C_TypeDef

* @brief Inter-integrated Circuit Interface

typedef struct {...} I2C_TypeDef

struct  
   {  
      volatile uint16_t CR1;  
      uint16_t RESERVED0;  
      volatile uint16_t CR2;  
      uint16_t RESERVED1;  
      volatile uint16_t OAR1;  
      uint16_t RESERVED2;  
      volatile uint16_t OAR2;  
      uint16_t RESERVED3;  
      volatile uint16_t DR;  
      uint16_t RESERVED4;  
      volatile uint16_t SR1;  
      uint16_t RESERVED5;  
      volatile uint16_t SR2;  
      uint16_t RESERVED6;  
      volatile uint16_t CCR;  
      uint16_t RESERVED7;  
      volatile uint16_t TRISE;  
      uint16_t RESERVED8;  
   }  

Typedef IWDG_TypeDef

* @brief Independent WATCHDOG

typedef struct {...} IWDG_TypeDef

struct  
   {  
      volatile uint32_t KR;  
      volatile uint32_t PR;  
      volatile uint32_t RLR;  
      volatile uint32_t SR;  
   }  

Typedef LCD_TypeDef

* @brief LCD

typedef struct {...} LCD_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t FCR;  
      volatile uint32_t SR;  
      volatile uint32_t CLR;  
      uint32_t RESERVED;  
      volatile uint32_t RAM[16];  
   }  

Typedef PWR_TypeDef

* @brief Power Control

typedef struct {...} PWR_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t CSR;  
   }  

Typedef RCC_TypeDef

* @brief Reset and Clock Control

typedef struct {...} RCC_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t ICSCR;  
      volatile uint32_t CFGR;  
      volatile uint32_t CIR;  
      volatile uint32_t AHBRSTR;  
      volatile uint32_t APB2RSTR;  
      volatile uint32_t APB1RSTR;  
      volatile uint32_t AHBENR;  
      volatile uint32_t APB2ENR;  
      volatile uint32_t APB1ENR;  
      volatile uint32_t AHBLPENR;  
      volatile uint32_t APB2LPENR;  
      volatile uint32_t APB1LPENR;  
      volatile uint32_t CSR;  
   }  

Typedef RI_TypeDef

* @brief Routing Interface

typedef struct {...} RI_TypeDef

struct  
   {  
      volatile uint32_t ICR;  
      volatile uint32_t ASCR1;  
      volatile uint32_t ASCR2;  
      volatile uint32_t HYSCR1;  
      volatile uint32_t HYSCR2;  
      volatile uint32_t HYSCR3;  
      volatile uint32_t HYSCR4;  
   }  

Typedef RTC_TypeDef

* @brief Real-Time Clock

typedef struct {...} RTC_TypeDef

struct  
   {  
      volatile uint32_t TR;  
      volatile uint32_t DR;  
      volatile uint32_t CR;  
      volatile uint32_t ISR;  
      volatile uint32_t PRER;  
      volatile uint32_t WUTR;  
      volatile uint32_t CALIBR;  
      volatile uint32_t ALRMAR;  
      volatile uint32_t ALRMBR;  
      volatile uint32_t WPR;  
      volatile uint32_t SSR;  
      volatile uint32_t SHIFTR;  
      volatile uint32_t TSTR;  
      volatile uint32_t TSDR;  
      volatile uint32_t TSSSR;  
      volatile uint32_t CALR;  
      volatile uint32_t TAFCR;  
      volatile uint32_t ALRMASSR;  
      volatile uint32_t ALRMBSSR;  
      uint32_t RESERVED7;  
      volatile uint32_t BKP0R;  
      volatile uint32_t BKP1R;  
      volatile uint32_t BKP2R;  
      volatile uint32_t BKP3R;  
      volatile uint32_t BKP4R;  
      volatile uint32_t BKP5R;  
      volatile uint32_t BKP6R;  
      volatile uint32_t BKP7R;  
      volatile uint32_t BKP8R;  
      volatile uint32_t BKP9R;  
      volatile uint32_t BKP10R;  
      volatile uint32_t BKP11R;  
      volatile uint32_t BKP12R;  
      volatile uint32_t BKP13R;  
      volatile uint32_t BKP14R;  
      volatile uint32_t BKP15R;  
      volatile uint32_t BKP16R;  
      volatile uint32_t BKP17R;  
      volatile uint32_t BKP18R;  
      volatile uint32_t BKP19R;  
      volatile uint32_t BKP20R;  
      volatile uint32_t BKP21R;  
      volatile uint32_t BKP22R;  
      volatile uint32_t BKP23R;  
      volatile uint32_t BKP24R;  
      volatile uint32_t BKP25R;  
      volatile uint32_t BKP26R;  
      volatile uint32_t BKP27R;  
      volatile uint32_t BKP28R;  
      volatile uint32_t BKP29R;  
      volatile uint32_t BKP30R;  
      volatile uint32_t BKP31R;  
   }  

Typedef SDIO_TypeDef

* @brief SD host Interface

typedef struct {...} SDIO_TypeDef

struct  
   {  
      volatile uint32_t POWER;  
      volatile uint32_t CLKCR;  
      volatile uint32_t ARG;  
      volatile uint32_t CMD;  
      volatile const uint32_t RESPCMD;  
      volatile const uint32_t RESP1;  
      volatile const uint32_t RESP2;  
      volatile const uint32_t RESP3;  
      volatile const uint32_t RESP4;  
      volatile uint32_t DTIMER;  
      volatile uint32_t DLEN;  
      volatile uint32_t DCTRL;  
      volatile const uint32_t DCOUNT;  
      volatile const uint32_t STA;  
      volatile uint32_t ICR;  
      volatile uint32_t MASK;  
      uint32_t RESERVED0[2];  
      volatile const uint32_t FIFOCNT;  
      uint32_t RESERVED1[13];  
      volatile uint32_t FIFO;  
   }  

Typedef SPI_TypeDef

* @brief Serial Peripheral Interface

typedef struct {...} SPI_TypeDef

struct  
   {  
      volatile uint16_t CR1;  
      uint16_t RESERVED0;  
      volatile uint16_t CR2;  
      uint16_t RESERVED1;  
      volatile uint16_t SR;  
      uint16_t RESERVED2;  
      volatile uint16_t DR;  
      uint16_t RESERVED3;  
      volatile uint16_t CRCPR;  
      uint16_t RESERVED4;  
      volatile uint16_t RXCRCR;  
      uint16_t RESERVED5;  
      volatile uint16_t TXCRCR;  
      uint16_t RESERVED6;  
      volatile uint16_t I2SCFGR;  
      uint16_t RESERVED7;  
      volatile uint16_t I2SPR;  
      uint16_t RESERVED8;  
   }  

Typedef TIM_TypeDef

* @brief TIM

typedef struct {...} TIM_TypeDef

struct  
   {  
      volatile uint16_t CR1;  
      uint16_t RESERVED0;  
      volatile uint16_t CR2;  
      uint16_t RESERVED1;  
      volatile uint16_t SMCR;  
      uint16_t RESERVED2;  
      volatile uint16_t DIER;  
      uint16_t RESERVED3;  
      volatile uint16_t SR;  
      uint16_t RESERVED4;  
      volatile uint16_t EGR;  
      uint16_t RESERVED5;  
      volatile uint16_t CCMR1;  
      uint16_t RESERVED6;  
      volatile uint16_t CCMR2;  
      uint16_t RESERVED7;  
      volatile uint16_t CCER;  
      uint16_t RESERVED8;  
      volatile uint32_t CNT;  
      volatile uint16_t PSC;  
      uint16_t RESERVED10;  
      volatile uint32_t ARR;  
      uint32_t RESERVED12;  
      volatile uint32_t CCR1;  
      volatile uint32_t CCR2;  
      volatile uint32_t CCR3;  
      volatile uint32_t CCR4;  
      uint32_t RESERVED17;  
      volatile uint16_t DCR;  
      uint16_t RESERVED18;  
      volatile uint16_t DMAR;  
      uint16_t RESERVED19;  
      volatile uint16_t OR;  
      uint16_t RESERVED20;  
   }  

Typedef USART_TypeDef

* @brief Universal Synchronous Asynchronous Receiver Transmitter

typedef struct {...} USART_TypeDef

struct  
   {  
      volatile uint16_t SR;  
      uint16_t RESERVED0;  
      volatile uint16_t DR;  
      uint16_t RESERVED1;  
      volatile uint16_t BRR;  
      uint16_t RESERVED2;  
      volatile uint16_t CR1;  
      uint16_t RESERVED3;  
      volatile uint16_t CR2;  
      uint16_t RESERVED4;  
      volatile uint16_t CR3;  
      uint16_t RESERVED5;  
      volatile uint16_t GTPR;  
      uint16_t RESERVED6;  
   }  

Typedef WWDG_TypeDef

* @brief Window WATCHDOG

typedef struct {...} WWDG_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t CFR;  
      volatile uint32_t SR;  
   }