File nut/include/arch/arm/atmel/at91_ssc.h


Preprocessor definitions

#define _ARCH_ARM_AT91_SSC_H_

#define SSC_CR_OFF 0x00000000

#define SSC_CR

#define SSC_RXEN 0x00000001

#define SSC_RXDIS 0x00000002

#define SSC_TXEN 0x00000100

#define SSC_TXDIS 0x00000200

#define SSC_SWRST 0x00008000

#define SSC_CMR_OFF 0x00000004

#define SSC_CMR

#define SSC_DIV_LSB 0

#define SSC_DIV 0x00000FFF

#define SSC_RCMR_OFF 0x00000010

#define SSC_RCMR

#define SSC_TCMR_OFF 0x00000018

#define SSC_TCMR

#define SSC_CKS 0x00000003

#define SSC_CKS_DIV 0x00000000

#define SSC_CKS_CLK 0x00000001

#define SSC_CKS_PIN 0x00000002

#define SSC_CKO 0x0000001C

#define SSC_CKO_NONE 0x00000000

#define SSC_CKO_CONT 0x00000004

#define SSC_CKO_TRAN 0x00000008

#define SSC_CKI 0x00000020

#define SSC_CKG 0x000000C0

#define SSC_CKG_NONE 0x00000000

#define SSC_CKG_RFL 0x00000040

#define SSC_CKG_RFH 0x00000080

#define SSC_START 0x00000F00

#define SSC_START_CONT 0x00000000

#define SSC_START_TX 0x00000100

#define SSC_START_LOW_RF 0x00000200

#define SSC_START_HIGH_RF 0x00000300

#define SSC_START_FALL_RF 0x00000400

#define SSC_START_RISE_RF 0x00000500

#define SSC_START_LEVEL_RF 0x00000600

#define SSC_START_EDGE_RF 0x00000700

#define SSC_START_COMP0 0x00000800

#define SSC_STOP 0x00001000

#define SSC_STTDLY 0x00FF0000

#define SSC_STTDLY_LSB 16

#define SSC_PERIOD 0xFF000000

#define SSC_PERIOD_LSB 24

#define SSC_RFMR_OFF 0x00000014

#define SSC_RFMR

#define SSC_TFMR_OFF 0x0000001C

#define SSC_TFMR

#define SSC_DATLEN 0x0000001F

#define SSC_DATLEN_LSB 0

#define SSC_LOOP 0x00000020

#define SSC_DATDEF 0x00000020

#define SSC_MSBF 0x00000080

#define SSC_DATNB 0x00000F00

#define SSC_DATNB_LSB 8

#define SSC_FSLEN 0x000F0000

#define SSC_FSLEN_LSB 16

#define SSC_FSOS 0x00700000

#define SSC_FSOS_NONE 0x00000000

#define SSC_FSOS_NEGATIVE 0x00100000

#define SSC_FSOS_POSITIVE 0x00200000

#define SSC_FSOS_LOW 0x00300000

#define SSC_FSOS_HIGH 0x00400000

#define SSC_FSOS_TOGGLE 0x00500000

#define SSC_FSDEN 0x00800000

#define SSC_FSEDGE 0x01000000

#define SSC_RHR_OFF 0x00000020

#define SSC_RHR

#define SSC_THR_OFF 0x00000024

#define SSC_THR

#define SSC_RSHR_OFF 0x00000030

#define SSC_RSHR

#define SSC_TSHR_OFF 0x00000034

#define SSC_TSHR

#define SSC_RC0R_OFF 0x00000038

#define SSC_RC0R

#define SSC_RC1R_OFF 0x0000003C

#define SSC_RC1R

#define SSC_SR_OFF 0x00000040

#define SSC_SR

#define SSC_TXRDY 0x00000001

#define SSC_TXEMPTY 0x00000002

#define SSC_ENDTX 0x00000004

#define SSC_TXBUFE 0x00000008

#define SSC_RXRDY 0x00000010

#define SSC_OVRUN 0x00000020

#define SSC_ENDRX 0x00000040

#define SSC_RXBUFF 0x00000080

#define SSC_CP0 0x00000100

#define SSC_CP1 0x00000200

#define SSC_TXSYN 0x00000400

#define SSC_RXSYN 0x00000800

#define SSC_TXENA 0x00010000

#define SSC_RXENA 0x00020000

#define SSC_IER_OFF 0x00000044

#define SSC_IER

#define SSC_IDR_OFF 0x00000048

#define SSC_IDR

#define SSC_IMR_OFF 0x0000004C

#define SSC_IMR