#define FLASH_BASE 0x100000UL
#define RAM_BASE 0x200000UL
#define NAND_FLASH_BASE 0x40000000
#define LCDC_BASE 0x00500000
#define UDP_BASE 0xFFF78000
#define TC_BASE 0xFFF7C000
#define MCI_BASE 0xFFF80000
#define TWI_BASE 0xFFF84000
#define USART0_BASE 0xFFF8C000
#define USART1_BASE 0xFFF90000
#define USART2_BASE 0xFFF94000
#define USART3_BASE 0xFFF98000
#define SSC_BASE 0xFFF9C000
#define SPI0_BASE 0xFFFA4000
#define SPI1_BASE 0xFFFA8000
#define AC97_BASE 0xFFFAC000
#define TSADCC_BASE 0xFFFB0000
#define ISI_BASE 0xFFFB4000
#define PWMC_BASE 0xFFFB8000
#define EMAC_BASE 0xFFFBC000
#define TRNG_BASE 0xFFFCC000
#define MCI1_BASE 0xFFFD0000
#define TC345_BASE 0xFFFD4000
#define DDRSDRC1_BASE 0xFFFFE400
#define DDRSDRC0_BASE 0xFFFFE600
#define SMC_BASE 0xFFFFE800
#define MATRIX_BASE 0xFFFFEA00
#define CCFG_BASE 0xFFFFEB10
#define DMAC_BASE 0xFFFFEC00
#define DBGU_BASE 0xFFFFEE00
#define AIC_BASE 0xFFFFF000
#define PIOA_BASE 0xFFFFF200
#define PIOB_BASE 0xFFFFF400
#define PIOC_BASE 0xFFFFF600
#define PIOD_BASE 0xFFFFF800
#define PIOE_BASE 0xFFFFFA00
#define PMC_BASE 0xFFFFFC00
#define RSTC_BASE 0xFFFFFD00
#define SHDWC_BASE 0xFFFFFD10
#define RTT_BASE 0xFFFFFD20
#define PIT_BASE 0xFFFFFD30
#define WDT_BASE 0xFFFFFD40
#define SCKCR_BASE 0xFFFFFD50
#define GPBR_BASE 0xFFFFFD60
#define RTC_BASE 0xFFFFFDB0
#define ECC_BASE 0xFFFFE200
#define PERIPH_RPR_OFF 0x00000100
#define PERIPH_RCR_OFF 0x00000104
#define PERIPH_TPR_OFF 0x00000108
#define PERIPH_TCR_OFF 0x0000010C
#define PERIPH_RNPR_OFF 0x00000110
#define PERIPH_RNCR_OFF 0x00000114
#define PERIPH_TNPR_OFF 0x00000118
#define PERIPH_TNCR_OFF 0x0000011C
#define PERIPH_PTCR_OFF 0x00000120
#define PERIPH_PTSR_OFF 0x00000124
#define PDC_RXTEN 0x00000001
#define PDC_RXTDIS 0x00000002
#define PDC_TXTEN 0x00000100
#define PDC_TXTDIS 0x00000200
#define DBGU_HAS_PDC
#define SPI_HAS_PDC
#define SSC_HAS_PDC
#define USART_HAS_PDC
#define USART_HAS_MODE
#define MCI_HAS_PDC
#define PMC_HAS_PLLB
#define PMC_HAS_MDIV
#define EBI_HAS_CSA
#define PIO_HAS_MULTIDRIVER
#define PIO_HAS_PULLUP
#define PIO_HAS_PERIPHERALSELECT
#define PIO_HAS_OUTPUTWRITEENABLE
#define FIQ_ID 0
#define SYSC_ID 1
#define PIOA_ID 2
#define PIOB_ID 3
#define PIOC_ID 4
#define PIODE_ID 5
#define TRNG_ID 6
#define US0_ID 7
#define US1_ID 8
#define US2_ID 9
#define US3_ID 10
#define MCI0_ID 11
#define TWI0_ID 12
#define TWI1_ID 13
#define SPI0_ID 14
#define SPI1_ID 15
#define SSC0_ID 16
#define SSC1_ID 17
#define TC0_ID 18
#define TC1_ID 18
#define TC2_ID 18
#define TC3_ID 18
#define TC4_ID 18
#define TC5_ID 18
#define PWMC_ID 19
#define TSADCC_ID 20
#define DMA_ID 21
#define UHPHS_ID 22
#define LCDC_ID 23
#define AC97C_ID 24
#define EMAC_ID 25
#define ISI_ID 26
#define UDPHS_ID 27
#define MCI1_ID 29
#define IRQ0_ID 31
#define TWI_ID TWI0_ID
#define MCI_ID MCI0_ID
#define SSC_ID SSC0_ID
#define PB16_SCK0_B 16
#define PB19_TXD0_A 19
#define PB18_RXD0_A 18
#define PB15_CTS0_B 15
#define PB17_RTS0_B 17
#define PD29_SCK1_B 29
#define PB4_TXD1_A 4
#define PB5_RXD1_A 5
#define PD17_CTS1_A 17
#define PD16_RTS1_A 16
#define PD30_SCK2_B 30
#define PB6_TXD2_A 6
#define PB7_RXD2_A 7
#define PC11_CTS2_B 11
#define PC9_RTS2_B 9
#define PA22_SCK3_B 22
#define PB8_TXD3_A 8
#define PB9_RXD3_A 9
#define PA24_CTS3_B 24
#define PA23_RTS3_B 23
#define PB0_SPI0_MISO_A 0
#define PB1_SPI0_MOSI_A 1
#define PB2_SPI0_SPCK_A 2
#define PB3_SPI0_NPCS0_A 3
#define PB18_SPI0_NPCS1_B 18
#define PD24_SPI0_NPCS1_A 24
#define PB19_SPI0_NPCS2_B 19
#define PD25_SPI0_NPCS2_A 25
#define PD27_SPI0_NPCS3_B 27
#define SPI0_PINS
#define SPI0_PIO_BASE PIOA_BASE
#define SPI0_PSR_OFF PIO_ASR_OFF
#define SPI0_CS0_PIN
#define SPI0_CS0_PIO_BASE PIOB_BASE
#define SPI0_CS0_PSR_OFF PIO_ASR_OFF
#define SPI0_CS1_PIN
#define SPI0_CS1_PIO_BASE PIOB_BASE
#define SPI0_CS1_PSR_OFF PIO_BSR_OFF
#define PB14_SPI1_MISO_A 14
#define PB15_SPI1_MOSI_A 15
#define PB16_SPI1_SPCK_A 16
#define PB17_SPI1_NPCS0_A 17
#define PD28_SPI1_NPCS1_B 28
#define PD18_SPI1_NPCS2_A 18
#define PD19_SPI1_NPCS3_A 19
#define SPI1_PINS
#define SPI1_PIO_BASE PIOB_BASE
#define SPI1_PSR_OFF PIO_ASR_OFF
#define SPI1_CS0_PIN
#define SPI1_CS0_PIO_BASE PIOB_BASE
#define SPI1_CS0_PSR_OFF PIO_ASR_OFF
#define SPI1_CS3_PIN
#define SPI1_CS3_PIO_BASE PIOD_BASE
#define SPI1_CS3_PSR_OFF PIO_ASR_OFF
#define PB20_ISI_D0_A 20
#define PB21_ISI_D1_A 21
#define PB22_ISI_D2_A 22
#define PB23_ISI_D3_A 23
#define PB24_ISI_D4_A 24
#define PB25_ISI_D5_A 25
#define PB26_ISI_D6_A 26
#define PB27_ISI_D7_A 27
#define PB10_ISI_D8_B 10
#define PB11_ISI_D9_B 11
#define PB12_ISI_D10_B 12
#define PB13_ISI_D11_B 13
#define PB28_ISI_PCK_A 28
#define PB29_ISI_VSYNC_A 29
#define PB30_ISI_HSYNC_A 30
#define PB31_ISI_MCK_A 31
#define PA6_ETX2_B 6
#define PA7_ETX3_B 7
#define PA10_ETX0_A 10
#define PA11_ETX1_A 11
#define PA12_ERX0_A 12
#define PA13_ERX1_A 13
#define PA14_ETXEN_A 14
#define PA15_ERXDV_A 15
#define PA16_ERXER_A 16
#define PA17_ETXCK_A 17
#define PA18_EMDC_A 18
#define PA19_EMDIO_A 19
#define PA27_ETXER_B 27
#define PA8_ERX2_B 8
#define PA9_ERX3_B 9
#define PA28_ERXCK_B 28
#define PA29_ECRS_B 29
#define PA30_ECOL_B 30
#define PHY_MODE_RMII
#define EMAC_PIO_ASR PIO_ASR_OFF
#define PHY_MII_PINS_A
#define EMAC_PIO_BSR PIO_BSR_OFF
#define PHY_MII_PINS_B
#define EMAC_PIO_PDR PIOA_PDR
#define PD28_ADTRG_A 28
#define PB12_DRXD_A 12
#define PB13_DTXD_A 13
#define PD2_TD0_A 2
#define PD3_RD0_A 3
#define PD0_TK0_A 0
#define PD4_RK0_A 4
#define PD1_TF0_A 1
#define PD5_RF0_A 5
#define PA20_TWD0_A 20
#define PA21_TWCK0_A 21
#define PB10_TWD1_A 10
#define PB11_TWCK1_A 11
#define PD23_TCLK0_A 23
#define PD20_TIOA0_A 20
#define PD30_TIOB0_A 30
#define PD29_TCLK1_A 29
#define PD21_TIOA1_A 21
#define PD31_TIOB1_A 31
#define PC10_TCLK2_B 10
#define PD22_TIOA2_A 22
#define PA26_TIOB2_B 26
#define PA0_TCLK3_B 0
#define PA1_TIOA3_B 1
#define PA2_TIOB3_B 2
#define PA3_TCLK4_B 3
#define PA4_TIOA4_B 4
#define PA5_TIOB4_B 5
#define PD9_TCLK5_B 9
#define PD7_TIOA5_B 7
#define PD8_TIOB5_B 8
#define PD26_PCK0_A 26
#define PE0_PCK0_B 0
#define PD27_PCK1_A 27
#define PE31_PCK1_B 31
#define PC12_A25_CFRNW_A 12
#define PC10_NCS4_CFCS0_A 10
#define PC11_NCS5_CFCS1_A 11
#define PC8_CFCE1_A 8
#define PC9_CFCE2_A 9
#define PC16_D16_A 16
#define PC17_D17_A 17
#define PC18_D18_A 18
#define PC19_D19_A 19
#define PC20_D20_A 20
#define PC21_D21_A 21
#define PC22_D22_A 22
#define PC23_D23_A 23
#define PC24_D24_A 24
#define PC25_D25_A 25
#define PC26_D26_A 26
#define PC27_D27_A 27
#define PC28_D28_A 28
#define PC29_D29_A 29
#define PC30_D30_A 30
#define PC31_D31_A 31
#define PC6_A23_A 6
#define PC7_A24_A 7
#define PC13_NCS2_A 13
#define PC14_NCS3_NANDCS_A 14
#define PC15_NWAIT_A 15
#define PD19_FIQ_B 19
#define PC18_IRQ_B 18
#define LCDC_PIO_BASE PIOE_BASE
#define LCDC_PINS_A 0x6FEFFFDE
#define LCDC_PINS_B 0x10100000
#define LCDC_PINS
#define LCDC_PIO_ASR PIOE_ASR
#define LCDC_PIO_BSR PIOE_BSR
#define LCDC_PIO_PDR PIOE_PDR