File nut/include/arch/cm3/stm/vendor/stm32f37x.h

Cortex-M4 Processor Exceptions Numbers

Included Files

* @}

Preprocessor definitions

@addtogroup stm32f37x * @{

#define __STM32F37x_H

@addtogroup Library_configuration_section * @{

#define STM32F37X

* @brief In the following line adjust the value of External High Speed oscillator (HSE) used in your application
Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor.

#define HSE_VALUE

* @brief In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value

#define HSE_STARTUP_TIMEOUT

* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup Timeout value

#define HSI_STARTUP_TIMEOUT

#define HSI_VALUE

#define LSI_VALUE

#define LSE_VALUE

* @brief STM32F37x Standard Peripherals Library version number V1.0.0

#define __STM32F37X_STDPERIPH_VERSION_MAIN 0x01

#define __STM32F37X_STDPERIPH_VERSION_SUB1 0x00

#define __STM32F37X_STDPERIPH_VERSION_SUB2 0x00

#define __STM32F37X_STDPERIPH_VERSION_RC 0x00

#define __STM32F37X_STDPERIPH_VERSION

* @brief Configuration of the Cortex-M4 Processor and Core Peripherals

#define __CM4_REV 0x0001

#define __MPU_PRESENT 1

#define __NVIC_PRIO_BITS 4

#define __Vendor_SysTickConfig 0

#define __FPU_PRESENT 1

#define IS_FUNCTIONAL_STATE( STATE )

@addtogroup Peripheral_memory_map * @{

#define FLASH_BASE

#define SRAM_BASE

#define PERIPH_BASE

#define SRAM_BB_BASE

#define PERIPH_BB_BASE

#define APB1PERIPH_BASE PERIPH_BASE

#define APB2PERIPH_BASE

#define AHB1PERIPH_BASE

#define AHB2PERIPH_BASE

#define TIM2_BASE

#define TIM3_BASE

#define TIM4_BASE

#define TIM5_BASE

#define TIM6_BASE

#define TIM7_BASE

#define TIM12_BASE

#define TIM13_BASE

#define TIM14_BASE

#define RTC_BASE

#define WWDG_BASE

#define IWDG_BASE

#define SPI2_BASE

#define SPI3_BASE

#define USART2_BASE

#define USART3_BASE

#define I2C1_BASE

#define I2C2_BASE

#define CAN1_BASE

#define PWR_BASE

#define DAC1_BASE

#define CEC_BASE

#define DAC2_BASE

#define TIM18_BASE

#define SYSCFG_BASE

#define COMP_BASE

#define EXTI_BASE

#define ADC1_BASE

#define SPI1_BASE

#define USART1_BASE

#define TIM15_BASE

#define TIM16_BASE

#define TIM17_BASE

#define TIM19_BASE

#define SDADC1_BASE

#define SDADC2_BASE

#define SDADC3_BASE

#define DMA1_BASE

#define DMA1_Channel1_BASE

#define DMA1_Channel2_BASE

#define DMA1_Channel3_BASE

#define DMA1_Channel4_BASE

#define DMA1_Channel5_BASE

#define DMA1_Channel6_BASE

#define DMA1_Channel7_BASE

#define DMA2_BASE

#define DMA2_Channel1_BASE

#define DMA2_Channel2_BASE

#define DMA2_Channel3_BASE

#define DMA2_Channel4_BASE

#define DMA2_Channel5_BASE

#define RCC_BASE

#define FLASH_R_BASE

#define OB_BASE

#define CRC_BASE

#define TSC_BASE

#define GPIOA_BASE

#define GPIOB_BASE

#define GPIOC_BASE

#define GPIOD_BASE

#define GPIOE_BASE

#define GPIOF_BASE

#define DBGMCU_BASE

@addtogroup Peripheral_declaration * @{

#define TIM2

#define TIM3

#define TIM4

#define TIM5

#define TIM6

#define TIM7

#define TIM12

#define TIM13

#define TIM14

#define RTC

#define WWDG

#define IWDG

#define SPI2

#define SPI3

#define USART2

#define USART3

#define I2C1

#define I2C2

#define CAN1

#define PWR

#define DAC1

#define DAC2

#define CEC

#define COMP

#define TIM18

#define SYSCFG

#define EXTI

#define ADC1

#define SPI1

#define USART1

#define TIM15

#define TIM16

#define TIM17

#define DBGMCU

#define TIM19

#define SDADC1

#define SDADC2

#define SDADC3

#define DMA1

#define DMA1_Channel1

#define DMA1_Channel2

#define DMA1_Channel3

#define DMA1_Channel4

#define DMA1_Channel5

#define DMA1_Channel6

#define DMA1_Channel7

#define DMA2

#define DMA2_Channel1

#define DMA2_Channel2

#define DMA2_Channel3

#define DMA2_Channel4

#define DMA2_Channel5

#define RCC

#define FLASH

#define OB

#define CRC

#define TSC

#define GPIOA

#define GPIOB

#define GPIOC

#define GPIOD

#define GPIOE

#define GPIOF

#define ADC_SR_AWD

#define ADC_SR_EOC

#define ADC_SR_JEOC

#define ADC_SR_JSTRT

#define ADC_SR_STRT

#define ADC_CR1_AWDCH

#define ADC_CR1_AWDCH_0

#define ADC_CR1_AWDCH_1

#define ADC_CR1_AWDCH_2

#define ADC_CR1_AWDCH_3

#define ADC_CR1_AWDCH_4

#define ADC_CR1_EOCIE

#define ADC_CR1_AWDIE

#define ADC_CR1_JEOCIE

#define ADC_CR1_SCAN

#define ADC_CR1_AWDSGL

#define ADC_CR1_JAUTO

#define ADC_CR1_DISCEN

#define ADC_CR1_JDISCEN

#define ADC_CR1_DISCNUM

#define ADC_CR1_DISCNUM_0

#define ADC_CR1_DISCNUM_1

#define ADC_CR1_DISCNUM_2

#define ADC_CR1_JAWDEN

#define ADC_CR1_AWDEN

#define ADC_CR2_ADON

#define ADC_CR2_CONT

#define ADC_CR2_CAL

#define ADC_CR2_RSTCAL

#define ADC_CR2_DMA

#define ADC_CR2_ALIGN

#define ADC_CR2_JEXTSEL

#define ADC_CR2_JEXTSEL_0

#define ADC_CR2_JEXTSEL_1

#define ADC_CR2_JEXTSEL_2

#define ADC_CR2_JEXTTRIG

#define ADC_CR2_EXTSEL

#define ADC_CR2_EXTSEL_0

#define ADC_CR2_EXTSEL_1

#define ADC_CR2_EXTSEL_2

#define ADC_CR2_EXTTRIG

#define ADC_CR2_JSWSTART

#define ADC_CR2_SWSTART

#define ADC_CR2_TSVREFE

#define ADC_SMPR1_SMP10

#define ADC_SMPR1_SMP10_0

#define ADC_SMPR1_SMP10_1

#define ADC_SMPR1_SMP10_2

#define ADC_SMPR1_SMP11

#define ADC_SMPR1_SMP11_0

#define ADC_SMPR1_SMP11_1

#define ADC_SMPR1_SMP11_2

#define ADC_SMPR1_SMP12

#define ADC_SMPR1_SMP12_0

#define ADC_SMPR1_SMP12_1

#define ADC_SMPR1_SMP12_2

#define ADC_SMPR1_SMP13

#define ADC_SMPR1_SMP13_0

#define ADC_SMPR1_SMP13_1

#define ADC_SMPR1_SMP13_2

#define ADC_SMPR1_SMP14

#define ADC_SMPR1_SMP14_0

#define ADC_SMPR1_SMP14_1

#define ADC_SMPR1_SMP14_2

#define ADC_SMPR1_SMP15

#define ADC_SMPR1_SMP15_0

#define ADC_SMPR1_SMP15_1

#define ADC_SMPR1_SMP15_2

#define ADC_SMPR1_SMP16

#define ADC_SMPR1_SMP16_0

#define ADC_SMPR1_SMP16_1

#define ADC_SMPR1_SMP16_2

#define ADC_SMPR1_SMP17

#define ADC_SMPR1_SMP17_0

#define ADC_SMPR1_SMP17_1

#define ADC_SMPR1_SMP17_2

#define ADC_SMPR2_SMP0

#define ADC_SMPR2_SMP0_0

#define ADC_SMPR2_SMP0_1

#define ADC_SMPR2_SMP0_2

#define ADC_SMPR2_SMP1

#define ADC_SMPR2_SMP1_0

#define ADC_SMPR2_SMP1_1

#define ADC_SMPR2_SMP1_2

#define ADC_SMPR2_SMP2

#define ADC_SMPR2_SMP2_0

#define ADC_SMPR2_SMP2_1

#define ADC_SMPR2_SMP2_2

#define ADC_SMPR2_SMP3

#define ADC_SMPR2_SMP3_0

#define ADC_SMPR2_SMP3_1

#define ADC_SMPR2_SMP3_2

#define ADC_SMPR2_SMP4

#define ADC_SMPR2_SMP4_0

#define ADC_SMPR2_SMP4_1

#define ADC_SMPR2_SMP4_2

#define ADC_SMPR2_SMP5

#define ADC_SMPR2_SMP5_0

#define ADC_SMPR2_SMP5_1

#define ADC_SMPR2_SMP5_2

#define ADC_SMPR2_SMP6

#define ADC_SMPR2_SMP6_0

#define ADC_SMPR2_SMP6_1

#define ADC_SMPR2_SMP6_2

#define ADC_SMPR2_SMP7

#define ADC_SMPR2_SMP7_0

#define ADC_SMPR2_SMP7_1

#define ADC_SMPR2_SMP7_2

#define ADC_SMPR2_SMP8

#define ADC_SMPR2_SMP8_0

#define ADC_SMPR2_SMP8_1

#define ADC_SMPR2_SMP8_2

#define ADC_SMPR2_SMP9

#define ADC_SMPR2_SMP9_0

#define ADC_SMPR2_SMP9_1

#define ADC_SMPR2_SMP9_2

#define ADC_JOFR1_JOFFSET1

#define ADC_JOFR2_JOFFSET2

#define ADC_JOFR3_JOFFSET3

#define ADC_JOFR4_JOFFSET4

#define ADC_HTR_HT

#define ADC_LTR_LT

#define ADC_SQR1_SQ13

#define ADC_SQR1_SQ13_0

#define ADC_SQR1_SQ13_1

#define ADC_SQR1_SQ13_2

#define ADC_SQR1_SQ13_3

#define ADC_SQR1_SQ13_4

#define ADC_SQR1_SQ14

#define ADC_SQR1_SQ14_0

#define ADC_SQR1_SQ14_1

#define ADC_SQR1_SQ14_2

#define ADC_SQR1_SQ14_3

#define ADC_SQR1_SQ14_4

#define ADC_SQR1_SQ15

#define ADC_SQR1_SQ15_0

#define ADC_SQR1_SQ15_1

#define ADC_SQR1_SQ15_2

#define ADC_SQR1_SQ15_3

#define ADC_SQR1_SQ15_4

#define ADC_SQR1_SQ16

#define ADC_SQR1_SQ16_0

#define ADC_SQR1_SQ16_1

#define ADC_SQR1_SQ16_2

#define ADC_SQR1_SQ16_3

#define ADC_SQR1_SQ16_4

#define ADC_SQR1_L

#define ADC_SQR1_L_0

#define ADC_SQR1_L_1

#define ADC_SQR1_L_2

#define ADC_SQR1_L_3

#define ADC_SQR2_SQ7

#define ADC_SQR2_SQ7_0

#define ADC_SQR2_SQ7_1

#define ADC_SQR2_SQ7_2

#define ADC_SQR2_SQ7_3

#define ADC_SQR2_SQ7_4

#define ADC_SQR2_SQ8

#define ADC_SQR2_SQ8_0

#define ADC_SQR2_SQ8_1

#define ADC_SQR2_SQ8_2

#define ADC_SQR2_SQ8_3

#define ADC_SQR2_SQ8_4

#define ADC_SQR2_SQ9

#define ADC_SQR2_SQ9_0

#define ADC_SQR2_SQ9_1

#define ADC_SQR2_SQ9_2

#define ADC_SQR2_SQ9_3

#define ADC_SQR2_SQ9_4

#define ADC_SQR2_SQ10

#define ADC_SQR2_SQ10_0

#define ADC_SQR2_SQ10_1

#define ADC_SQR2_SQ10_2

#define ADC_SQR2_SQ10_3

#define ADC_SQR2_SQ10_4

#define ADC_SQR2_SQ11

#define ADC_SQR2_SQ11_0

#define ADC_SQR2_SQ11_1

#define ADC_SQR2_SQ11_2

#define ADC_SQR2_SQ11_3

#define ADC_SQR2_SQ11_4

#define ADC_SQR2_SQ12

#define ADC_SQR2_SQ12_0

#define ADC_SQR2_SQ12_1

#define ADC_SQR2_SQ12_2

#define ADC_SQR2_SQ12_3

#define ADC_SQR2_SQ12_4

#define ADC_SQR3_SQ1

#define ADC_SQR3_SQ1_0

#define ADC_SQR3_SQ1_1

#define ADC_SQR3_SQ1_2

#define ADC_SQR3_SQ1_3

#define ADC_SQR3_SQ1_4

#define ADC_SQR3_SQ2

#define ADC_SQR3_SQ2_0

#define ADC_SQR3_SQ2_1

#define ADC_SQR3_SQ2_2

#define ADC_SQR3_SQ2_3

#define ADC_SQR3_SQ2_4

#define ADC_SQR3_SQ3

#define ADC_SQR3_SQ3_0

#define ADC_SQR3_SQ3_1

#define ADC_SQR3_SQ3_2

#define ADC_SQR3_SQ3_3

#define ADC_SQR3_SQ3_4

#define ADC_SQR3_SQ4

#define ADC_SQR3_SQ4_0

#define ADC_SQR3_SQ4_1

#define ADC_SQR3_SQ4_2

#define ADC_SQR3_SQ4_3

#define ADC_SQR3_SQ4_4

#define ADC_SQR3_SQ5

#define ADC_SQR3_SQ5_0

#define ADC_SQR3_SQ5_1

#define ADC_SQR3_SQ5_2

#define ADC_SQR3_SQ5_3

#define ADC_SQR3_SQ5_4

#define ADC_SQR3_SQ6

#define ADC_SQR3_SQ6_0

#define ADC_SQR3_SQ6_1

#define ADC_SQR3_SQ6_2

#define ADC_SQR3_SQ6_3

#define ADC_SQR3_SQ6_4

#define ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_4

#define ADC_JSQR_JL

#define ADC_JSQR_JL_0

#define ADC_JSQR_JL_1

#define ADC_JDR1_JDATA

#define ADC_JDR2_JDATA

#define ADC_JDR3_JDATA

#define ADC_JDR4_JDATA

#define ADC_DR_DATA

#define COMP_CSR_COMP1EN

#define COMP_CSR_COMP1SW1

#define COMP_CSR_COMP1MODE

#define COMP_CSR_COMP1MODE_0

#define COMP_CSR_COMP1MODE_1

#define COMP_CSR_COMP1INSEL

#define COMP_CSR_COMP1INSEL_0

#define COMP_CSR_COMP1INSEL_1

#define COMP_CSR_COMP1INSEL_2

#define COMP_CSR_COMP1OUTSEL

#define COMP_CSR_COMP1OUTSEL_0

#define COMP_CSR_COMP1OUTSEL_1

#define COMP_CSR_COMP1OUTSEL_2

#define COMP_CSR_COMP1POL

#define COMP_CSR_COMP1HYST

#define COMP_CSR_COMP1HYST_0

#define COMP_CSR_COMP1HYST_1

#define COMP_CSR_COMP1OUT

#define COMP_CSR_COMP1LOCK

#define COMP_CSR_COMP2EN

#define COMP_CSR_COMP2MODE

#define COMP_CSR_COMP2MODE_0

#define COMP_CSR_COMP2MODE_1

#define COMP_CSR_COMP2INSEL

#define COMP_CSR_COMP2INSEL_0

#define COMP_CSR_COMP2INSEL_1

#define COMP_CSR_COMP2INSEL_2

#define COMP_CSR_WNDWEN

#define COMP_CSR_COMP2OUTSEL

#define COMP_CSR_COMP2OUTSEL_0

#define COMP_CSR_COMP2OUTSEL_1

#define COMP_CSR_COMP2OUTSEL_2

#define COMP_CSR_COMP2POL

#define COMP_CSR_COMP2HYST

#define COMP_CSR_COMP2HYST_0

#define COMP_CSR_COMP2HYST_1

#define COMP_CSR_COMP2OUT

#define COMP_CSR_COMP2LOCK

#define CAN_MCR_INRQ

#define CAN_MCR_SLEEP

#define CAN_MCR_TXFP

#define CAN_MCR_RFLM

#define CAN_MCR_NART

#define CAN_MCR_AWUM

#define CAN_MCR_ABOM

#define CAN_MCR_TTCM

#define CAN_MCR_RESET

#define CAN_MSR_INAK

#define CAN_MSR_SLAK

#define CAN_MSR_ERRI

#define CAN_MSR_WKUI

#define CAN_MSR_SLAKI

#define CAN_MSR_TXM

#define CAN_MSR_RXM

#define CAN_MSR_SAMP

#define CAN_MSR_RX

#define CAN_TSR_RQCP0

#define CAN_TSR_TXOK0

#define CAN_TSR_ALST0

#define CAN_TSR_TERR0

#define CAN_TSR_ABRQ0

#define CAN_TSR_RQCP1

#define CAN_TSR_TXOK1

#define CAN_TSR_ALST1

#define CAN_TSR_TERR1

#define CAN_TSR_ABRQ1

#define CAN_TSR_RQCP2

#define CAN_TSR_TXOK2

#define CAN_TSR_ALST2

#define CAN_TSR_TERR2

#define CAN_TSR_ABRQ2

#define CAN_TSR_CODE

#define CAN_TSR_TME

#define CAN_TSR_TME0

#define CAN_TSR_TME1

#define CAN_TSR_TME2

#define CAN_TSR_LOW

#define CAN_TSR_LOW0

#define CAN_TSR_LOW1

#define CAN_TSR_LOW2

#define CAN_RF0R_FMP0

#define CAN_RF0R_FULL0

#define CAN_RF0R_FOVR0

#define CAN_RF0R_RFOM0

#define CAN_RF1R_FMP1

#define CAN_RF1R_FULL1

#define CAN_RF1R_FOVR1

#define CAN_RF1R_RFOM1

#define CAN_IER_TMEIE

#define CAN_IER_FMPIE0

#define CAN_IER_FFIE0

#define CAN_IER_FOVIE0

#define CAN_IER_FMPIE1

#define CAN_IER_FFIE1

#define CAN_IER_FOVIE1

#define CAN_IER_EWGIE

#define CAN_IER_EPVIE

#define CAN_IER_BOFIE

#define CAN_IER_LECIE

#define CAN_IER_ERRIE

#define CAN_IER_WKUIE

#define CAN_IER_SLKIE

#define CAN_ESR_EWGF

#define CAN_ESR_EPVF

#define CAN_ESR_BOFF

#define CAN_ESR_LEC

#define CAN_ESR_LEC_0

#define CAN_ESR_LEC_1

#define CAN_ESR_LEC_2

#define CAN_ESR_TEC

#define CAN_ESR_REC

#define CAN_BTR_BRP

#define CAN_BTR_TS1

#define CAN_BTR_TS2

#define CAN_BTR_SJW

#define CAN_BTR_LBKM

#define CAN_BTR_SILM

#define CAN_TI0R_TXRQ

#define CAN_TI0R_RTR

#define CAN_TI0R_IDE

#define CAN_TI0R_EXID

#define CAN_TI0R_STID

#define CAN_TDT0R_DLC

#define CAN_TDT0R_TGT

#define CAN_TDT0R_TIME

#define CAN_TDL0R_DATA0

#define CAN_TDL0R_DATA1

#define CAN_TDL0R_DATA2

#define CAN_TDL0R_DATA3

#define CAN_TDH0R_DATA4

#define CAN_TDH0R_DATA5

#define CAN_TDH0R_DATA6

#define CAN_TDH0R_DATA7

#define CAN_TI1R_TXRQ

#define CAN_TI1R_RTR

#define CAN_TI1R_IDE

#define CAN_TI1R_EXID

#define CAN_TI1R_STID

#define CAN_TDT1R_DLC

#define CAN_TDT1R_TGT

#define CAN_TDT1R_TIME

#define CAN_TDL1R_DATA0

#define CAN_TDL1R_DATA1

#define CAN_TDL1R_DATA2

#define CAN_TDL1R_DATA3

#define CAN_TDH1R_DATA4

#define CAN_TDH1R_DATA5

#define CAN_TDH1R_DATA6

#define CAN_TDH1R_DATA7

#define CAN_TI2R_TXRQ

#define CAN_TI2R_RTR

#define CAN_TI2R_IDE

#define CAN_TI2R_EXID

#define CAN_TI2R_STID

#define CAN_TDT2R_DLC

#define CAN_TDT2R_TGT

#define CAN_TDT2R_TIME

#define CAN_TDL2R_DATA0

#define CAN_TDL2R_DATA1

#define CAN_TDL2R_DATA2

#define CAN_TDL2R_DATA3

#define CAN_TDH2R_DATA4

#define CAN_TDH2R_DATA5

#define CAN_TDH2R_DATA6

#define CAN_TDH2R_DATA7

#define CAN_RI0R_RTR

#define CAN_RI0R_IDE

#define CAN_RI0R_EXID

#define CAN_RI0R_STID

#define CAN_RDT0R_DLC

#define CAN_RDT0R_FMI

#define CAN_RDT0R_TIME

#define CAN_RDL0R_DATA0

#define CAN_RDL0R_DATA1

#define CAN_RDL0R_DATA2

#define CAN_RDL0R_DATA3

#define CAN_RDH0R_DATA4

#define CAN_RDH0R_DATA5

#define CAN_RDH0R_DATA6

#define CAN_RDH0R_DATA7

#define CAN_RI1R_RTR

#define CAN_RI1R_IDE

#define CAN_RI1R_EXID

#define CAN_RI1R_STID

#define CAN_RDT1R_DLC

#define CAN_RDT1R_FMI

#define CAN_RDT1R_TIME

#define CAN_RDL1R_DATA0

#define CAN_RDL1R_DATA1

#define CAN_RDL1R_DATA2

#define CAN_RDL1R_DATA3

#define CAN_RDH1R_DATA4

#define CAN_RDH1R_DATA5

#define CAN_RDH1R_DATA6

#define CAN_RDH1R_DATA7

#define CAN_FMR_FINIT

#define CAN_FM1R_FBM

#define CAN_FM1R_FBM0

#define CAN_FM1R_FBM1

#define CAN_FM1R_FBM2

#define CAN_FM1R_FBM3

#define CAN_FM1R_FBM4

#define CAN_FM1R_FBM5

#define CAN_FM1R_FBM6

#define CAN_FM1R_FBM7

#define CAN_FM1R_FBM8

#define CAN_FM1R_FBM9

#define CAN_FM1R_FBM10

#define CAN_FM1R_FBM11

#define CAN_FM1R_FBM12

#define CAN_FM1R_FBM13

#define CAN_FS1R_FSC

#define CAN_FS1R_FSC0

#define CAN_FS1R_FSC1

#define CAN_FS1R_FSC2

#define CAN_FS1R_FSC3

#define CAN_FS1R_FSC4

#define CAN_FS1R_FSC5

#define CAN_FS1R_FSC6

#define CAN_FS1R_FSC7

#define CAN_FS1R_FSC8

#define CAN_FS1R_FSC9

#define CAN_FS1R_FSC10

#define CAN_FS1R_FSC11

#define CAN_FS1R_FSC12

#define CAN_FS1R_FSC13

#define CAN_FFA1R_FFA

#define CAN_FFA1R_FFA0

#define CAN_FFA1R_FFA1

#define CAN_FFA1R_FFA2

#define CAN_FFA1R_FFA3

#define CAN_FFA1R_FFA4

#define CAN_FFA1R_FFA5

#define CAN_FFA1R_FFA6

#define CAN_FFA1R_FFA7

#define CAN_FFA1R_FFA8

#define CAN_FFA1R_FFA9

#define CAN_FFA1R_FFA10

#define CAN_FFA1R_FFA11

#define CAN_FFA1R_FFA12

#define CAN_FFA1R_FFA13

#define CAN_FA1R_FACT

#define CAN_FA1R_FACT0

#define CAN_FA1R_FACT1

#define CAN_FA1R_FACT2

#define CAN_FA1R_FACT3

#define CAN_FA1R_FACT4

#define CAN_FA1R_FACT5

#define CAN_FA1R_FACT6

#define CAN_FA1R_FACT7

#define CAN_FA1R_FACT8

#define CAN_FA1R_FACT9

#define CAN_FA1R_FACT10

#define CAN_FA1R_FACT11

#define CAN_FA1R_FACT12

#define CAN_FA1R_FACT13

#define CAN_F0R1_FB0

#define CAN_F0R1_FB1

#define CAN_F0R1_FB2

#define CAN_F0R1_FB3

#define CAN_F0R1_FB4

#define CAN_F0R1_FB5

#define CAN_F0R1_FB6

#define CAN_F0R1_FB7

#define CAN_F0R1_FB8

#define CAN_F0R1_FB9

#define CAN_F0R1_FB10

#define CAN_F0R1_FB11

#define CAN_F0R1_FB12

#define CAN_F0R1_FB13

#define CAN_F0R1_FB14

#define CAN_F0R1_FB15

#define CAN_F0R1_FB16

#define CAN_F0R1_FB17

#define CAN_F0R1_FB18

#define CAN_F0R1_FB19

#define CAN_F0R1_FB20

#define CAN_F0R1_FB21

#define CAN_F0R1_FB22

#define CAN_F0R1_FB23

#define CAN_F0R1_FB24

#define CAN_F0R1_FB25

#define CAN_F0R1_FB26

#define CAN_F0R1_FB27

#define CAN_F0R1_FB28

#define CAN_F0R1_FB29

#define CAN_F0R1_FB30

#define CAN_F0R1_FB31

#define CAN_F1R1_FB0

#define CAN_F1R1_FB1

#define CAN_F1R1_FB2

#define CAN_F1R1_FB3

#define CAN_F1R1_FB4

#define CAN_F1R1_FB5

#define CAN_F1R1_FB6

#define CAN_F1R1_FB7

#define CAN_F1R1_FB8

#define CAN_F1R1_FB9

#define CAN_F1R1_FB10

#define CAN_F1R1_FB11

#define CAN_F1R1_FB12

#define CAN_F1R1_FB13

#define CAN_F1R1_FB14

#define CAN_F1R1_FB15

#define CAN_F1R1_FB16

#define CAN_F1R1_FB17

#define CAN_F1R1_FB18

#define CAN_F1R1_FB19

#define CAN_F1R1_FB20

#define CAN_F1R1_FB21

#define CAN_F1R1_FB22

#define CAN_F1R1_FB23

#define CAN_F1R1_FB24

#define CAN_F1R1_FB25

#define CAN_F1R1_FB26

#define CAN_F1R1_FB27

#define CAN_F1R1_FB28

#define CAN_F1R1_FB29

#define CAN_F1R1_FB30

#define CAN_F1R1_FB31

#define CAN_F2R1_FB0

#define CAN_F2R1_FB1

#define CAN_F2R1_FB2

#define CAN_F2R1_FB3

#define CAN_F2R1_FB4

#define CAN_F2R1_FB5

#define CAN_F2R1_FB6

#define CAN_F2R1_FB7

#define CAN_F2R1_FB8

#define CAN_F2R1_FB9

#define CAN_F2R1_FB10

#define CAN_F2R1_FB11

#define CAN_F2R1_FB12

#define CAN_F2R1_FB13

#define CAN_F2R1_FB14

#define CAN_F2R1_FB15

#define CAN_F2R1_FB16

#define CAN_F2R1_FB17

#define CAN_F2R1_FB18

#define CAN_F2R1_FB19

#define CAN_F2R1_FB20

#define CAN_F2R1_FB21

#define CAN_F2R1_FB22

#define CAN_F2R1_FB23

#define CAN_F2R1_FB24

#define CAN_F2R1_FB25

#define CAN_F2R1_FB26

#define CAN_F2R1_FB27

#define CAN_F2R1_FB28

#define CAN_F2R1_FB29

#define CAN_F2R1_FB30

#define CAN_F2R1_FB31

#define CAN_F3R1_FB0

#define CAN_F3R1_FB1

#define CAN_F3R1_FB2

#define CAN_F3R1_FB3

#define CAN_F3R1_FB4

#define CAN_F3R1_FB5

#define CAN_F3R1_FB6

#define CAN_F3R1_FB7

#define CAN_F3R1_FB8

#define CAN_F3R1_FB9

#define CAN_F3R1_FB10

#define CAN_F3R1_FB11

#define CAN_F3R1_FB12

#define CAN_F3R1_FB13

#define CAN_F3R1_FB14

#define CAN_F3R1_FB15

#define CAN_F3R1_FB16

#define CAN_F3R1_FB17

#define CAN_F3R1_FB18

#define CAN_F3R1_FB19

#define CAN_F3R1_FB20

#define CAN_F3R1_FB21

#define CAN_F3R1_FB22

#define CAN_F3R1_FB23

#define CAN_F3R1_FB24

#define CAN_F3R1_FB25

#define CAN_F3R1_FB26

#define CAN_F3R1_FB27

#define CAN_F3R1_FB28

#define CAN_F3R1_FB29

#define CAN_F3R1_FB30

#define CAN_F3R1_FB31

#define CAN_F4R1_FB0

#define CAN_F4R1_FB1

#define CAN_F4R1_FB2

#define CAN_F4R1_FB3

#define CAN_F4R1_FB4

#define CAN_F4R1_FB5

#define CAN_F4R1_FB6

#define CAN_F4R1_FB7

#define CAN_F4R1_FB8

#define CAN_F4R1_FB9

#define CAN_F4R1_FB10

#define CAN_F4R1_FB11

#define CAN_F4R1_FB12

#define CAN_F4R1_FB13

#define CAN_F4R1_FB14

#define CAN_F4R1_FB15

#define CAN_F4R1_FB16

#define CAN_F4R1_FB17

#define CAN_F4R1_FB18

#define CAN_F4R1_FB19

#define CAN_F4R1_FB20

#define CAN_F4R1_FB21

#define CAN_F4R1_FB22

#define CAN_F4R1_FB23

#define CAN_F4R1_FB24

#define CAN_F4R1_FB25

#define CAN_F4R1_FB26

#define CAN_F4R1_FB27

#define CAN_F4R1_FB28

#define CAN_F4R1_FB29

#define CAN_F4R1_FB30

#define CAN_F4R1_FB31

#define CAN_F5R1_FB0

#define CAN_F5R1_FB1

#define CAN_F5R1_FB2

#define CAN_F5R1_FB3

#define CAN_F5R1_FB4

#define CAN_F5R1_FB5

#define CAN_F5R1_FB6

#define CAN_F5R1_FB7

#define CAN_F5R1_FB8

#define CAN_F5R1_FB9

#define CAN_F5R1_FB10

#define CAN_F5R1_FB11

#define CAN_F5R1_FB12

#define CAN_F5R1_FB13

#define CAN_F5R1_FB14

#define CAN_F5R1_FB15

#define CAN_F5R1_FB16

#define CAN_F5R1_FB17

#define CAN_F5R1_FB18

#define CAN_F5R1_FB19

#define CAN_F5R1_FB20

#define CAN_F5R1_FB21

#define CAN_F5R1_FB22

#define CAN_F5R1_FB23

#define CAN_F5R1_FB24

#define CAN_F5R1_FB25

#define CAN_F5R1_FB26

#define CAN_F5R1_FB27

#define CAN_F5R1_FB28

#define CAN_F5R1_FB29

#define CAN_F5R1_FB30

#define CAN_F5R1_FB31

#define CAN_F6R1_FB0

#define CAN_F6R1_FB1

#define CAN_F6R1_FB2

#define CAN_F6R1_FB3

#define CAN_F6R1_FB4

#define CAN_F6R1_FB5

#define CAN_F6R1_FB6

#define CAN_F6R1_FB7

#define CAN_F6R1_FB8

#define CAN_F6R1_FB9

#define CAN_F6R1_FB10

#define CAN_F6R1_FB11

#define CAN_F6R1_FB12

#define CAN_F6R1_FB13

#define CAN_F6R1_FB14

#define CAN_F6R1_FB15

#define CAN_F6R1_FB16

#define CAN_F6R1_FB17

#define CAN_F6R1_FB18

#define CAN_F6R1_FB19

#define CAN_F6R1_FB20

#define CAN_F6R1_FB21

#define CAN_F6R1_FB22

#define CAN_F6R1_FB23

#define CAN_F6R1_FB24

#define CAN_F6R1_FB25

#define CAN_F6R1_FB26

#define CAN_F6R1_FB27

#define CAN_F6R1_FB28

#define CAN_F6R1_FB29

#define CAN_F6R1_FB30

#define CAN_F6R1_FB31

#define CAN_F7R1_FB0

#define CAN_F7R1_FB1

#define CAN_F7R1_FB2

#define CAN_F7R1_FB3

#define CAN_F7R1_FB4

#define CAN_F7R1_FB5

#define CAN_F7R1_FB6

#define CAN_F7R1_FB7

#define CAN_F7R1_FB8

#define CAN_F7R1_FB9

#define CAN_F7R1_FB10

#define CAN_F7R1_FB11

#define CAN_F7R1_FB12

#define CAN_F7R1_FB13

#define CAN_F7R1_FB14

#define CAN_F7R1_FB15

#define CAN_F7R1_FB16

#define CAN_F7R1_FB17

#define CAN_F7R1_FB18

#define CAN_F7R1_FB19

#define CAN_F7R1_FB20

#define CAN_F7R1_FB21

#define CAN_F7R1_FB22

#define CAN_F7R1_FB23

#define CAN_F7R1_FB24

#define CAN_F7R1_FB25

#define CAN_F7R1_FB26

#define CAN_F7R1_FB27

#define CAN_F7R1_FB28

#define CAN_F7R1_FB29

#define CAN_F7R1_FB30

#define CAN_F7R1_FB31

#define CAN_F8R1_FB0

#define CAN_F8R1_FB1

#define CAN_F8R1_FB2

#define CAN_F8R1_FB3

#define CAN_F8R1_FB4

#define CAN_F8R1_FB5

#define CAN_F8R1_FB6

#define CAN_F8R1_FB7

#define CAN_F8R1_FB8

#define CAN_F8R1_FB9

#define CAN_F8R1_FB10

#define CAN_F8R1_FB11

#define CAN_F8R1_FB12

#define CAN_F8R1_FB13

#define CAN_F8R1_FB14

#define CAN_F8R1_FB15

#define CAN_F8R1_FB16

#define CAN_F8R1_FB17

#define CAN_F8R1_FB18

#define CAN_F8R1_FB19

#define CAN_F8R1_FB20

#define CAN_F8R1_FB21

#define CAN_F8R1_FB22

#define CAN_F8R1_FB23

#define CAN_F8R1_FB24

#define CAN_F8R1_FB25

#define CAN_F8R1_FB26

#define CAN_F8R1_FB27

#define CAN_F8R1_FB28

#define CAN_F8R1_FB29

#define CAN_F8R1_FB30

#define CAN_F8R1_FB31

#define CAN_F9R1_FB0

#define CAN_F9R1_FB1

#define CAN_F9R1_FB2

#define CAN_F9R1_FB3

#define CAN_F9R1_FB4

#define CAN_F9R1_FB5

#define CAN_F9R1_FB6

#define CAN_F9R1_FB7

#define CAN_F9R1_FB8

#define CAN_F9R1_FB9

#define CAN_F9R1_FB10

#define CAN_F9R1_FB11

#define CAN_F9R1_FB12

#define CAN_F9R1_FB13

#define CAN_F9R1_FB14

#define CAN_F9R1_FB15

#define CAN_F9R1_FB16

#define CAN_F9R1_FB17

#define CAN_F9R1_FB18

#define CAN_F9R1_FB19

#define CAN_F9R1_FB20

#define CAN_F9R1_FB21

#define CAN_F9R1_FB22

#define CAN_F9R1_FB23

#define CAN_F9R1_FB24

#define CAN_F9R1_FB25

#define CAN_F9R1_FB26

#define CAN_F9R1_FB27

#define CAN_F9R1_FB28

#define CAN_F9R1_FB29

#define CAN_F9R1_FB30

#define CAN_F9R1_FB31

#define CAN_F10R1_FB0

#define CAN_F10R1_FB1

#define CAN_F10R1_FB2

#define CAN_F10R1_FB3

#define CAN_F10R1_FB4

#define CAN_F10R1_FB5

#define CAN_F10R1_FB6

#define CAN_F10R1_FB7

#define CAN_F10R1_FB8

#define CAN_F10R1_FB9

#define CAN_F10R1_FB10

#define CAN_F10R1_FB11

#define CAN_F10R1_FB12

#define CAN_F10R1_FB13

#define CAN_F10R1_FB14

#define CAN_F10R1_FB15

#define CAN_F10R1_FB16

#define CAN_F10R1_FB17

#define CAN_F10R1_FB18

#define CAN_F10R1_FB19

#define CAN_F10R1_FB20

#define CAN_F10R1_FB21

#define CAN_F10R1_FB22

#define CAN_F10R1_FB23

#define CAN_F10R1_FB24

#define CAN_F10R1_FB25

#define CAN_F10R1_FB26

#define CAN_F10R1_FB27

#define CAN_F10R1_FB28

#define CAN_F10R1_FB29

#define CAN_F10R1_FB30

#define CAN_F10R1_FB31

#define CAN_F11R1_FB0

#define CAN_F11R1_FB1

#define CAN_F11R1_FB2

#define CAN_F11R1_FB3

#define CAN_F11R1_FB4

#define CAN_F11R1_FB5

#define CAN_F11R1_FB6

#define CAN_F11R1_FB7

#define CAN_F11R1_FB8

#define CAN_F11R1_FB9

#define CAN_F11R1_FB10

#define CAN_F11R1_FB11

#define CAN_F11R1_FB12

#define CAN_F11R1_FB13

#define CAN_F11R1_FB14

#define CAN_F11R1_FB15

#define CAN_F11R1_FB16

#define CAN_F11R1_FB17

#define CAN_F11R1_FB18

#define CAN_F11R1_FB19

#define CAN_F11R1_FB20

#define CAN_F11R1_FB21

#define CAN_F11R1_FB22

#define CAN_F11R1_FB23

#define CAN_F11R1_FB24

#define CAN_F11R1_FB25

#define CAN_F11R1_FB26

#define CAN_F11R1_FB27

#define CAN_F11R1_FB28

#define CAN_F11R1_FB29

#define CAN_F11R1_FB30

#define CAN_F11R1_FB31

#define CAN_F12R1_FB0

#define CAN_F12R1_FB1

#define CAN_F12R1_FB2

#define CAN_F12R1_FB3

#define CAN_F12R1_FB4

#define CAN_F12R1_FB5

#define CAN_F12R1_FB6

#define CAN_F12R1_FB7

#define CAN_F12R1_FB8

#define CAN_F12R1_FB9

#define CAN_F12R1_FB10

#define CAN_F12R1_FB11

#define CAN_F12R1_FB12

#define CAN_F12R1_FB13

#define CAN_F12R1_FB14

#define CAN_F12R1_FB15

#define CAN_F12R1_FB16

#define CAN_F12R1_FB17

#define CAN_F12R1_FB18

#define CAN_F12R1_FB19

#define CAN_F12R1_FB20

#define CAN_F12R1_FB21

#define CAN_F12R1_FB22

#define CAN_F12R1_FB23

#define CAN_F12R1_FB24

#define CAN_F12R1_FB25

#define CAN_F12R1_FB26

#define CAN_F12R1_FB27

#define CAN_F12R1_FB28

#define CAN_F12R1_FB29

#define CAN_F12R1_FB30

#define CAN_F12R1_FB31

#define CAN_F13R1_FB0

#define CAN_F13R1_FB1

#define CAN_F13R1_FB2

#define CAN_F13R1_FB3

#define CAN_F13R1_FB4

#define CAN_F13R1_FB5

#define CAN_F13R1_FB6

#define CAN_F13R1_FB7

#define CAN_F13R1_FB8

#define CAN_F13R1_FB9

#define CAN_F13R1_FB10

#define CAN_F13R1_FB11

#define CAN_F13R1_FB12

#define CAN_F13R1_FB13

#define CAN_F13R1_FB14

#define CAN_F13R1_FB15

#define CAN_F13R1_FB16

#define CAN_F13R1_FB17

#define CAN_F13R1_FB18

#define CAN_F13R1_FB19

#define CAN_F13R1_FB20

#define CAN_F13R1_FB21

#define CAN_F13R1_FB22

#define CAN_F13R1_FB23

#define CAN_F13R1_FB24

#define CAN_F13R1_FB25

#define CAN_F13R1_FB26

#define CAN_F13R1_FB27

#define CAN_F13R1_FB28

#define CAN_F13R1_FB29

#define CAN_F13R1_FB30

#define CAN_F13R1_FB31

#define CAN_F0R2_FB0

#define CAN_F0R2_FB1

#define CAN_F0R2_FB2

#define CAN_F0R2_FB3

#define CAN_F0R2_FB4

#define CAN_F0R2_FB5

#define CAN_F0R2_FB6

#define CAN_F0R2_FB7

#define CAN_F0R2_FB8

#define CAN_F0R2_FB9

#define CAN_F0R2_FB10

#define CAN_F0R2_FB11

#define CAN_F0R2_FB12

#define CAN_F0R2_FB13

#define CAN_F0R2_FB14

#define CAN_F0R2_FB15

#define CAN_F0R2_FB16

#define CAN_F0R2_FB17

#define CAN_F0R2_FB18

#define CAN_F0R2_FB19

#define CAN_F0R2_FB20

#define CAN_F0R2_FB21

#define CAN_F0R2_FB22

#define CAN_F0R2_FB23

#define CAN_F0R2_FB24

#define CAN_F0R2_FB25

#define CAN_F0R2_FB26

#define CAN_F0R2_FB27

#define CAN_F0R2_FB28

#define CAN_F0R2_FB29

#define CAN_F0R2_FB30

#define CAN_F0R2_FB31

#define CAN_F1R2_FB0

#define CAN_F1R2_FB1

#define CAN_F1R2_FB2

#define CAN_F1R2_FB3

#define CAN_F1R2_FB4

#define CAN_F1R2_FB5

#define CAN_F1R2_FB6

#define CAN_F1R2_FB7

#define CAN_F1R2_FB8

#define CAN_F1R2_FB9

#define CAN_F1R2_FB10

#define CAN_F1R2_FB11

#define CAN_F1R2_FB12

#define CAN_F1R2_FB13

#define CAN_F1R2_FB14

#define CAN_F1R2_FB15

#define CAN_F1R2_FB16

#define CAN_F1R2_FB17

#define CAN_F1R2_FB18

#define CAN_F1R2_FB19

#define CAN_F1R2_FB20

#define CAN_F1R2_FB21

#define CAN_F1R2_FB22

#define CAN_F1R2_FB23

#define CAN_F1R2_FB24

#define CAN_F1R2_FB25

#define CAN_F1R2_FB26

#define CAN_F1R2_FB27

#define CAN_F1R2_FB28

#define CAN_F1R2_FB29

#define CAN_F1R2_FB30

#define CAN_F1R2_FB31

#define CAN_F2R2_FB0

#define CAN_F2R2_FB1

#define CAN_F2R2_FB2

#define CAN_F2R2_FB3

#define CAN_F2R2_FB4

#define CAN_F2R2_FB5

#define CAN_F2R2_FB6

#define CAN_F2R2_FB7

#define CAN_F2R2_FB8

#define CAN_F2R2_FB9

#define CAN_F2R2_FB10

#define CAN_F2R2_FB11

#define CAN_F2R2_FB12

#define CAN_F2R2_FB13

#define CAN_F2R2_FB14

#define CAN_F2R2_FB15

#define CAN_F2R2_FB16

#define CAN_F2R2_FB17

#define CAN_F2R2_FB18

#define CAN_F2R2_FB19

#define CAN_F2R2_FB20

#define CAN_F2R2_FB21

#define CAN_F2R2_FB22

#define CAN_F2R2_FB23

#define CAN_F2R2_FB24

#define CAN_F2R2_FB25

#define CAN_F2R2_FB26

#define CAN_F2R2_FB27

#define CAN_F2R2_FB28

#define CAN_F2R2_FB29

#define CAN_F2R2_FB30

#define CAN_F2R2_FB31

#define CAN_F3R2_FB0

#define CAN_F3R2_FB1

#define CAN_F3R2_FB2

#define CAN_F3R2_FB3

#define CAN_F3R2_FB4

#define CAN_F3R2_FB5

#define CAN_F3R2_FB6

#define CAN_F3R2_FB7

#define CAN_F3R2_FB8

#define CAN_F3R2_FB9

#define CAN_F3R2_FB10

#define CAN_F3R2_FB11

#define CAN_F3R2_FB12

#define CAN_F3R2_FB13

#define CAN_F3R2_FB14

#define CAN_F3R2_FB15

#define CAN_F3R2_FB16

#define CAN_F3R2_FB17

#define CAN_F3R2_FB18

#define CAN_F3R2_FB19

#define CAN_F3R2_FB20

#define CAN_F3R2_FB21

#define CAN_F3R2_FB22

#define CAN_F3R2_FB23

#define CAN_F3R2_FB24

#define CAN_F3R2_FB25

#define CAN_F3R2_FB26

#define CAN_F3R2_FB27

#define CAN_F3R2_FB28

#define CAN_F3R2_FB29

#define CAN_F3R2_FB30

#define CAN_F3R2_FB31

#define CAN_F4R2_FB0

#define CAN_F4R2_FB1

#define CAN_F4R2_FB2

#define CAN_F4R2_FB3

#define CAN_F4R2_FB4

#define CAN_F4R2_FB5

#define CAN_F4R2_FB6

#define CAN_F4R2_FB7

#define CAN_F4R2_FB8

#define CAN_F4R2_FB9

#define CAN_F4R2_FB10

#define CAN_F4R2_FB11

#define CAN_F4R2_FB12

#define CAN_F4R2_FB13

#define CAN_F4R2_FB14

#define CAN_F4R2_FB15

#define CAN_F4R2_FB16

#define CAN_F4R2_FB17

#define CAN_F4R2_FB18

#define CAN_F4R2_FB19

#define CAN_F4R2_FB20

#define CAN_F4R2_FB21

#define CAN_F4R2_FB22

#define CAN_F4R2_FB23

#define CAN_F4R2_FB24

#define CAN_F4R2_FB25

#define CAN_F4R2_FB26

#define CAN_F4R2_FB27

#define CAN_F4R2_FB28

#define CAN_F4R2_FB29

#define CAN_F4R2_FB30

#define CAN_F4R2_FB31

#define CAN_F5R2_FB0

#define CAN_F5R2_FB1

#define CAN_F5R2_FB2

#define CAN_F5R2_FB3

#define CAN_F5R2_FB4

#define CAN_F5R2_FB5

#define CAN_F5R2_FB6

#define CAN_F5R2_FB7

#define CAN_F5R2_FB8

#define CAN_F5R2_FB9

#define CAN_F5R2_FB10

#define CAN_F5R2_FB11

#define CAN_F5R2_FB12

#define CAN_F5R2_FB13

#define CAN_F5R2_FB14

#define CAN_F5R2_FB15

#define CAN_F5R2_FB16

#define CAN_F5R2_FB17

#define CAN_F5R2_FB18

#define CAN_F5R2_FB19

#define CAN_F5R2_FB20

#define CAN_F5R2_FB21

#define CAN_F5R2_FB22

#define CAN_F5R2_FB23

#define CAN_F5R2_FB24

#define CAN_F5R2_FB25

#define CAN_F5R2_FB26

#define CAN_F5R2_FB27

#define CAN_F5R2_FB28

#define CAN_F5R2_FB29

#define CAN_F5R2_FB30

#define CAN_F5R2_FB31

#define CAN_F6R2_FB0

#define CAN_F6R2_FB1

#define CAN_F6R2_FB2

#define CAN_F6R2_FB3

#define CAN_F6R2_FB4

#define CAN_F6R2_FB5

#define CAN_F6R2_FB6

#define CAN_F6R2_FB7

#define CAN_F6R2_FB8

#define CAN_F6R2_FB9

#define CAN_F6R2_FB10

#define CAN_F6R2_FB11

#define CAN_F6R2_FB12

#define CAN_F6R2_FB13

#define CAN_F6R2_FB14

#define CAN_F6R2_FB15

#define CAN_F6R2_FB16

#define CAN_F6R2_FB17

#define CAN_F6R2_FB18

#define CAN_F6R2_FB19

#define CAN_F6R2_FB20

#define CAN_F6R2_FB21

#define CAN_F6R2_FB22

#define CAN_F6R2_FB23

#define CAN_F6R2_FB24

#define CAN_F6R2_FB25

#define CAN_F6R2_FB26

#define CAN_F6R2_FB27

#define CAN_F6R2_FB28

#define CAN_F6R2_FB29

#define CAN_F6R2_FB30

#define CAN_F6R2_FB31

#define CAN_F7R2_FB0

#define CAN_F7R2_FB1

#define CAN_F7R2_FB2

#define CAN_F7R2_FB3

#define CAN_F7R2_FB4

#define CAN_F7R2_FB5

#define CAN_F7R2_FB6

#define CAN_F7R2_FB7

#define CAN_F7R2_FB8

#define CAN_F7R2_FB9

#define CAN_F7R2_FB10

#define CAN_F7R2_FB11

#define CAN_F7R2_FB12

#define CAN_F7R2_FB13

#define CAN_F7R2_FB14

#define CAN_F7R2_FB15

#define CAN_F7R2_FB16

#define CAN_F7R2_FB17

#define CAN_F7R2_FB18

#define CAN_F7R2_FB19

#define CAN_F7R2_FB20

#define CAN_F7R2_FB21

#define CAN_F7R2_FB22

#define CAN_F7R2_FB23

#define CAN_F7R2_FB24

#define CAN_F7R2_FB25

#define CAN_F7R2_FB26

#define CAN_F7R2_FB27

#define CAN_F7R2_FB28

#define CAN_F7R2_FB29

#define CAN_F7R2_FB30

#define CAN_F7R2_FB31

#define CAN_F8R2_FB0

#define CAN_F8R2_FB1

#define CAN_F8R2_FB2

#define CAN_F8R2_FB3

#define CAN_F8R2_FB4

#define CAN_F8R2_FB5

#define CAN_F8R2_FB6

#define CAN_F8R2_FB7

#define CAN_F8R2_FB8

#define CAN_F8R2_FB9

#define CAN_F8R2_FB10

#define CAN_F8R2_FB11

#define CAN_F8R2_FB12

#define CAN_F8R2_FB13

#define CAN_F8R2_FB14

#define CAN_F8R2_FB15

#define CAN_F8R2_FB16

#define CAN_F8R2_FB17

#define CAN_F8R2_FB18

#define CAN_F8R2_FB19

#define CAN_F8R2_FB20

#define CAN_F8R2_FB21

#define CAN_F8R2_FB22

#define CAN_F8R2_FB23

#define CAN_F8R2_FB24

#define CAN_F8R2_FB25

#define CAN_F8R2_FB26

#define CAN_F8R2_FB27

#define CAN_F8R2_FB28

#define CAN_F8R2_FB29

#define CAN_F8R2_FB30

#define CAN_F8R2_FB31

#define CAN_F9R2_FB0

#define CAN_F9R2_FB1

#define CAN_F9R2_FB2

#define CAN_F9R2_FB3

#define CAN_F9R2_FB4

#define CAN_F9R2_FB5

#define CAN_F9R2_FB6

#define CAN_F9R2_FB7

#define CAN_F9R2_FB8

#define CAN_F9R2_FB9

#define CAN_F9R2_FB10

#define CAN_F9R2_FB11

#define CAN_F9R2_FB12

#define CAN_F9R2_FB13

#define CAN_F9R2_FB14

#define CAN_F9R2_FB15

#define CAN_F9R2_FB16

#define CAN_F9R2_FB17

#define CAN_F9R2_FB18

#define CAN_F9R2_FB19

#define CAN_F9R2_FB20

#define CAN_F9R2_FB21

#define CAN_F9R2_FB22

#define CAN_F9R2_FB23

#define CAN_F9R2_FB24

#define CAN_F9R2_FB25

#define CAN_F9R2_FB26

#define CAN_F9R2_FB27

#define CAN_F9R2_FB28

#define CAN_F9R2_FB29

#define CAN_F9R2_FB30

#define CAN_F9R2_FB31

#define CAN_F10R2_FB0

#define CAN_F10R2_FB1

#define CAN_F10R2_FB2

#define CAN_F10R2_FB3

#define CAN_F10R2_FB4

#define CAN_F10R2_FB5

#define CAN_F10R2_FB6

#define CAN_F10R2_FB7

#define CAN_F10R2_FB8

#define CAN_F10R2_FB9

#define CAN_F10R2_FB10

#define CAN_F10R2_FB11

#define CAN_F10R2_FB12

#define CAN_F10R2_FB13

#define CAN_F10R2_FB14

#define CAN_F10R2_FB15

#define CAN_F10R2_FB16

#define CAN_F10R2_FB17

#define CAN_F10R2_FB18

#define CAN_F10R2_FB19

#define CAN_F10R2_FB20

#define CAN_F10R2_FB21

#define CAN_F10R2_FB22

#define CAN_F10R2_FB23

#define CAN_F10R2_FB24

#define CAN_F10R2_FB25

#define CAN_F10R2_FB26

#define CAN_F10R2_FB27

#define CAN_F10R2_FB28

#define CAN_F10R2_FB29

#define CAN_F10R2_FB30

#define CAN_F10R2_FB31

#define CAN_F11R2_FB0

#define CAN_F11R2_FB1

#define CAN_F11R2_FB2

#define CAN_F11R2_FB3

#define CAN_F11R2_FB4

#define CAN_F11R2_FB5

#define CAN_F11R2_FB6

#define CAN_F11R2_FB7

#define CAN_F11R2_FB8

#define CAN_F11R2_FB9

#define CAN_F11R2_FB10

#define CAN_F11R2_FB11

#define CAN_F11R2_FB12

#define CAN_F11R2_FB13

#define CAN_F11R2_FB14

#define CAN_F11R2_FB15

#define CAN_F11R2_FB16

#define CAN_F11R2_FB17

#define CAN_F11R2_FB18

#define CAN_F11R2_FB19

#define CAN_F11R2_FB20

#define CAN_F11R2_FB21

#define CAN_F11R2_FB22

#define CAN_F11R2_FB23

#define CAN_F11R2_FB24

#define CAN_F11R2_FB25

#define CAN_F11R2_FB26

#define CAN_F11R2_FB27

#define CAN_F11R2_FB28

#define CAN_F11R2_FB29

#define CAN_F11R2_FB30

#define CAN_F11R2_FB31

#define CAN_F12R2_FB0

#define CAN_F12R2_FB1

#define CAN_F12R2_FB2

#define CAN_F12R2_FB3

#define CAN_F12R2_FB4

#define CAN_F12R2_FB5

#define CAN_F12R2_FB6

#define CAN_F12R2_FB7

#define CAN_F12R2_FB8

#define CAN_F12R2_FB9

#define CAN_F12R2_FB10

#define CAN_F12R2_FB11

#define CAN_F12R2_FB12

#define CAN_F12R2_FB13

#define CAN_F12R2_FB14

#define CAN_F12R2_FB15

#define CAN_F12R2_FB16

#define CAN_F12R2_FB17

#define CAN_F12R2_FB18

#define CAN_F12R2_FB19

#define CAN_F12R2_FB20

#define CAN_F12R2_FB21

#define CAN_F12R2_FB22

#define CAN_F12R2_FB23

#define CAN_F12R2_FB24

#define CAN_F12R2_FB25

#define CAN_F12R2_FB26

#define CAN_F12R2_FB27

#define CAN_F12R2_FB28

#define CAN_F12R2_FB29

#define CAN_F12R2_FB30

#define CAN_F12R2_FB31

#define CAN_F13R2_FB0

#define CAN_F13R2_FB1

#define CAN_F13R2_FB2

#define CAN_F13R2_FB3

#define CAN_F13R2_FB4

#define CAN_F13R2_FB5

#define CAN_F13R2_FB6

#define CAN_F13R2_FB7

#define CAN_F13R2_FB8

#define CAN_F13R2_FB9

#define CAN_F13R2_FB10

#define CAN_F13R2_FB11

#define CAN_F13R2_FB12

#define CAN_F13R2_FB13

#define CAN_F13R2_FB14

#define CAN_F13R2_FB15

#define CAN_F13R2_FB16

#define CAN_F13R2_FB17

#define CAN_F13R2_FB18

#define CAN_F13R2_FB19

#define CAN_F13R2_FB20

#define CAN_F13R2_FB21

#define CAN_F13R2_FB22

#define CAN_F13R2_FB23

#define CAN_F13R2_FB24

#define CAN_F13R2_FB25

#define CAN_F13R2_FB26

#define CAN_F13R2_FB27

#define CAN_F13R2_FB28

#define CAN_F13R2_FB29

#define CAN_F13R2_FB30

#define CAN_F13R2_FB31

#define CRC_DR_DR

#define CRC_IDR_IDR

#define CRC_CR_RESET

#define CRC_CR_POLSIZE

#define CRC_CR_POLSIZE_0

#define CRC_CR_POLSIZE_1

#define CRC_CR_REV_IN

#define CRC_CR_REV_IN_0

#define CRC_CR_REV_IN_1

#define CRC_CR_REV_OUT

#define CRC_INIT_INIT

#define CRC_POL_POL

#define DAC_CR_EN1

#define DAC_CR_BOFF1

#define DAC_CR_TEN1

#define DAC_CR_TSEL1

#define DAC_CR_TSEL1_0

#define DAC_CR_TSEL1_1

#define DAC_CR_TSEL1_2

#define DAC_CR_WAVE1

#define DAC_CR_WAVE1_0

#define DAC_CR_WAVE1_1

#define DAC_CR_MAMP1

#define DAC_CR_MAMP1_0

#define DAC_CR_MAMP1_1

#define DAC_CR_MAMP1_2

#define DAC_CR_MAMP1_3

#define DAC_CR_DMAEN1

#define DAC_CR_EN2

#define DAC_CR_BOFF2

#define DAC_CR_TEN2

#define DAC_CR_TSEL2

#define DAC_CR_TSEL2_0

#define DAC_CR_TSEL2_1

#define DAC_CR_TSEL2_2

#define DAC_CR_WAVE2

#define DAC_CR_WAVE2_0

#define DAC_CR_WAVE2_1

#define DAC_CR_MAMP2

#define DAC_CR_MAMP2_0

#define DAC_CR_MAMP2_1

#define DAC_CR_MAMP2_2

#define DAC_CR_MAMP2_3

#define DAC_CR_DMAEN2

#define DAC_SWTRIGR_SWTRIG1

#define DAC_SWTRIGR_SWTRIG2

#define DAC_DHR12R1_DACC1DHR

#define DAC_DHR12L1_DACC1DHR

#define DAC_DHR8R1_DACC1DHR

#define DAC_DHR12R2_DACC2DHR

#define DAC_DHR12L2_DACC2DHR

#define DAC_DHR8R2_DACC2DHR

#define DAC_DHR12RD_DACC1DHR

#define DAC_DHR12RD_DACC2DHR

#define DAC_DHR12LD_DACC1DHR

#define DAC_DHR12LD_DACC2DHR

#define DAC_DHR8RD_DACC1DHR

#define DAC_DHR8RD_DACC2DHR

#define DAC_DOR1_DACC1DOR

#define DAC_DOR2_DACC2DOR

#define DAC_SR_DMAUDR1

#define DAC_SR_DMAUDR2

#define DBGMCU_IDCODE_DEV_ID

#define DBGMCU_IDCODE_REV_ID

#define DBGMCU_CR_DBG_SLEEP

#define DBGMCU_CR_DBG_STOP

#define DBGMCU_CR_DBG_STANDBY

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP

#define DBGMCU_APB1_FZ_DBG_TIM12_STOP

#define DBGMCU_APB1_FZ_DBG_TIM13_STOP

#define DBGMCU_APB1_FZ_DBG_TIM14_STOP

#define DBGMCU_APB1_FZ_DBG_TIM18_STOP

#define DBGMCU_APB1_FZ_DBG_RTC_STOP

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP

#define DBGMCU_APB2_FZ_DBG_TIM15_STOP

#define DBGMCU_APB2_FZ_DBG_TIM16_STOP

#define DBGMCU_APB2_FZ_DBG_TIM17_STOP

#define DBGMCU_APB2_FZ_DBG_TIM19_STOP

#define DMA_ISR_GIF1

#define DMA_ISR_TCIF1

#define DMA_ISR_HTIF1

#define DMA_ISR_TEIF1

#define DMA_ISR_GIF2

#define DMA_ISR_TCIF2

#define DMA_ISR_HTIF2

#define DMA_ISR_TEIF2

#define DMA_ISR_GIF3

#define DMA_ISR_TCIF3

#define DMA_ISR_HTIF3

#define DMA_ISR_TEIF3

#define DMA_ISR_GIF4

#define DMA_ISR_TCIF4

#define DMA_ISR_HTIF4

#define DMA_ISR_TEIF4

#define DMA_ISR_GIF5

#define DMA_ISR_TCIF5

#define DMA_ISR_HTIF5

#define DMA_ISR_TEIF5

#define DMA_ISR_GIF6

#define DMA_ISR_TCIF6

#define DMA_ISR_HTIF6

#define DMA_ISR_TEIF6

#define DMA_ISR_GIF7

#define DMA_ISR_TCIF7

#define DMA_ISR_HTIF7

#define DMA_ISR_TEIF7

#define DMA_IFCR_CGIF1

#define DMA_IFCR_CTCIF1

#define DMA_IFCR_CHTIF1

#define DMA_IFCR_CTEIF1

#define DMA_IFCR_CGIF2

#define DMA_IFCR_CTCIF2

#define DMA_IFCR_CHTIF2

#define DMA_IFCR_CTEIF2

#define DMA_IFCR_CGIF3

#define DMA_IFCR_CTCIF3

#define DMA_IFCR_CHTIF3

#define DMA_IFCR_CTEIF3

#define DMA_IFCR_CGIF4

#define DMA_IFCR_CTCIF4

#define DMA_IFCR_CHTIF4

#define DMA_IFCR_CTEIF4

#define DMA_IFCR_CGIF5

#define DMA_IFCR_CTCIF5

#define DMA_IFCR_CHTIF5

#define DMA_IFCR_CTEIF5

#define DMA_IFCR_CGIF6

#define DMA_IFCR_CTCIF6

#define DMA_IFCR_CHTIF6

#define DMA_IFCR_CTEIF6

#define DMA_IFCR_CGIF7

#define DMA_IFCR_CTCIF7

#define DMA_IFCR_CHTIF7

#define DMA_IFCR_CTEIF7

#define DMA_CCR_EN

#define DMA_CCR_TCIE

#define DMA_CCR_HTIE

#define DMA_CCR_TEIE

#define DMA_CCR_DIR

#define DMA_CCR_CIRC

#define DMA_CCR_PINC

#define DMA_CCR_MINC

#define DMA_CCR_PSIZE

#define DMA_CCR_PSIZE_0

#define DMA_CCR_PSIZE_1

#define DMA_CCR_MSIZE

#define DMA_CCR_MSIZE_0

#define DMA_CCR_MSIZE_1

#define DMA_CCR_PL

#define DMA_CCR_PL_0

#define DMA_CCR_PL_1

#define DMA_CCR_MEM2MEM

#define DMA_CNDTR_NDT

#define DMA_CPAR_PA

#define DMA_CMAR_MA

#define EXTI_IMR_MR0

#define EXTI_IMR_MR1

#define EXTI_IMR_MR2

#define EXTI_IMR_MR3

#define EXTI_IMR_MR4

#define EXTI_IMR_MR5

#define EXTI_IMR_MR6

#define EXTI_IMR_MR7

#define EXTI_IMR_MR8

#define EXTI_IMR_MR9

#define EXTI_IMR_MR10

#define EXTI_IMR_MR11

#define EXTI_IMR_MR12

#define EXTI_IMR_MR13

#define EXTI_IMR_MR14

#define EXTI_IMR_MR15

#define EXTI_IMR_MR16

#define EXTI_IMR_MR17

#define EXTI_IMR_MR18

#define EXTI_IMR_MR19

#define EXTI_IMR_MR20

#define EXTI_IMR_MR21

#define EXTI_IMR_MR22

#define EXTI_IMR_MR23

#define EXTI_IMR_MR24

#define EXTI_IMR_MR25

#define EXTI_IMR_MR26

#define EXTI_IMR_MR27

#define EXTI_IMR_MR28

#define EXTI_EMR_MR0

#define EXTI_EMR_MR1

#define EXTI_EMR_MR2

#define EXTI_EMR_MR3

#define EXTI_EMR_MR4

#define EXTI_EMR_MR5

#define EXTI_EMR_MR6

#define EXTI_EMR_MR7

#define EXTI_EMR_MR8

#define EXTI_EMR_MR9

#define EXTI_EMR_MR10

#define EXTI_EMR_MR11

#define EXTI_EMR_MR12

#define EXTI_EMR_MR13

#define EXTI_EMR_MR14

#define EXTI_EMR_MR15

#define EXTI_EMR_MR16

#define EXTI_EMR_MR17

#define EXTI_EMR_MR18

#define EXTI_EMR_MR19

#define EXTI_EMR_MR20

#define EXTI_EMR_MR21

#define EXTI_EMR_MR22

#define EXTI_EMR_MR23

#define EXTI_EMR_MR24

#define EXTI_EMR_MR25

#define EXTI_EMR_MR26

#define EXTI_EMR_MR27

#define EXTI_EMR_MR28

#define EXTI_RTSR_TR0

#define EXTI_RTSR_TR1

#define EXTI_RTSR_TR2

#define EXTI_RTSR_TR3

#define EXTI_RTSR_TR4

#define EXTI_RTSR_TR5

#define EXTI_RTSR_TR6

#define EXTI_RTSR_TR7

#define EXTI_RTSR_TR8

#define EXTI_RTSR_TR9

#define EXTI_RTSR_TR10

#define EXTI_RTSR_TR11

#define EXTI_RTSR_TR12

#define EXTI_RTSR_TR13

#define EXTI_RTSR_TR14

#define EXTI_RTSR_TR15

#define EXTI_RTSR_TR16

#define EXTI_RTSR_TR17

#define EXTI_RTSR_TR18

#define EXTI_RTSR_TR19

#define EXTI_RTSR_TR20

#define EXTI_RTSR_TR21

#define EXTI_RTSR_TR22

#define EXTI_RTSR_TR23

#define EXTI_RTSR_TR24

#define EXTI_RTSR_TR25

#define EXTI_RTSR_TR26

#define EXTI_RTSR_TR27

#define EXTI_RTSR_TR28

#define EXTI_FTSR_TR0

#define EXTI_FTSR_TR1

#define EXTI_FTSR_TR2

#define EXTI_FTSR_TR3

#define EXTI_FTSR_TR4

#define EXTI_FTSR_TR5

#define EXTI_FTSR_TR6

#define EXTI_FTSR_TR7

#define EXTI_FTSR_TR8

#define EXTI_FTSR_TR9

#define EXTI_FTSR_TR10

#define EXTI_FTSR_TR11

#define EXTI_FTSR_TR12

#define EXTI_FTSR_TR13

#define EXTI_FTSR_TR14

#define EXTI_FTSR_TR15

#define EXTI_FTSR_TR16

#define EXTI_FTSR_TR17

#define EXTI_FTSR_TR18

#define EXTI_FTSR_TR19

#define EXTI_FTSR_TR20

#define EXTI_FTSR_TR21

#define EXTI_FTSR_TR22

#define EXTI_FTSR_TR23

#define EXTI_FTSR_TR24

#define EXTI_FTSR_TR25

#define EXTI_FTSR_TR26

#define EXTI_FTSR_TR27

#define EXTI_FTSR_TR28

#define EXTI_SWIER_SWIER0

#define EXTI_SWIER_SWIER1

#define EXTI_SWIER_SWIER2

#define EXTI_SWIER_SWIER3

#define EXTI_SWIER_SWIER4

#define EXTI_SWIER_SWIER5

#define EXTI_SWIER_SWIER6

#define EXTI_SWIER_SWIER7

#define EXTI_SWIER_SWIER8

#define EXTI_SWIER_SWIER9

#define EXTI_SWIER_SWIER10

#define EXTI_SWIER_SWIER11

#define EXTI_SWIER_SWIER12

#define EXTI_SWIER_SWIER13

#define EXTI_SWIER_SWIER14

#define EXTI_SWIER_SWIER15

#define EXTI_SWIER_SWIER16

#define EXTI_SWIER_SWIER17

#define EXTI_SWIER_SWIER18

#define EXTI_SWIER_SWIER19

#define EXTI_SWIER_SWIER20

#define EXTI_SWIER_SWIER21

#define EXTI_SWIER_SWIER22

#define EXTI_SWIER_SWIER23

#define EXTI_SWIER_SWIER24

#define EXTI_SWIER_SWIER25

#define EXTI_SWIER_SWIER26

#define EXTI_SWIER_SWIER27

#define EXTI_SWIER_SWIER28

#define EXTI_PR_PR0

#define EXTI_PR_PR1

#define EXTI_PR_PR2

#define EXTI_PR_PR3

#define EXTI_PR_PR4

#define EXTI_PR_PR5

#define EXTI_PR_PR6

#define EXTI_PR_PR7

#define EXTI_PR_PR8

#define EXTI_PR_PR9

#define EXTI_PR_PR10

#define EXTI_PR_PR11

#define EXTI_PR_PR12

#define EXTI_PR_PR13

#define EXTI_PR_PR14

#define EXTI_PR_PR15

#define EXTI_PR_PR16

#define EXTI_PR_PR17

#define EXTI_PR_PR18

#define EXTI_PR_PR19

#define EXTI_PR_PR20

#define EXTI_PR_PR21

#define EXTI_PR_PR22

#define EXTI_PR_PR23

#define EXTI_PR_PR24

#define EXTI_PR_PR25

#define EXTI_PR_PR26

#define EXTI_PR_PR27

#define EXTI_PR_PR28

#define FLASH_ACR_LATENCY

#define FLASH_ACR_LATENCY_0

#define FLASH_ACR_LATENCY_1

#define FLASH_ACR_HLFCYA

#define FLASH_ACR_PRFTBE

#define FLASH_ACR_PRFTBS

#define FLASH_KEYR_FKEYR

#define FLASH_OPTKEYR_OPTKEYR

#define FLASH_SR_BSY

#define FLASH_SR_PGERR

#define FLASH_SR_WRPERR

#define FLASH_SR_EOP

#define FLASH_CR_PG

#define FLASH_CR_PER

#define FLASH_CR_MER

#define FLASH_CR_OPTPG

#define FLASH_CR_OPTER

#define FLASH_CR_STRT

#define FLASH_CR_LOCK

#define FLASH_CR_OPTWRE

#define FLASH_CR_ERRIE

#define FLASH_CR_EOPIE

#define FLASH_CR_OBL_LAUNCH

#define FLASH_AR_FAR

#define FLASH_OBR_OPTERR

#define FLASH_OBR_RDPRT1

#define FLASH_OBR_RDPRT2

#define FLASH_OBR_USER

#define FLASH_OBR_IWDG_SW

#define FLASH_OBR_nRST_STOP

#define FLASH_OBR_nRST_STDBY

#define FLASH_WRPR_WRP

#define OB_RDP_RDP

#define OB_RDP_nRDP

#define OB_USER_USER

#define OB_USER_nUSER

#define OB_WRP0_WRP0

#define OB_WRP0_nWRP0

#define OB_WRP1_WRP1

#define OB_WRP1_nWRP1

#define OB_WRP2_WRP2

#define OB_WRP2_nWRP2

#define OB_WRP3_WRP3

#define OB_WRP3_nWRP3

#define GPIO_MODER_MODER0

#define GPIO_MODER_MODER0_0

#define GPIO_MODER_MODER0_1

#define GPIO_MODER_MODER1

#define GPIO_MODER_MODER1_0

#define GPIO_MODER_MODER1_1

#define GPIO_MODER_MODER2

#define GPIO_MODER_MODER2_0

#define GPIO_MODER_MODER2_1

#define GPIO_MODER_MODER3

#define GPIO_MODER_MODER3_0

#define GPIO_MODER_MODER3_1

#define GPIO_MODER_MODER4

#define GPIO_MODER_MODER4_0

#define GPIO_MODER_MODER4_1

#define GPIO_MODER_MODER5

#define GPIO_MODER_MODER5_0

#define GPIO_MODER_MODER5_1

#define GPIO_MODER_MODER6

#define GPIO_MODER_MODER6_0

#define GPIO_MODER_MODER6_1

#define GPIO_MODER_MODER7

#define GPIO_MODER_MODER7_0

#define GPIO_MODER_MODER7_1

#define GPIO_MODER_MODER8

#define GPIO_MODER_MODER8_0

#define GPIO_MODER_MODER8_1

#define GPIO_MODER_MODER9

#define GPIO_MODER_MODER9_0

#define GPIO_MODER_MODER9_1

#define GPIO_MODER_MODER10

#define GPIO_MODER_MODER10_0

#define GPIO_MODER_MODER10_1

#define GPIO_MODER_MODER11

#define GPIO_MODER_MODER11_0

#define GPIO_MODER_MODER11_1

#define GPIO_MODER_MODER12

#define GPIO_MODER_MODER12_0

#define GPIO_MODER_MODER12_1

#define GPIO_MODER_MODER13

#define GPIO_MODER_MODER13_0

#define GPIO_MODER_MODER13_1

#define GPIO_MODER_MODER14

#define GPIO_MODER_MODER14_0

#define GPIO_MODER_MODER14_1

#define GPIO_MODER_MODER15

#define GPIO_MODER_MODER15_0

#define GPIO_MODER_MODER15_1

#define GPIO_OTYPER_OT_0

#define GPIO_OTYPER_OT_1

#define GPIO_OTYPER_OT_2

#define GPIO_OTYPER_OT_3

#define GPIO_OTYPER_OT_4

#define GPIO_OTYPER_OT_5

#define GPIO_OTYPER_OT_6

#define GPIO_OTYPER_OT_7

#define GPIO_OTYPER_OT_8

#define GPIO_OTYPER_OT_9

#define GPIO_OTYPER_OT_10

#define GPIO_OTYPER_OT_11

#define GPIO_OTYPER_OT_12

#define GPIO_OTYPER_OT_13

#define GPIO_OTYPER_OT_14

#define GPIO_OTYPER_OT_15

#define GPIO_OSPEEDER_OSPEEDR0

#define GPIO_OSPEEDER_OSPEEDR0_0

#define GPIO_OSPEEDER_OSPEEDR0_1

#define GPIO_OSPEEDER_OSPEEDR1

#define GPIO_OSPEEDER_OSPEEDR1_0

#define GPIO_OSPEEDER_OSPEEDR1_1

#define GPIO_OSPEEDER_OSPEEDR2

#define GPIO_OSPEEDER_OSPEEDR2_0

#define GPIO_OSPEEDER_OSPEEDR2_1

#define GPIO_OSPEEDER_OSPEEDR3

#define GPIO_OSPEEDER_OSPEEDR3_0

#define GPIO_OSPEEDER_OSPEEDR3_1

#define GPIO_OSPEEDER_OSPEEDR4

#define GPIO_OSPEEDER_OSPEEDR4_0

#define GPIO_OSPEEDER_OSPEEDR4_1

#define GPIO_OSPEEDER_OSPEEDR5

#define GPIO_OSPEEDER_OSPEEDR5_0

#define GPIO_OSPEEDER_OSPEEDR5_1

#define GPIO_OSPEEDER_OSPEEDR6

#define GPIO_OSPEEDER_OSPEEDR6_0

#define GPIO_OSPEEDER_OSPEEDR6_1

#define GPIO_OSPEEDER_OSPEEDR7

#define GPIO_OSPEEDER_OSPEEDR7_0

#define GPIO_OSPEEDER_OSPEEDR7_1

#define GPIO_OSPEEDER_OSPEEDR8

#define GPIO_OSPEEDER_OSPEEDR8_0

#define GPIO_OSPEEDER_OSPEEDR8_1

#define GPIO_OSPEEDER_OSPEEDR9

#define GPIO_OSPEEDER_OSPEEDR9_0

#define GPIO_OSPEEDER_OSPEEDR9_1

#define GPIO_OSPEEDER_OSPEEDR10

#define GPIO_OSPEEDER_OSPEEDR10_0

#define GPIO_OSPEEDER_OSPEEDR10_1

#define GPIO_OSPEEDER_OSPEEDR11

#define GPIO_OSPEEDER_OSPEEDR11_0

#define GPIO_OSPEEDER_OSPEEDR11_1

#define GPIO_OSPEEDER_OSPEEDR12

#define GPIO_OSPEEDER_OSPEEDR12_0

#define GPIO_OSPEEDER_OSPEEDR12_1

#define GPIO_OSPEEDER_OSPEEDR13

#define GPIO_OSPEEDER_OSPEEDR13_0

#define GPIO_OSPEEDER_OSPEEDR13_1

#define GPIO_OSPEEDER_OSPEEDR14

#define GPIO_OSPEEDER_OSPEEDR14_0

#define GPIO_OSPEEDER_OSPEEDR14_1

#define GPIO_OSPEEDER_OSPEEDR15

#define GPIO_OSPEEDER_OSPEEDR15_0

#define GPIO_OSPEEDER_OSPEEDR15_1

#define GPIO_PUPDR_PUPDR0

#define GPIO_PUPDR_PUPDR0_0

#define GPIO_PUPDR_PUPDR0_1

#define GPIO_PUPDR_PUPDR1

#define GPIO_PUPDR_PUPDR1_0

#define GPIO_PUPDR_PUPDR1_1

#define GPIO_PUPDR_PUPDR2

#define GPIO_PUPDR_PUPDR2_0

#define GPIO_PUPDR_PUPDR2_1

#define GPIO_PUPDR_PUPDR3

#define GPIO_PUPDR_PUPDR3_0

#define GPIO_PUPDR_PUPDR3_1

#define GPIO_PUPDR_PUPDR4

#define GPIO_PUPDR_PUPDR4_0

#define GPIO_PUPDR_PUPDR4_1

#define GPIO_PUPDR_PUPDR5

#define GPIO_PUPDR_PUPDR5_0

#define GPIO_PUPDR_PUPDR5_1

#define GPIO_PUPDR_PUPDR6

#define GPIO_PUPDR_PUPDR6_0

#define GPIO_PUPDR_PUPDR6_1

#define GPIO_PUPDR_PUPDR7

#define GPIO_PUPDR_PUPDR7_0

#define GPIO_PUPDR_PUPDR7_1

#define GPIO_PUPDR_PUPDR8

#define GPIO_PUPDR_PUPDR8_0

#define GPIO_PUPDR_PUPDR8_1

#define GPIO_PUPDR_PUPDR9

#define GPIO_PUPDR_PUPDR9_0

#define GPIO_PUPDR_PUPDR9_1

#define GPIO_PUPDR_PUPDR10

#define GPIO_PUPDR_PUPDR10_0

#define GPIO_PUPDR_PUPDR10_1

#define GPIO_PUPDR_PUPDR11

#define GPIO_PUPDR_PUPDR11_0

#define GPIO_PUPDR_PUPDR11_1

#define GPIO_PUPDR_PUPDR12

#define GPIO_PUPDR_PUPDR12_0

#define GPIO_PUPDR_PUPDR12_1

#define GPIO_PUPDR_PUPDR13

#define GPIO_PUPDR_PUPDR13_0

#define GPIO_PUPDR_PUPDR13_1

#define GPIO_PUPDR_PUPDR14

#define GPIO_PUPDR_PUPDR14_0

#define GPIO_PUPDR_PUPDR14_1

#define GPIO_PUPDR_PUPDR15

#define GPIO_PUPDR_PUPDR15_0

#define GPIO_PUPDR_PUPDR15_1

#define GPIO_IDR_0

#define GPIO_IDR_1

#define GPIO_IDR_2

#define GPIO_IDR_3

#define GPIO_IDR_4

#define GPIO_IDR_5

#define GPIO_IDR_6

#define GPIO_IDR_7

#define GPIO_IDR_8

#define GPIO_IDR_9

#define GPIO_IDR_10

#define GPIO_IDR_11

#define GPIO_IDR_12

#define GPIO_IDR_13

#define GPIO_IDR_14

#define GPIO_IDR_15

#define GPIO_ODR_0

#define GPIO_ODR_1

#define GPIO_ODR_2

#define GPIO_ODR_3

#define GPIO_ODR_4

#define GPIO_ODR_5

#define GPIO_ODR_6

#define GPIO_ODR_7

#define GPIO_ODR_8

#define GPIO_ODR_9

#define GPIO_ODR_10

#define GPIO_ODR_11

#define GPIO_ODR_12

#define GPIO_ODR_13

#define GPIO_ODR_14

#define GPIO_ODR_15

#define GPIO_BSRR_BS_0

#define GPIO_BSRR_BS_1

#define GPIO_BSRR_BS_2

#define GPIO_BSRR_BS_3

#define GPIO_BSRR_BS_4

#define GPIO_BSRR_BS_5

#define GPIO_BSRR_BS_6

#define GPIO_BSRR_BS_7

#define GPIO_BSRR_BS_8

#define GPIO_BSRR_BS_9

#define GPIO_BSRR_BS_10

#define GPIO_BSRR_BS_11

#define GPIO_BSRR_BS_12

#define GPIO_BSRR_BS_13

#define GPIO_BSRR_BS_14

#define GPIO_BSRR_BS_15

#define GPIO_BSRR_BR_0

#define GPIO_BSRR_BR_1

#define GPIO_BSRR_BR_2

#define GPIO_BSRR_BR_3

#define GPIO_BSRR_BR_4

#define GPIO_BSRR_BR_5

#define GPIO_BSRR_BR_6

#define GPIO_BSRR_BR_7

#define GPIO_BSRR_BR_8

#define GPIO_BSRR_BR_9

#define GPIO_BSRR_BR_10

#define GPIO_BSRR_BR_11

#define GPIO_BSRR_BR_12

#define GPIO_BSRR_BR_13

#define GPIO_BSRR_BR_14

#define GPIO_BSRR_BR_15

#define GPIO_LCKR_LCK0

#define GPIO_LCKR_LCK1

#define GPIO_LCKR_LCK2

#define GPIO_LCKR_LCK3

#define GPIO_LCKR_LCK4

#define GPIO_LCKR_LCK5

#define GPIO_LCKR_LCK6

#define GPIO_LCKR_LCK7

#define GPIO_LCKR_LCK8

#define GPIO_LCKR_LCK9

#define GPIO_LCKR_LCK10

#define GPIO_LCKR_LCK11

#define GPIO_LCKR_LCK12

#define GPIO_LCKR_LCK13

#define GPIO_LCKR_LCK14

#define GPIO_LCKR_LCK15

#define GPIO_LCKR_LCKK

#define GPIO_AFRL_AFRL0

#define GPIO_AFRL_AFRL1

#define GPIO_AFRL_AFRL2

#define GPIO_AFRL_AFRL3

#define GPIO_AFRL_AFRL4

#define GPIO_AFRL_AFRL5

#define GPIO_AFRL_AFRL6

#define GPIO_AFRL_AFRL7

#define GPIO_AFRH_AFRH0

#define GPIO_AFRH_AFRH1

#define GPIO_AFRH_AFRH2

#define GPIO_AFRH_AFRH3

#define GPIO_AFRH_AFRH4

#define GPIO_AFRH_AFRH5

#define GPIO_AFRH_AFRH6

#define GPIO_AFRH_AFRH7

#define GPIO_BRR_BR_0

#define GPIO_BRR_BR_1

#define GPIO_BRR_BR_2

#define GPIO_BRR_BR_3

#define GPIO_BRR_BR_4

#define GPIO_BRR_BR_5

#define GPIO_BRR_BR_6

#define GPIO_BRR_BR_7

#define GPIO_BRR_BR_8

#define GPIO_BRR_BR_9

#define GPIO_BRR_BR_10

#define GPIO_BRR_BR_11

#define GPIO_BRR_BR_12

#define GPIO_BRR_BR_13

#define GPIO_BRR_BR_14

#define GPIO_BRR_BR_15

#define I2C_CR1_PE

#define I2C_CR1_TXIE

#define I2C_CR1_RXIE

#define I2C_CR1_ADDRIE

#define I2C_CR1_NACKIE

#define I2C_CR1_STOPIE

#define I2C_CR1_TCIE

#define I2C_CR1_ERRIE

#define I2C_CR1_DFN

#define I2C_CR1_ANFOFF

#define I2C_CR1_SWRST

#define I2C_CR1_TXDMAEN

#define I2C_CR1_RXDMAEN

#define I2C_CR1_SBC

#define I2C_CR1_NOSTRETCH

#define I2C_CR1_WUPEN

#define I2C_CR1_GCEN

#define I2C_CR1_SMBHEN

#define I2C_CR1_SMBDEN

#define I2C_CR1_ALERTEN

#define I2C_CR1_PECEN

#define I2C_CR2_SADD

#define I2C_CR2_RD_WRN

#define I2C_CR2_ADD10

#define I2C_CR2_HEAD10R

#define I2C_CR2_START

#define I2C_CR2_STOP

#define I2C_CR2_NACK

#define I2C_CR2_NBYTES

#define I2C_CR2_RELOAD

#define I2C_CR2_AUTOEND

#define I2C_CR2_PECBYTE

#define I2C_OAR1_OA1

#define I2C_OAR1_OA1MODE

#define I2C_OAR1_OA1EN

#define I2C_OAR2_OA2

#define I2C_OAR2_OA2MSK

#define I2C_OAR2_OA2EN

#define I2C_TIMINGR_SCLL

#define I2C_TIMINGR_SCLH

#define I2C_TIMINGR_SDADEL

#define I2C_TIMINGR_SCLDEL

#define I2C_TIMINGR_PRESC

#define I2C_TIMEOUTR_TIMEOUTA

#define I2C_TIMEOUTR_TIDLE

#define I2C_TIMEOUTR_TIMOUTEN

#define I2C_TIMEOUTR_TIMEOUTB

#define I2C_TIMEOUTR_TEXTEN

#define I2C_ISR_TXE

#define I2C_ISR_TXIS

#define I2C_ISR_RXNE

#define I2C_ISR_ADDR

#define I2C_ISR_NACKF

#define I2C_ISR_STOPF

#define I2C_ISR_TC

#define I2C_ISR_TCR

#define I2C_ISR_BERR

#define I2C_ISR_ARLO

#define I2C_ISR_OVR

#define I2C_ISR_PECERR

#define I2C_ISR_TIMEOUT

#define I2C_ISR_ALERT

#define I2C_ISR_BUSY

#define I2C_ISR_DIR

#define I2C_ISR_ADDCODE

#define I2C_ICR_ADDRCF

#define I2C_ICR_NACKCF

#define I2C_ICR_STOPCF

#define I2C_ICR_BERRCF

#define I2C_ICR_ARLOCF

#define I2C_ICR_OVRCF

#define I2C_ICR_PECCF

#define I2C_ICR_TIMOUTCF

#define I2C_ICR_ALERTCF

#define I2C_PECR_PEC

#define I2C_RXDR_RXDATA

#define I2C_TXDR_TXDATA

#define IWDG_KR_KEY

#define IWDG_PR_PR

#define IWDG_PR_PR_0

#define IWDG_PR_PR_1

#define IWDG_PR_PR_2

#define IWDG_RLR_RL

#define IWDG_SR_PVU

#define IWDG_SR_RVU

#define IWDG_SR_WVU

#define IWDG_WINR_WIN

#define CEC_CR_CECEN

#define CEC_CR_TXSOM

#define CEC_CR_TXEOM

#define CEC_CFGR_SFT

#define CEC_CFGR_RXTOL

#define CEC_CFGR_BRESTP

#define CEC_CFGR_BREGEN

#define CEC_CFGR_LREGEN

#define CEC_CFGR_SFTOPT

#define CEC_CFGR_BRDNOGEN

#define CEC_CFGR_OAR

#define CEC_CFGR_LSTN

#define CEC_TXDR_TXD

#define CEC_TXDR_RXD

#define CEC_ISR_RXBR

#define CEC_ISR_RXEND

#define CEC_ISR_RXOVR

#define CEC_ISR_BRE

#define CEC_ISR_SBPE

#define CEC_ISR_LBPE

#define CEC_ISR_RXACKE

#define CEC_ISR_ARBLST

#define CEC_ISR_TXBR

#define CEC_ISR_TXEND

#define CEC_ISR_TXUDR

#define CEC_ISR_TXERR

#define CEC_ISR_TXACKE

#define CEC_IER_RXBRIE

#define CEC_IER_RXENDIE

#define CEC_IER_RXOVRIE

#define CEC_IER_BREIEIE

#define CEC_IER_SBPEIE

#define CEC_IER_LBPEIE

#define CEC_IER_RXACKEIE

#define CEC_IER_ARBLSTIE

#define CEC_IER_TXBRIE

#define CEC_IER_TXENDIE

#define CEC_IER_TXUDRIE

#define CEC_IER_TXERRIE

#define CEC_IER_TXACKEIE

#define PWR_CR_LPSDSR

#define PWR_CR_PDDS

#define PWR_CR_CWUF

#define PWR_CR_CSBF

#define PWR_CR_PVDE

#define PWR_CR_PLS

#define PWR_CR_PLS_0

#define PWR_CR_PLS_1

#define PWR_CR_PLS_2

#define PWR_CR_PLS_LEV0

#define PWR_CR_PLS_LEV1

#define PWR_CR_PLS_LEV2

#define PWR_CR_PLS_LEV3

#define PWR_CR_PLS_LEV4

#define PWR_CR_PLS_LEV5

#define PWR_CR_PLS_LEV6

#define PWR_CR_PLS_LEV7

#define PWR_CR_DBP

#define PWR_CR_SDADC1EN

#define PWR_CR_SDADC2EN

#define PWR_CR_SDADC3EN

#define PWR_CSR_WUF

#define PWR_CSR_SBF

#define PWR_CSR_PVDO

#define PWR_CSR_VREFINTRDYF

#define PWR_CSR_EWUP1

#define PWR_CSR_EWUP2

#define PWR_CSR_EWUP3

#define RCC_CR_HSION

#define RCC_CR_HSIRDY

#define RCC_CR_HSITRIM

#define RCC_CR_HSITRIM_0

#define RCC_CR_HSITRIM_1

#define RCC_CR_HSITRIM_2

#define RCC_CR_HSITRIM_3

#define RCC_CR_HSITRIM_4

#define RCC_CR_HSICAL

#define RCC_CR_HSICAL_0

#define RCC_CR_HSICAL_1

#define RCC_CR_HSICAL_2

#define RCC_CR_HSICAL_3

#define RCC_CR_HSICAL_4

#define RCC_CR_HSICAL_5

#define RCC_CR_HSICAL_6

#define RCC_CR_HSICAL_7

#define RCC_CR_HSEON

#define RCC_CR_HSERDY

#define RCC_CR_HSEBYP

#define RCC_CR_CSSON

#define RCC_CR_PLLON

#define RCC_CR_PLLRDY

#define RCC_CFGR_SW

#define RCC_CFGR_SW_0

#define RCC_CFGR_SW_1

#define RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_PLL

#define RCC_CFGR_SWS

#define RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_PLL

#define RCC_CFGR_HPRE

#define RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV2

#define RCC_CFGR_HPRE_DIV4

#define RCC_CFGR_HPRE_DIV8

#define RCC_CFGR_HPRE_DIV16

#define RCC_CFGR_HPRE_DIV64

#define RCC_CFGR_HPRE_DIV128

#define RCC_CFGR_HPRE_DIV256

#define RCC_CFGR_HPRE_DIV512

#define RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1_0

#define RCC_CFGR_PPRE1_1

#define RCC_CFGR_PPRE1_2

#define RCC_CFGR_PPRE1_DIV1

#define RCC_CFGR_PPRE1_DIV2

#define RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV8

#define RCC_CFGR_PPRE1_DIV16

#define RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2_0

#define RCC_CFGR_PPRE2_1

#define RCC_CFGR_PPRE2_2

#define RCC_CFGR_PPRE2_DIV1

#define RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV4

#define RCC_CFGR_PPRE2_DIV8

#define RCC_CFGR_PPRE2_DIV16

#define RCC_CFGR_ADCPRE

#define RCC_CFGR_ADCPRE_0

#define RCC_CFGR_ADCPRE_1

#define RCC_CFGR_ADCPRE_DIV2

#define RCC_CFGR_ADCPRE_DIV4

#define RCC_CFGR_ADCPRE_DIV6

#define RCC_CFGR_ADCPRE_DIV8

#define RCC_CFGR_PLLSRC

#define RCC_CFGR_PLLXTPRE

#define RCC_CFGR_PLLMULL

#define RCC_CFGR_PLLMULL_0

#define RCC_CFGR_PLLMULL_1

#define RCC_CFGR_PLLMULL_2

#define RCC_CFGR_PLLMULL_3

#define RCC_CFGR_PLLSRC_HSI_Div2

#define RCC_CFGR_PLLSRC_PREDIV1

#define RCC_CFGR_PLLXTPRE_PREDIV1

#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2

#define RCC_CFGR_PLLMULL2

#define RCC_CFGR_PLLMULL3

#define RCC_CFGR_PLLMULL4

#define RCC_CFGR_PLLMULL5

#define RCC_CFGR_PLLMULL6

#define RCC_CFGR_PLLMULL7

#define RCC_CFGR_PLLMULL8

#define RCC_CFGR_PLLMULL9

#define RCC_CFGR_PLLMULL10

#define RCC_CFGR_PLLMULL11

#define RCC_CFGR_PLLMULL12

#define RCC_CFGR_PLLMULL13

#define RCC_CFGR_PLLMULL14

#define RCC_CFGR_PLLMULL15

#define RCC_CFGR_PLLMULL16

#define RCC_CFGR_USBPRE

#define RCC_CFGR_MCO

#define RCC_CFGR_MCO_0

#define RCC_CFGR_MCO_1

#define RCC_CFGR_MCO_2

#define RCC_CFGR_MCO_NOCLOCK

#define RCC_CFGR_MCO_LSI

#define RCC_CFGR_MCO_LSE

#define RCC_CFGR_MCO_SYSCLK

#define RCC_CFGR_MCO_HSI

#define RCC_CFGR_MCO_HSE

#define RCC_CFGR_MCO_PLL

#define RCC_CFGR_SDADCPRE

#define RCC_CFGR_SDADCPRE_0

#define RCC_CFGR_SDADCPRE_1

#define RCC_CFGR_SDADCPRE_2

#define RCC_CFGR_SDADCPRE_3

#define RCC_CFGR_SDADCPRE_4

#define RCC_CFGR_SDADCPRE_DIV1

#define RCC_CFGR_SDADCPRE_DIV2

#define RCC_CFGR_SDADCPRE_DIV4

#define RCC_CFGR_SDADCPRE_DIV6

#define RCC_CFGR_SDADCPRE_DIV8

#define RCC_CFGR_SDADCPRE_DIV10

#define RCC_CFGR_SDADCPRE_DIV12

#define RCC_CFGR_SDADCPRE_DIV14

#define RCC_CFGR_SDADCPRE_DIV16

#define RCC_CFGR_SDADCPRE_DIV20

#define RCC_CFGR_SDADCPRE_DIV24

#define RCC_CFGR_SDADCPRE_DIV28

#define RCC_CFGR_SDADCPRE_DIV32

#define RCC_CFGR_SDADCPRE_DIV36

#define RCC_CFGR_SDADCPRE_DIV40

#define RCC_CFGR_SDADCPRE_DIV44

#define RCC_CFGR_SDADCPRE_DIV48

#define RCC_CIR_LSIRDYF

#define RCC_CIR_LSERDYF

#define RCC_CIR_HSIRDYF

#define RCC_CIR_HSERDYF

#define RCC_CIR_PLLRDYF

#define RCC_CIR_CSSF

#define RCC_CIR_LSIRDYIE

#define RCC_CIR_LSERDYIE

#define RCC_CIR_HSIRDYIE

#define RCC_CIR_HSERDYIE

#define RCC_CIR_PLLRDYIE

#define RCC_CIR_LSIRDYC

#define RCC_CIR_LSERDYC

#define RCC_CIR_HSIRDYC

#define RCC_CIR_HSERDYC

#define RCC_CIR_PLLRDYC

#define RCC_CIR_CSSC

#define RCC_APB2RSTR_SYSCFGRST

#define RCC_APB2RSTR_ADC1RST

#define RCC_APB2RSTR_SPI1RST

#define RCC_APB2RSTR_USART1RST

#define RCC_APB2RSTR_TIM15RST

#define RCC_APB2RSTR_TIM16RST

#define RCC_APB2RSTR_TIM17RST

#define RCC_APB2RSTR_TIM19RST

#define RCC_APB2RSTR_SDADC1RST

#define RCC_APB2RSTR_SDADC2RST

#define RCC_APB2RSTR_SDADC3RST

#define RCC_APB1RSTR_TIM2RST

#define RCC_APB1RSTR_TIM3RST

#define RCC_APB1RSTR_TIM4RST

#define RCC_APB1RSTR_TIM5RST

#define RCC_APB1RSTR_TIM6RST

#define RCC_APB1RSTR_TIM7RST

#define RCC_APB1RSTR_TIM12RST

#define RCC_APB1RSTR_TIM13RST

#define RCC_APB1RSTR_TIM14RST

#define RCC_APB1RSTR_TIM18RST

#define RCC_APB1RSTR_WWDGRST

#define RCC_APB1RSTR_SPI2RST

#define RCC_APB1RSTR_SPI3RST

#define RCC_APB1RSTR_USART2RST

#define RCC_APB1RSTR_USART3RST

#define RCC_APB1RSTR_I2C1RST

#define RCC_APB1RSTR_I2C2RST

#define RCC_APB1RSTR_USBRST

#define RCC_APB1RSTR_CAN1RST

#define RCC_APB1RSTR_DAC2RST

#define RCC_APB1RSTR_PWRRST

#define RCC_APB1RSTR_DAC1RST

#define RCC_APB1RSTR_CECRST

#define RCC_AHBENR_DMA1EN

#define RCC_AHBENR_DMA2EN

#define RCC_AHBENR_SRAMEN

#define RCC_AHBENR_FLITFEN

#define RCC_AHBENR_CRCEN

#define RCC_AHBENR_GPIOAEN

#define RCC_AHBENR_GPIOBEN

#define RCC_AHBENR_GPIOCEN

#define RCC_AHBENR_GPIODEN

#define RCC_AHBENR_GPIOEEN

#define RCC_AHBENR_GPIOFEN

#define RCC_AHBENR_TSEN

#define RCC_APB2ENR_SYSCFGEN

#define RCC_APB2ENR_ADC1EN

#define RCC_APB2ENR_SPI1EN

#define RCC_APB2ENR_USART1EN

#define RCC_APB2ENR_TIM15EN

#define RCC_APB2ENR_TIM16EN

#define RCC_APB2ENR_TIM17EN

#define RCC_APB2ENR_TIM19EN

#define RCC_APB2ENR_SDADC1EN

#define RCC_APB2ENR_SDADC2EN

#define RCC_APB2ENR_SDADC3EN

#define RCC_APB1ENR_TIM2EN

#define RCC_APB1ENR_TIM3EN

#define RCC_APB1ENR_TIM4EN

#define RCC_APB1ENR_TIM5EN

#define RCC_APB1ENR_TIM6EN

#define RCC_APB1ENR_TIM7EN

#define RCC_APB1ENR_TIM12EN

#define RCC_APB1ENR_TIM13EN

#define RCC_APB1ENR_TIM14EN

#define RCC_APB1ENR_TIM18EN

#define RCC_APB1ENR_WWDGEN

#define RCC_APB1ENR_SPI2EN

#define RCC_APB1ENR_SPI3EN

#define RCC_APB1ENR_USART2EN

#define RCC_APB1ENR_USART3EN

#define RCC_APB1ENR_I2C1EN

#define RCC_APB1ENR_I2C2EN

#define RCC_APB1ENR_USBEN

#define RCC_APB1ENR_CAN1EN

#define RCC_APB1ENR_DAC2EN

#define RCC_APB1ENR_PWREN

#define RCC_APB1ENR_DAC1EN

#define RCC_APB1ENR_CECEN

#define RCC_BDCR_LSEON

#define RCC_BDCR_LSERDY

#define RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEDRV

#define RCC_BDCR_LSEDRV_0

#define RCC_BDCR_LSEDRV_1

#define RCC_BDCR_RTCSEL

#define RCC_BDCR_RTCSEL_0

#define RCC_BDCR_RTCSEL_1

#define RCC_BDCR_RTCSEL_NOCLOCK

#define RCC_BDCR_RTCSEL_LSE

#define RCC_BDCR_RTCSEL_LSI

#define RCC_BDCR_RTCSEL_HSE

#define RCC_BDCR_RTCEN

#define RCC_BDCR_BDRST

#define RCC_CSR_LSION

#define RCC_CSR_LSIRDY

#define RCC_CSR_V18PWRRSTF

#define RCC_CSR_RMVF

#define RCC_CSR_OBL

#define RCC_CSR_PINRSTF

#define RCC_CSR_PORRSTF

#define RCC_CSR_SFTRSTF

#define RCC_CSR_IWDGRSTF

#define RCC_CSR_WWDGRSTF

#define RCC_CSR_LPWRRSTF

#define RCC_AHBRSTR_GPIOARST

#define RCC_AHBRSTR_GPIOBRST

#define RCC_AHBRSTR_GPIOCRST

#define RCC_AHBRSTR_GPIODRST

#define RCC_AHBRSTR_GPIOFRST

#define RCC_AHBRSTR_TSRST

#define RCC_CFGR2_PREDIV1

#define RCC_CFGR2_PREDIV1_0

#define RCC_CFGR2_PREDIV1_1

#define RCC_CFGR2_PREDIV1_2

#define RCC_CFGR2_PREDIV1_3

#define RCC_CFGR2_PREDIV1_DIV1

#define RCC_CFGR2_PREDIV1_DIV2

#define RCC_CFGR2_PREDIV1_DIV3

#define RCC_CFGR2_PREDIV1_DIV4

#define RCC_CFGR2_PREDIV1_DIV5

#define RCC_CFGR2_PREDIV1_DIV6

#define RCC_CFGR2_PREDIV1_DIV7

#define RCC_CFGR2_PREDIV1_DIV8

#define RCC_CFGR2_PREDIV1_DIV9

#define RCC_CFGR2_PREDIV1_DIV10

#define RCC_CFGR2_PREDIV1_DIV11

#define RCC_CFGR2_PREDIV1_DIV12

#define RCC_CFGR2_PREDIV1_DIV13

#define RCC_CFGR2_PREDIV1_DIV14

#define RCC_CFGR2_PREDIV1_DIV15

#define RCC_CFGR2_PREDIV1_DIV16

#define RCC_CFGR3_USART1SW

#define RCC_CFGR3_USART1SW_0

#define RCC_CFGR3_USART1SW_1

#define RCC_CFGR3_I2CSW

#define RCC_CFGR3_I2C1SW

#define RCC_CFGR3_I2C2SW

#define RCC_CFGR3_CECSW

#define RCC_CFGR3_USART2SW

#define RCC_CFGR3_USART2SW_0

#define RCC_CFGR3_USART2SW_1

#define RCC_CFGR3_USART3SW

#define RCC_CFGR3_USART3SW_0

#define RCC_CFGR3_USART3SW_1

#define RTC_TR_PM

#define RTC_TR_HT

#define RTC_TR_HT_0

#define RTC_TR_HT_1

#define RTC_TR_HU

#define RTC_TR_HU_0

#define RTC_TR_HU_1

#define RTC_TR_HU_2

#define RTC_TR_HU_3

#define RTC_TR_MNT

#define RTC_TR_MNT_0

#define RTC_TR_MNT_1

#define RTC_TR_MNT_2

#define RTC_TR_MNU

#define RTC_TR_MNU_0

#define RTC_TR_MNU_1

#define RTC_TR_MNU_2

#define RTC_TR_MNU_3

#define RTC_TR_ST

#define RTC_TR_ST_0

#define RTC_TR_ST_1

#define RTC_TR_ST_2

#define RTC_TR_SU

#define RTC_TR_SU_0

#define RTC_TR_SU_1

#define RTC_TR_SU_2

#define RTC_TR_SU_3

#define RTC_DR_YT

#define RTC_DR_YT_0

#define RTC_DR_YT_1

#define RTC_DR_YT_2

#define RTC_DR_YT_3

#define RTC_DR_YU

#define RTC_DR_YU_0

#define RTC_DR_YU_1

#define RTC_DR_YU_2

#define RTC_DR_YU_3

#define RTC_DR_WDU

#define RTC_DR_WDU_0

#define RTC_DR_WDU_1

#define RTC_DR_WDU_2

#define RTC_DR_MT

#define RTC_DR_MU

#define RTC_DR_MU_0

#define RTC_DR_MU_1

#define RTC_DR_MU_2

#define RTC_DR_MU_3

#define RTC_DR_DT

#define RTC_DR_DT_0

#define RTC_DR_DT_1

#define RTC_DR_DU

#define RTC_DR_DU_0

#define RTC_DR_DU_1

#define RTC_DR_DU_2

#define RTC_DR_DU_3

#define RTC_CR_COE

#define RTC_CR_OSEL

#define RTC_CR_OSEL_0

#define RTC_CR_OSEL_1

#define RTC_CR_POL

#define RTC_CR_COSEL

#define RTC_CR_BCK

#define RTC_CR_SUB1H

#define RTC_CR_ADD1H

#define RTC_CR_TSIE

#define RTC_CR_WUTIE

#define RTC_CR_ALRBIE

#define RTC_CR_ALRAIE

#define RTC_CR_TSE

#define RTC_CR_WUTE

#define RTC_CR_ALRBE

#define RTC_CR_ALRAE

#define RTC_CR_FMT

#define RTC_CR_BYPSHAD

#define RTC_CR_REFCKON

#define RTC_CR_TSEDGE

#define RTC_CR_WUCKSEL

#define RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_2

#define RTC_ISR_RECALPF

#define RTC_ISR_TAMP3F

#define RTC_ISR_TAMP2F

#define RTC_ISR_TAMP1F

#define RTC_ISR_TSOVF

#define RTC_ISR_TSF

#define RTC_ISR_WUTF

#define RTC_ISR_ALRBF

#define RTC_ISR_ALRAF

#define RTC_ISR_INIT

#define RTC_ISR_INITF

#define RTC_ISR_RSF

#define RTC_ISR_INITS

#define RTC_ISR_SHPF

#define RTC_ISR_WUTWF

#define RTC_ISR_ALRBWF

#define RTC_ISR_ALRAWF

#define RTC_PRER_PREDIV_A

#define RTC_PRER_PREDIV_S

#define RTC_WUTR_WUT

#define RTC_ALRMAR_MSK4

#define RTC_ALRMAR_WDSEL

#define RTC_ALRMAR_DT

#define RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DU

#define RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_3

#define RTC_ALRMAR_MSK3

#define RTC_ALRMAR_PM

#define RTC_ALRMAR_HT

#define RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HU

#define RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_3

#define RTC_ALRMAR_MSK2

#define RTC_ALRMAR_MNT

#define RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNU

#define RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MSK1

#define RTC_ALRMAR_ST

#define RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_2

#define RTC_ALRMAR_SU

#define RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_3

#define RTC_ALRMBR_MSK4

#define RTC_ALRMBR_WDSEL

#define RTC_ALRMBR_DT

#define RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DU

#define RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_3

#define RTC_ALRMBR_MSK3

#define RTC_ALRMBR_PM

#define RTC_ALRMBR_HT

#define RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HU

#define RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_3

#define RTC_ALRMBR_MSK2

#define RTC_ALRMBR_MNT

#define RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNU

#define RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MSK1

#define RTC_ALRMBR_ST

#define RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_2

#define RTC_ALRMBR_SU

#define RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_3

#define RTC_WPR_KEY

#define RTC_SSR_SS

#define RTC_SHIFTR_SUBFS

#define RTC_SHIFTR_ADD1S

#define RTC_TSTR_PM

#define RTC_TSTR_HT

#define RTC_TSTR_HT_0

#define RTC_TSTR_HT_1

#define RTC_TSTR_HU

#define RTC_TSTR_HU_0

#define RTC_TSTR_HU_1

#define RTC_TSTR_HU_2

#define RTC_TSTR_HU_3

#define RTC_TSTR_MNT

#define RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_2

#define RTC_TSTR_MNU

#define RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_3

#define RTC_TSTR_ST

#define RTC_TSTR_ST_0

#define RTC_TSTR_ST_1

#define RTC_TSTR_ST_2

#define RTC_TSTR_SU

#define RTC_TSTR_SU_0

#define RTC_TSTR_SU_1

#define RTC_TSTR_SU_2

#define RTC_TSTR_SU_3

#define RTC_TSDR_WDU

#define RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_2

#define RTC_TSDR_MT

#define RTC_TSDR_MU

#define RTC_TSDR_MU_0

#define RTC_TSDR_MU_1

#define RTC_TSDR_MU_2

#define RTC_TSDR_MU_3

#define RTC_TSDR_DT

#define RTC_TSDR_DT_0

#define RTC_TSDR_DT_1

#define RTC_TSDR_DU

#define RTC_TSDR_DU_0

#define RTC_TSDR_DU_1

#define RTC_TSDR_DU_2

#define RTC_TSDR_DU_3

#define RTC_TSSSR_SS

#define RTC_CALR_CALP

#define RTC_CALR_CALW8

#define RTC_CALR_CALW16

#define RTC_CALR_CALM

#define RTC_CALR_CALM_0

#define RTC_CALR_CALM_1

#define RTC_CALR_CALM_2

#define RTC_CALR_CALM_3

#define RTC_CALR_CALM_4

#define RTC_CALR_CALM_5

#define RTC_CALR_CALM_6

#define RTC_CALR_CALM_7

#define RTC_CALR_CALM_8

#define RTC_TAFCR_ALARMOUTTYPE

#define RTC_TAFCR_TAMPPUDIS

#define RTC_TAFCR_TAMPPRCH

#define RTC_TAFCR_TAMPPRCH_0

#define RTC_TAFCR_TAMPPRCH_1

#define RTC_TAFCR_TAMPFLT

#define RTC_TAFCR_TAMPFLT_0

#define RTC_TAFCR_TAMPFLT_1

#define RTC_TAFCR_TAMPFREQ

#define RTC_TAFCR_TAMPFREQ_0

#define RTC_TAFCR_TAMPFREQ_1

#define RTC_TAFCR_TAMPFREQ_2

#define RTC_TAFCR_TAMPTS

#define RTC_TAFCR_TAMP3TRG

#define RTC_TAFCR_TAMP3E

#define RTC_TAFCR_TAMP2TRG

#define RTC_TAFCR_TAMP2E

#define RTC_TAFCR_TAMPIE

#define RTC_TAFCR_TAMP1TRG

#define RTC_TAFCR_TAMP1E

#define RTC_ALRMASSR_MASKSS

#define RTC_ALRMASSR_MASKSS_0

#define RTC_ALRMASSR_MASKSS_1

#define RTC_ALRMASSR_MASKSS_2

#define RTC_ALRMASSR_MASKSS_3

#define RTC_ALRMASSR_SS

#define RTC_ALRMBSSR_MASKSS

#define RTC_ALRMBSSR_MASKSS_0

#define RTC_ALRMBSSR_MASKSS_1

#define RTC_ALRMBSSR_MASKSS_2

#define RTC_ALRMBSSR_MASKSS_3

#define RTC_ALRMBSSR_SS

#define RTC_BKP0R

#define RTC_BKP1R

#define RTC_BKP2R

#define RTC_BKP3R

#define RTC_BKP4R

#define RTC_BKP5R

#define RTC_BKP6R

#define RTC_BKP7R

#define RTC_BKP8R

#define RTC_BKP9R

#define RTC_BKP10R

#define RTC_BKP11R

#define RTC_BKP12R

#define RTC_BKP13R

#define RTC_BKP14R

#define RTC_BKP15R

#define RTC_BKP16R

#define RTC_BKP17R

#define RTC_BKP18R

#define RTC_BKP19R

#define RTC_BKP20R

#define RTC_BKP21R

#define RTC_BKP22R

#define RTC_BKP23R

#define RTC_BKP24R

#define RTC_BKP25R

#define RTC_BKP26R

#define RTC_BKP27R

#define RTC_BKP28R

#define RTC_BKP29R

#define RTC_BKP30R

#define RTC_BKP31R

#define SDADC_CR1_EOCALIE

#define SDADC_CR1_JEOCIE

#define SDADC_CR1_JOVRIE

#define SDADC_CR1_REOCIE

#define SDADC_CR1_ROVRIE

#define SDADC_CR1_REFV

#define SDADC_CR1_REFV_0

#define SDADC_CR1_REFV_1

#define SDADC_CR1_SLOWCK

#define SDADC_CR1_SBI

#define SDADC_CR1_PDI

#define SDADC_CR1_JSYNC

#define SDADC_CR1_RSYNC

#define SDADC_CR1_JDMAEN

#define SDADC_CR1_RDMAEN

#define SDADC_CR1_INIT

#define SDADC_CR2_ADON

#define SDADC_CR2_CALIBCNT

#define SDADC_CR2_CALIBCNT_0

#define SDADC_CR2_CALIBCNT_1

#define SDADC_CR2_STARTCALIB

#define SDADC_CR2_JCONT

#define SDADC_CR2_JDS

#define SDADC_CR2_JEXTSEL

#define SDADC_CR2_JEXTSEL_0

#define SDADC_CR2_JEXTSEL_1

#define SDADC_CR2_JEXTSEL_2

#define SDADC_CR2_JEXTSEL_3

#define SDADC_CR2_JEXTEN

#define SDADC_CR2_JEXTEN_0

#define SDADC_CR2_JEXTEN_1

#define SDADC_CR2_JSWSTART

#define SDADC_CR2_RCH

#define SDADC_CR2_RCH_0

#define SDADC_CR2_RCH_1

#define SDADC_CR2_RCH_2

#define SDADC_CR2_RCH_3

#define SDADC_CR2_RCONT

#define SDADC_CR2_RSWSTART

#define SDADC_CR2_FAST

#define SDADC_ISR_EOCALF

#define SDADC_ISR_JEOCF

#define SDADC_ISR_JOVRF

#define SDADC_ISR_REOCF

#define SDADC_ISR_ROVRF

#define SDADC_ISR_CALIBIP

#define SDADC_ISR_JCIP

#define SDADC_ISR_RCIP

#define SDADC_ISR_STABIP

#define SDADC_ISR_INITRDY

#define SDADC_ISR_CLREOCALF

#define SDADC_ISR_CLRJOVRF

#define SDADC_ISR_CLRROVRF

#define SDADC_JCHGR_JCHG

#define SDADC_JCHGR_JCHG_0

#define SDADC_JCHGR_JCHG_1

#define SDADC_JCHGR_JCHG_2

#define SDADC_JCHGR_JCHG_3

#define SDADC_JCHGR_JCHG_4

#define SDADC_JCHGR_JCHG_5

#define SDADC_JCHGR_JCHG_6

#define SDADC_JCHGR_JCHG_7

#define SDADC_JCHGR_JCHG_8

#define SDADC_CONF0R_OFFSET0

#define SDADC_CONF0R_GAIN0

#define SDADC_CONF0R_GAIN0_0

#define SDADC_CONF0R_GAIN0_1

#define SDADC_CONF0R_GAIN0_2

#define SDADC_CONF0R_SE0

#define SDADC_CONF0R_SE0_0

#define SDADC_CONF0R_SE0_1

#define SDADC_CONF0R_COMMON0

#define SDADC_CONF0R_COMMON0_0

#define SDADC_CONF0R_COMMON0_1

#define SDADC_CONF1R_OFFSET1

#define SDADC_CONF1R_GAIN1

#define SDADC_CONF1R_GAIN1_0

#define SDADC_CONF1R_GAIN1_1

#define SDADC_CONF1R_GAIN1_2

#define SDADC_CONF1R_SE1

#define SDADC_CONF1R_SE1_0

#define SDADC_CONF1R_SE1_1

#define SDADC_CONF1R_COMMON1

#define SDADC_CONF1R_COMMON1_0

#define SDADC_CONF1R_COMMON1_1

#define SDADC_CONF2R_OFFSET2

#define SDADC_CONF2R_GAIN2

#define SDADC_CONF2R_GAIN2_0

#define SDADC_CONF2R_GAIN2_1

#define SDADC_CONF2R_GAIN2_2

#define SDADC_CONF2R_SE2

#define SDADC_CONF2R_SE2_0

#define SDADC_CONF2R_SE2_1

#define SDADC_CONF2R_COMMON2

#define SDADC_CONF2R_COMMON2_0

#define SDADC_CONF2R_COMMON2_1

#define SDADC_CONFCHR1_CONFCH0

#define SDADC_CONFCHR1_CONFCH1

#define SDADC_CONFCHR1_CONFCH2

#define SDADC_CONFCHR1_CONFCH3

#define SDADC_CONFCHR1_CONFCH4

#define SDADC_CONFCHR1_CONFCH5

#define SDADC_CONFCHR1_CONFCH6

#define SDADC_CONFCHR1_CONFCH7

#define SDADC_CONFCHR2_CONFCH8

#define SDADC_JDATAR_JDATA

#define SDADC_JDATAR_JDATACH

#define SDADC_JDATAR_JDATACH_0

#define SDADC_JDATAR_JDATACH_1

#define SDADC_JDATAR_JDATACH_2

#define SDADC_JDATAR_JDATACH_3

#define SDADC_RDATAR_RDATA

#define SDADC_JDATA12R_JDATA2

#define SDADC_JDATA12R_JDATA1

#define SDADC_RDATA12R_RDATA2

#define SDADC_RDATA12R_RDATA1

#define SDADC_JDATA13R_JDATA3

#define SDADC_JDATA13R_JDATA1

#define SDADC_RDATA13R_RDATA3

#define SDADC_RDATA13R_RDATA1

#define SPI_CR1_CPHA

#define SPI_CR1_CPOL

#define SPI_CR1_MSTR

#define SPI_CR1_BR

#define SPI_CR1_BR_0

#define SPI_CR1_BR_1

#define SPI_CR1_BR_2

#define SPI_CR1_SPE

#define SPI_CR1_LSBFIRST

#define SPI_CR1_SSI

#define SPI_CR1_SSM

#define SPI_CR1_RXONLY

#define SPI_CR1_CRCL

#define SPI_CR1_CRCNEXT

#define SPI_CR1_CRCEN

#define SPI_CR1_BIDIOE

#define SPI_CR1_BIDIMODE

#define SPI_CR2_RXDMAEN

#define SPI_CR2_TXDMAEN

#define SPI_CR2_SSOE

#define SPI_CR2_NSSP

#define SPI_CR2_FRF

#define SPI_CR2_ERRIE

#define SPI_CR2_RXNEIE

#define SPI_CR2_TXEIE

#define SPI_CR2_DS

#define SPI_CR2_DS_0

#define SPI_CR2_DS_1

#define SPI_CR2_DS_2

#define SPI_CR2_DS_3

#define SPI_CR2_FRXTH

#define SPI_CR2_LDMARX

#define SPI_CR2_LDMATX

#define SPI_SR_RXNE

#define SPI_SR_TXE

#define SPI_SR_CHSIDE

#define SPI_SR_UDR

#define SPI_SR_CRCERR

#define SPI_SR_MODF

#define SPI_SR_OVR

#define SPI_SR_BSY

#define SPI_SR_FRE

#define SPI_SR_FRLVL

#define SPI_SR_FRLVL_0

#define SPI_SR_FRLVL_1

#define SPI_SR_FTLVL

#define SPI_SR_FTLVL_0

#define SPI_SR_FTLVL_1

#define SPI_DR_DR

#define SPI_CRCPR_CRCPOLY

#define SPI_RXCRCR_RXCRC

#define SPI_TXCRCR_TXCRC

#define SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SMOD

#define SPI_I2SPR_I2SDIV

#define SPI_I2SPR_ODD

#define SPI_I2SPR_MCKOE

#define SYSCFG_CFGR1_MEM_MODE

#define SYSCFG_CFGR1_MEM_MODE_0

#define SYSCFG_CFGR1_MEM_MODE_1

#define SYSCFG_CFGR1_TIM16_DMA_RMP

#define SYSCFG_CFGR1_TIM17_DMA_RMP

#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP

#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP

#define SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP

#define SYSCFG_CFGR1_I2C_FMP_PB6

#define SYSCFG_CFGR1_I2C_FMP_PB7

#define SYSCFG_CFGR1_I2C_FMP_PB8

#define SYSCFG_CFGR1_I2C_FMP_PB9

#define SYSCFG_CFGR1_I2C_FMP_I2C1

#define SYSCFG_CFGR1_I2C_FMP_I2C2

#define SYSCFG_CFGR1_VBAT

#define SYSCFG_CFGR1_FPU_IE

#define SYSCFG_CFGR1_FPU_IE_0

#define SYSCFG_CFGR1_FPU_IE_1

#define SYSCFG_CFGR1_FPU_IE_2

#define SYSCFG_CFGR1_FPU_IE_3

#define SYSCFG_CFGR1_FPU_IE_4

#define SYSCFG_CFGR1_FPU_IE_5

#define SYSCFG_EXTICR1_EXTI0

#define SYSCFG_EXTICR1_EXTI1

#define SYSCFG_EXTICR1_EXTI2

#define SYSCFG_EXTICR1_EXTI3

* @brief EXTI0 configuration

#define SYSCFG_EXTICR1_EXTI0_PA

#define SYSCFG_EXTICR1_EXTI0_PB

#define SYSCFG_EXTICR1_EXTI0_PC

#define SYSCFG_EXTICR1_EXTI0_PD

#define SYSCFG_EXTICR1_EXTI0_PE

#define SYSCFG_EXTICR1_EXTI0_PF

* @brief EXTI1 configuration

#define SYSCFG_EXTICR1_EXTI1_PA

#define SYSCFG_EXTICR1_EXTI1_PB

#define SYSCFG_EXTICR1_EXTI1_PC

#define SYSCFG_EXTICR1_EXTI1_PD

#define SYSCFG_EXTICR1_EXTI1_PE

#define SYSCFG_EXTICR1_EXTI1_PF

* @brief EXTI2 configuration

#define SYSCFG_EXTICR1_EXTI2_PA

#define SYSCFG_EXTICR1_EXTI2_PB

#define SYSCFG_EXTICR1_EXTI2_PC

#define SYSCFG_EXTICR1_EXTI2_PD

#define SYSCFG_EXTICR1_EXTI2_PE

#define SYSCFG_EXTICR1_EXTI2_PF

* @brief EXTI3 configuration

#define SYSCFG_EXTICR1_EXTI3_PA

#define SYSCFG_EXTICR1_EXTI3_PB

#define SYSCFG_EXTICR1_EXTI3_PC

#define SYSCFG_EXTICR1_EXTI3_PD

#define SYSCFG_EXTICR1_EXTI3_PE

#define SYSCFG_EXTICR2_EXTI4

#define SYSCFG_EXTICR2_EXTI5

#define SYSCFG_EXTICR2_EXTI6

#define SYSCFG_EXTICR2_EXTI7

* @brief EXTI4 configuration

#define SYSCFG_EXTICR2_EXTI4_PA

#define SYSCFG_EXTICR2_EXTI4_PB

#define SYSCFG_EXTICR2_EXTI4_PC

#define SYSCFG_EXTICR2_EXTI4_PD

#define SYSCFG_EXTICR2_EXTI4_PE

#define SYSCFG_EXTICR2_EXTI4_PF

* @brief EXTI5 configuration

#define SYSCFG_EXTICR2_EXTI5_PA

#define SYSCFG_EXTICR2_EXTI5_PB

#define SYSCFG_EXTICR2_EXTI5_PC

#define SYSCFG_EXTICR2_EXTI5_PD

#define SYSCFG_EXTICR2_EXTI5_PE

* @brief EXTI6 configuration

#define SYSCFG_EXTICR2_EXTI6_PA

#define SYSCFG_EXTICR2_EXTI6_PB

#define SYSCFG_EXTICR2_EXTI6_PC

#define SYSCFG_EXTICR2_EXTI6_PD

#define SYSCFG_EXTICR2_EXTI6_PE

#define SYSCFG_EXTICR2_EXTI6_PF

* @brief EXTI7 configuration

#define SYSCFG_EXTICR2_EXTI7_PA

#define SYSCFG_EXTICR2_EXTI7_PB

#define SYSCFG_EXTICR2_EXTI7_PC

#define SYSCFG_EXTICR2_EXTI7_PD

#define SYSCFG_EXTICR2_EXTI7_PE

#define SYSCFG_EXTICR3_EXTI8

#define SYSCFG_EXTICR3_EXTI9

#define SYSCFG_EXTICR3_EXTI10

#define SYSCFG_EXTICR3_EXTI11

* @brief EXTI8 configuration

#define SYSCFG_EXTICR3_EXTI8_PA

#define SYSCFG_EXTICR3_EXTI8_PB

#define SYSCFG_EXTICR3_EXTI8_PC

#define SYSCFG_EXTICR3_EXTI8_PD

#define SYSCFG_EXTICR3_EXTI8_PE

* @brief EXTI9 configuration

#define SYSCFG_EXTICR3_EXTI9_PA

#define SYSCFG_EXTICR3_EXTI9_PB

#define SYSCFG_EXTICR3_EXTI9_PC

#define SYSCFG_EXTICR3_EXTI9_PD

#define SYSCFG_EXTICR3_EXTI9_PE

#define SYSCFG_EXTICR3_EXTI9_PF

* @brief EXTI10 configuration

#define SYSCFG_EXTICR3_EXTI10_PA

#define SYSCFG_EXTICR3_EXTI10_PB

#define SYSCFG_EXTICR3_EXTI10_PC

#define SYSCFG_EXTICR3_EXTI10_PD

#define SYSCFG_EXTICR3_EXTI10_PE

#define SYSCFG_EXTICR3_EXTI10_PF

* @brief EXTI11 configuration

#define SYSCFG_EXTICR3_EXTI11_PA

#define SYSCFG_EXTICR3_EXTI11_PC

#define SYSCFG_EXTICR3_EXTI11_PD

#define SYSCFG_EXTICR3_EXTI11_PE

#define SYSCFG_EXTICR4_EXTI12

#define SYSCFG_EXTICR4_EXTI13

#define SYSCFG_EXTICR4_EXTI14

#define SYSCFG_EXTICR4_EXTI15

* @brief EXTI12 configuration

#define SYSCFG_EXTICR4_EXTI12_PA

#define SYSCFG_EXTICR4_EXTI12_PC

#define SYSCFG_EXTICR4_EXTI12_PD

#define SYSCFG_EXTICR4_EXTI12_PE

* @brief EXTI13 configuration

#define SYSCFG_EXTICR4_EXTI13_PA

#define SYSCFG_EXTICR4_EXTI13_PC

#define SYSCFG_EXTICR4_EXTI13_PD

#define SYSCFG_EXTICR4_EXTI13_PE

* @brief EXTI14 configuration

#define SYSCFG_EXTICR4_EXTI14_PA

#define SYSCFG_EXTICR4_EXTI14_PB

#define SYSCFG_EXTICR4_EXTI14_PC

#define SYSCFG_EXTICR4_EXTI14_PD

#define SYSCFG_EXTICR4_EXTI14_PE

* @brief EXTI15 configuration

#define SYSCFG_EXTICR4_EXTI15_PA

#define SYSCFG_EXTICR4_EXTI15_PB

#define SYSCFG_EXTICR4_EXTI15_PC

#define SYSCFG_EXTICR4_EXTI15_PD

#define SYSCFG_EXTICR4_EXTI15_PE

#define SYSCFG_CFGR2_LOCKUP_LOCK

#define SYSCFG_CFGR2_SRAM_PARITY_LOCK

#define SYSCFG_CFGR2_PVD_LOCK

#define SYSCFG_CFGR2_SRAM_PE

#define TIM_CR1_CEN

#define TIM_CR1_UDIS

#define TIM_CR1_URS

#define TIM_CR1_OPM

#define TIM_CR1_DIR

#define TIM_CR1_CMS

#define TIM_CR1_CMS_0

#define TIM_CR1_CMS_1

#define TIM_CR1_ARPE

#define TIM_CR1_CKD

#define TIM_CR1_CKD_0

#define TIM_CR1_CKD_1

#define TIM_CR2_CCPC

#define TIM_CR2_CCUS

#define TIM_CR2_CCDS

#define TIM_CR2_MMS

#define TIM_CR2_MMS_0

#define TIM_CR2_MMS_1

#define TIM_CR2_MMS_2

#define TIM_CR2_TI1S

#define TIM_CR2_OIS1

#define TIM_CR2_OIS1N

#define TIM_CR2_OIS2

#define TIM_CR2_OIS2N

#define TIM_CR2_OIS3

#define TIM_CR2_OIS3N

#define TIM_CR2_OIS4

#define TIM_SMCR_SMS

#define TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_2

#define TIM_SMCR_OCCS

#define TIM_SMCR_TS

#define TIM_SMCR_TS_0

#define TIM_SMCR_TS_1

#define TIM_SMCR_TS_2

#define TIM_SMCR_MSM

#define TIM_SMCR_ETF

#define TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_3

#define TIM_SMCR_ETPS

#define TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_1

#define TIM_SMCR_ECE

#define TIM_SMCR_ETP

#define TIM_DIER_UIE

#define TIM_DIER_CC1IE

#define TIM_DIER_CC2IE

#define TIM_DIER_CC3IE

#define TIM_DIER_CC4IE

#define TIM_DIER_COMIE

#define TIM_DIER_TIE

#define TIM_DIER_BIE

#define TIM_DIER_UDE

#define TIM_DIER_CC1DE

#define TIM_DIER_CC2DE

#define TIM_DIER_CC3DE

#define TIM_DIER_CC4DE

#define TIM_DIER_COMDE

#define TIM_DIER_TDE

#define TIM_SR_UIF

#define TIM_SR_CC1IF

#define TIM_SR_CC2IF

#define TIM_SR_CC3IF

#define TIM_SR_CC4IF

#define TIM_SR_COMIF

#define TIM_SR_TIF

#define TIM_SR_BIF

#define TIM_SR_CC1OF

#define TIM_SR_CC2OF

#define TIM_SR_CC3OF

#define TIM_SR_CC4OF

#define TIM_EGR_UG

#define TIM_EGR_CC1G

#define TIM_EGR_CC2G

#define TIM_EGR_CC3G

#define TIM_EGR_CC4G

#define TIM_EGR_COMG

#define TIM_EGR_TG

#define TIM_EGR_BG

#define TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_1

#define TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1CE

#define TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_1

#define TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2CE

#define TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_3

#define TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_1

#define TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3CE

#define TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_1

#define TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4CE

#define TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_3

#define TIM_CCER_CC1E

#define TIM_CCER_CC1P

#define TIM_CCER_CC1NE

#define TIM_CCER_CC1NP

#define TIM_CCER_CC2E

#define TIM_CCER_CC2P

#define TIM_CCER_CC2NE

#define TIM_CCER_CC2NP

#define TIM_CCER_CC3E

#define TIM_CCER_CC3P

#define TIM_CCER_CC3NE

#define TIM_CCER_CC3NP

#define TIM_CCER_CC4E

#define TIM_CCER_CC4P

#define TIM_CCER_CC4NP

#define TIM_CNT_CNT

#define TIM_PSC_PSC

#define TIM_ARR_ARR

#define TIM_RCR_REP

#define TIM_CCR1_CCR1

#define TIM_CCR2_CCR2

#define TIM_CCR3_CCR3

#define TIM_CCR4_CCR4

#define TIM_BDTR_DTG

#define TIM_BDTR_DTG_0

#define TIM_BDTR_DTG_1

#define TIM_BDTR_DTG_2

#define TIM_BDTR_DTG_3

#define TIM_BDTR_DTG_4

#define TIM_BDTR_DTG_5

#define TIM_BDTR_DTG_6

#define TIM_BDTR_DTG_7

#define TIM_BDTR_LOCK

#define TIM_BDTR_LOCK_0

#define TIM_BDTR_LOCK_1

#define TIM_BDTR_OSSI

#define TIM_BDTR_OSSR

#define TIM_BDTR_BKE

#define TIM_BDTR_BKP

#define TIM_BDTR_AOE

#define TIM_BDTR_MOE

#define TIM_DCR_DBA

#define TIM_DCR_DBA_0

#define TIM_DCR_DBA_1

#define TIM_DCR_DBA_2

#define TIM_DCR_DBA_3

#define TIM_DCR_DBA_4

#define TIM_DCR_DBL

#define TIM_DCR_DBL_0

#define TIM_DCR_DBL_1

#define TIM_DCR_DBL_2

#define TIM_DCR_DBL_3

#define TIM_DCR_DBL_4

#define TIM_DMAR_DMAB

#define TIM14_OR_TI1_RMP

#define TIM14_OR_TI1_RMP_0

#define TIM14_OR_TI1_RMP_1

#define USART_CR1_UE

#define USART_CR1_UESM

#define USART_CR1_RE

#define USART_CR1_TE

#define USART_CR1_IDLEIE

#define USART_CR1_RXNEIE

#define USART_CR1_TCIE

#define USART_CR1_TXEIE

#define USART_CR1_PEIE

#define USART_CR1_PS

#define USART_CR1_PCE

#define USART_CR1_WAKE

#define USART_CR1_M

#define USART_CR1_MME

#define USART_CR1_CMIE

#define USART_CR1_OVER8

#define USART_CR1_DEDT

#define USART_CR1_DEDT_0

#define USART_CR1_DEDT_1

#define USART_CR1_DEDT_2

#define USART_CR1_DEDT_3

#define USART_CR1_DEDT_4

#define USART_CR1_DEAT

#define USART_CR1_DEAT_0

#define USART_CR1_DEAT_1

#define USART_CR1_DEAT_2

#define USART_CR1_DEAT_3

#define USART_CR1_DEAT_4

#define USART_CR1_RTOIE

#define USART_CR1_EOBIE

#define USART_CR2_ADDM7

#define USART_CR2_LBDL

#define USART_CR2_LBDIE

#define USART_CR2_LBCL

#define USART_CR2_CPHA

#define USART_CR2_CPOL

#define USART_CR2_CLKEN

#define USART_CR2_STOP

#define USART_CR2_STOP_0

#define USART_CR2_STOP_1

#define USART_CR2_LINEN

#define USART_CR2_SWAP

#define USART_CR2_RXINV

#define USART_CR2_TXINV

#define USART_CR2_DATAINV

#define USART_CR2_MSBFIRST

#define USART_CR2_ABREN

#define USART_CR2_ABRMODE

#define USART_CR2_ABRMODE_0

#define USART_CR2_ABRMODE_1

#define USART_CR2_RTOEN

#define USART_CR2_ADD

#define USART_CR3_EIE

#define USART_CR3_IREN

#define USART_CR3_IRLP

#define USART_CR3_HDSEL

#define USART_CR3_NACK

#define USART_CR3_SCEN

#define USART_CR3_DMAR

#define USART_CR3_DMAT

#define USART_CR3_RTSE

#define USART_CR3_CTSE

#define USART_CR3_CTSIE

#define USART_CR3_ONEBIT

#define USART_CR3_OVRDIS

#define USART_CR3_DDRE

#define USART_CR3_DEM

#define USART_CR3_DEP

#define USART_CR3_SCARCNT

#define USART_CR3_SCARCNT_0

#define USART_CR3_SCARCNT_1

#define USART_CR3_SCARCNT_2

#define USART_CR3_WUS

#define USART_CR3_WUS_0

#define USART_CR3_WUS_1

#define USART_CR3_WUFIE

#define USART_BRR_DIV_FRACTION

#define USART_BRR_DIV_MANTISSA

#define USART_GTPR_PSC

#define USART_GTPR_GT

#define USART_RTOR_RTO

#define USART_RTOR_BLEN

#define USART_RQR_ABRRQ

#define USART_RQR_SBKRQ

#define USART_RQR_MMRQ

#define USART_RQR_RXFRQ

#define USART_RQR_TXFRQ

#define USART_ISR_PE

#define USART_ISR_FE

#define USART_ISR_NE

#define USART_ISR_ORE

#define USART_ISR_IDLE

#define USART_ISR_RXNE

#define USART_ISR_TC

#define USART_ISR_TXE

#define USART_ISR_LBD

#define USART_ISR_CTSIF

#define USART_ISR_CTS

#define USART_ISR_RTOF

#define USART_ISR_EOBF

#define USART_ISR_ABRE

#define USART_ISR_ABRF

#define USART_ISR_BUSY

#define USART_ISR_CMF

#define USART_ISR_SBKF

#define USART_ISR_RWU

#define USART_ISR_WUF

#define USART_ISR_TEACK

#define USART_ISR_REACK

#define USART_ICR_PECF

#define USART_ICR_FECF

#define USART_ICR_NCF

#define USART_ICR_ORECF

#define USART_ICR_IDLECF

#define USART_ICR_TCCF

#define USART_ICR_LBDCF

#define USART_ICR_CTSCF

#define USART_ICR_RTOCF

#define USART_ICR_EOBCF

#define USART_ICR_CMCF

#define USART_ICR_WUCF

#define USART_RDR_RDR

#define USART_TDR_TDR

#define WWDG_CR_T

#define WWDG_CR_T0

#define WWDG_CR_T1

#define WWDG_CR_T2

#define WWDG_CR_T3

#define WWDG_CR_T4

#define WWDG_CR_T5

#define WWDG_CR_T6

#define WWDG_CR_WDGA

#define WWDG_CFR_W

#define WWDG_CFR_W0

#define WWDG_CFR_W1

#define WWDG_CFR_W2

#define WWDG_CFR_W3

#define WWDG_CFR_W4

#define WWDG_CFR_W5

#define WWDG_CFR_W6

#define WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB0

#define WWDG_CFR_WDGTB1

#define WWDG_CFR_EWI

#define WWDG_SR_EWIF

@addtogroup Exported_macro * @{

#define SET_BIT( REG, BIT )

#define CLEAR_BIT( REG, BIT )

#define READ_BIT( REG, BIT )

#define CLEAR_REG( REG )

#define WRITE_REG( REG, VAL )

#define READ_REG( REG )

#define MODIFY_REG( REG, CLEARMASK, SETMASK )

Typedef IRQn_Type

* @brief STM32F37X Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section

typedef enum IRQn IRQn_Type

enum IRQn  
   {  
      NonMaskableInt_IRQn;  
      MemoryManagement_IRQn;  
      BusFault_IRQn;  
      UsageFault_IRQn;  
      SVCall_IRQn;  
      DebugMonitor_IRQn;  
      PendSV_IRQn;  
      SysTick_IRQn;  
      WWDG_IRQn;  
      PVD_IRQn;  
      TAMPER_STAMP_IRQn;  
      RTC_WKUP_IRQn;  
      FLASH_IRQn;  
      RCC_IRQn;  
      EXTI0_IRQn;  
      EXTI1_IRQn;  
      EXTI2_TS_IRQn;  
      EXTI3_IRQn;  
      EXTI4_IRQn;  
      DMA1_Channel1_IRQn;  
      DMA1_Channel2_IRQn;  
      DMA1_Channel3_IRQn;  
      DMA1_Channel4_IRQn;  
      DMA1_Channel5_IRQn;  
      DMA1_Channel6_IRQn;  
      DMA1_Channel7_IRQn;  
      ADC1_IRQn;  
      CAN1_TX_IRQn;  
      CAN1_RX0_IRQn;  
      CAN1_RX1_IRQn;  
      CAN1_SCE_IRQn;  
      EXTI9_5_IRQn;  
      TIM15_IRQn;  
      TIM16_IRQn;  
      TIM17_IRQn;  
      TIM18_DAC2_IRQn;  
      TIM2_IRQn;  
      TIM3_IRQn;  
      TIM4_IRQn;  
      I2C1_EV_IRQn;  
      I2C1_ER_IRQn;  
      I2C2_EV_IRQn;  
      I2C2_ER_IRQn;  
      SPI1_IRQn;  
      SPI2_IRQn;  
      USART1_IRQn;  
      USART2_IRQn;  
      USART3_IRQn;  
      EXTI15_10_IRQn;  
      RTC_Alarm_IRQn;  
      CEC_IRQn;  
      TIM12_IRQn;  
      TIM13_IRQn;  
      TIM14_IRQn;  
      TIM5_IRQn;  
      SPI3_IRQn;  
      TIM6_DAC1_IRQn;  
      TIM7_IRQn;  
      DMA2_Channel1_IRQn;  
      DMA2_Channel2_IRQn;  
      DMA2_Channel3_IRQn;  
      DMA2_Channel4_IRQn;  
      DMA2_Channel5_IRQn;  
      SDADC1_IRQn;  
      SDADC2_IRQn;  
      SDADC3_IRQn;  
      COMP_IRQn;  
      USB_HP_IRQn;  
      USB_LP_IRQn;  
      USBWakeUp_IRQn;  
      TIM19_IRQn;  
      FPU_IRQn;  
      IRQn_MAX;  
   }  

Typedef s32

@addtogroup Exported_types * @{

typedef int32_t s32

Typedef s16

typedef int16_t s16

Typedef s8

typedef int8_t s8

Typedef sc32

typedef const int32_t sc32

Typedef sc16

typedef const int16_t sc16

Typedef sc8

typedef const int8_t sc8

Typedef vs32

typedef volatile int32_t vs32

Typedef vs16

typedef volatile int16_t vs16

Typedef vs8

typedef volatile int8_t vs8

Typedef vsc32

typedef volatile const int32_t vsc32

Typedef vsc16

typedef volatile const int16_t vsc16

Typedef vsc8

typedef volatile const int8_t vsc8

Typedef u32

typedef uint32_t u32

Typedef u16

typedef uint16_t u16

Typedef u8

typedef uint8_t u8

Typedef uc32

typedef const uint32_t uc32

Typedef uc16

typedef const uint16_t uc16

Typedef uc8

typedef const uint8_t uc8

Typedef vu32

typedef volatile uint32_t vu32

Typedef vu16

typedef volatile uint16_t vu16

Typedef vu8

typedef volatile uint8_t vu8

Typedef vuc32

typedef volatile const uint32_t vuc32

Typedef vuc16

typedef volatile const uint16_t vuc16

Typedef vuc8

typedef volatile const uint8_t vuc8

Typedef FlagStatus

typedef enum {...} FlagStatus
enum  
   {  
      RESET;  
      SET;  
   }  

Typedef ITStatus

typedef enum {...} ITStatus
See: Typedef FlagStatus

Typedef FunctionalState

typedef enum {...} FunctionalState
enum  
   {  
      DISABLE;  
      ENABLE;  
   }  

Typedef ErrorStatus

typedef enum {...} ErrorStatus
enum  
   {  
      ERROR;  
      SUCCESS;  
   }  

Typedef ADC_TypeDef

* @brief Analog to Digital Converter

typedef struct {...} ADC_TypeDef

struct  
   {  
      volatile uint32_t SR;  
      volatile uint32_t CR1;  
      volatile uint32_t CR2;  
      volatile uint32_t SMPR1;  
      volatile uint32_t SMPR2;  
      volatile uint32_t JOFR1;  
      volatile uint32_t JOFR2;  
      volatile uint32_t JOFR3;  
      volatile uint32_t JOFR4;  
      volatile uint32_t HTR;  
      volatile uint32_t LTR;  
      volatile uint32_t SQR1;  
      volatile uint32_t SQR2;  
      volatile uint32_t SQR3;  
      volatile uint32_t JSQR;  
      volatile uint32_t JDR1;  
      volatile uint32_t JDR2;  
      volatile uint32_t JDR3;  
      volatile uint32_t JDR4;  
      volatile uint32_t DR;  
   }  

Typedef CAN_TxMailBox_TypeDef

* @brief Controller Area Network TxMailBox

typedef struct {...} CAN_TxMailBox_TypeDef

struct  
   {  
      volatile uint32_t TIR;  
      volatile uint32_t TDTR;  
      volatile uint32_t TDLR;  
      volatile uint32_t TDHR;  
   }  

Typedef CAN_FIFOMailBox_TypeDef

* @brief Controller Area Network FIFOMailBox

typedef struct {...} CAN_FIFOMailBox_TypeDef

struct  
   {  
      volatile uint32_t RIR;  
      volatile uint32_t RDTR;  
      volatile uint32_t RDLR;  
      volatile uint32_t RDHR;  
   }  

Typedef CAN_FilterRegister_TypeDef

* @brief Controller Area Network FilterRegister

typedef struct {...} CAN_FilterRegister_TypeDef

struct  
   {  
      volatile uint32_t FR1;  
      volatile uint32_t FR2;  
   }  

Typedef CAN_TypeDef

* @brief Controller Area Network

typedef struct {...} CAN_TypeDef

struct  
   {  
      volatile uint32_t MCR;  
      volatile uint32_t MSR;  
      volatile uint32_t TSR;  
      volatile uint32_t RF0R;  
      volatile uint32_t RF1R;  
      volatile uint32_t IER;  
      volatile uint32_t ESR;  
      volatile uint32_t BTR;  
      uint32_t RESERVED0[88];  
      CAN_TxMailBox_TypeDef sTxMailBox[3];  
      CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];  
      uint32_t RESERVED1[12];  
      volatile uint32_t FMR;  
      volatile uint32_t FM1R;  
      uint32_t RESERVED2;  
      volatile uint32_t FS1R;  
      uint32_t RESERVED3;  
      volatile uint32_t FFA1R;  
      uint32_t RESERVED4;  
      volatile uint32_t FA1R;  
      uint32_t RESERVED5[8];  
      CAN_FilterRegister_TypeDef sFilterRegister[28];  
   }  

Typedef CEC_TypeDef

* @brief Consumer Electronics Control

typedef struct {...} CEC_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t CFGR;  
      volatile uint32_t TXDR;  
      volatile uint32_t RXDR;  
      volatile uint32_t ISR;  
      volatile uint32_t IER;  
   }  

Typedef COMP_TypeDef

* @brief Analog Comparators

typedef struct {...} COMP_TypeDef

struct  
   {  
      volatile uint32_t CSR;  
   }  

Typedef CRC_TypeDef

* @brief CRC calculation unit

typedef struct {...} CRC_TypeDef

struct  
   {  
      volatile uint32_t DR;  
      volatile uint8_t IDR;  
      uint8_t RESERVED0;  
      uint16_t RESERVED1;  
      volatile uint32_t CR;  
      uint32_t RESERVED2;  
      volatile uint32_t INIT;  
      volatile uint32_t POL;  
   }  

Typedef DAC_TypeDef

* @brief Digital to Analog Converter

typedef struct {...} DAC_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t SWTRIGR;  
      volatile uint32_t DHR12R1;  
      volatile uint32_t DHR12L1;  
      volatile uint32_t DHR8R1;  
      volatile uint32_t DHR12R2;  
      volatile uint32_t DHR12L2;  
      volatile uint32_t DHR8R2;  
      volatile uint32_t DHR12RD;  
      volatile uint32_t DHR12LD;  
      volatile uint32_t DHR8RD;  
      volatile uint32_t DOR1;  
      volatile uint32_t DOR2;  
      volatile uint32_t SR;  
   }  

Typedef DBGMCU_TypeDef

* @brief Debug MCU

typedef struct {...} DBGMCU_TypeDef

struct  
   {  
      volatile uint32_t IDCODE;  
      volatile uint32_t CR;  
      volatile uint32_t APB1FZ;  
      volatile uint32_t APB2FZ;  
   }  

Typedef DMA_Channel_TypeDef

* @brief DMA Controller

typedef struct {...} DMA_Channel_TypeDef

struct  
   {  
      volatile uint32_t CCR;  
      volatile uint32_t CNDTR;  
      volatile uint32_t CPAR;  
      volatile uint32_t CMAR;  
   }  

Typedef DMA_TypeDef

typedef struct {...} DMA_TypeDef
struct  
   {  
      volatile uint32_t ISR;  
      volatile uint32_t IFCR;  
   }  

Typedef EXTI_TypeDef

* @brief External Interrupt/Event Controller

typedef struct {...} EXTI_TypeDef

struct  
   {  
      volatile uint32_t IMR;  
      volatile uint32_t EMR;  
      volatile uint32_t RTSR;  
      volatile uint32_t FTSR;  
      volatile uint32_t SWIER;  
      volatile uint32_t PR;  
   }  

Typedef FLASH_TypeDef

* @brief FLASH Registers

typedef struct {...} FLASH_TypeDef

struct  
   {  
      volatile uint32_t ACR;  
      volatile uint32_t KEYR;  
      volatile uint32_t OPTKEYR;  
      volatile uint32_t SR;  
      volatile uint32_t CR;  
      volatile uint32_t AR;  
      uint32_t RESERVED;  
      volatile uint32_t OBR;  
      volatile uint32_t WRPR;  
   }  

Typedef OB_TypeDef

* @brief Option Bytes Registers

typedef struct {...} OB_TypeDef

struct  
   {  
      volatile uint16_t RDP;  
      volatile uint16_t USER;  
      uint16_t RESERVED0;  
      uint16_t RESERVED1;  
      volatile uint16_t WRP0;  
      volatile uint16_t WRP1;  
      volatile uint16_t WRP2;  
      volatile uint16_t WRP3;  
   }  

Typedef GPIO_TypeDef

* @brief General Purpose I/O

typedef struct {...} GPIO_TypeDef

struct  
   {  
      volatile uint32_t MODER;  
      volatile uint16_t OTYPER;  
      uint16_t RESERVED0;  
      volatile uint32_t OSPEEDR;  
      volatile uint32_t PUPDR;  
      volatile uint16_t IDR;  
      uint16_t RESERVED1;  
      volatile uint16_t ODR;  
      uint16_t RESERVED2;  
      volatile uint32_t BSRR;  
      volatile uint32_t LCKR;  
      volatile uint32_t AFR[2];  
      volatile uint16_t BRR;  
      uint16_t RESERVED3;  
   }  

Typedef SYSCFG_TypeDef

* @brief System configuration controller

typedef struct {...} SYSCFG_TypeDef

struct  
   {  
      volatile uint32_t CFGR1;  
      uint32_t RESERVED;  
      volatile uint32_t EXTICR[4];  
      volatile uint32_t CFGR2;  
   }  

Typedef I2C_TypeDef

* @brief Inter-integrated Circuit Interface

typedef struct {...} I2C_TypeDef

struct  
   {  
      volatile uint32_t CR1;  
      volatile uint32_t CR2;  
      volatile uint32_t OAR1;  
      volatile uint32_t OAR2;  
      volatile uint32_t TIMINGR;  
      volatile uint32_t TIMEOUTR;  
      volatile uint32_t ISR;  
      volatile uint32_t ICR;  
      volatile uint32_t PECR;  
      volatile uint32_t RXDR;  
      volatile uint32_t TXDR;  
   }  

Typedef IWDG_TypeDef

* @brief Independent WATCHDOG

typedef struct {...} IWDG_TypeDef

struct  
   {  
      volatile uint32_t KR;  
      volatile uint32_t PR;  
      volatile uint32_t RLR;  
      volatile uint32_t SR;  
      volatile uint32_t WINR;  
   }  

Typedef PWR_TypeDef

* @brief Power Control

typedef struct {...} PWR_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t CSR;  
   }  

Typedef RCC_TypeDef

* @brief Reset and Clock Control

typedef struct {...} RCC_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t CFGR;  
      volatile uint32_t CIR;  
      volatile uint32_t APB2RSTR;  
      volatile uint32_t APB1RSTR;  
      volatile uint32_t AHBENR;  
      volatile uint32_t APB2ENR;  
      volatile uint32_t APB1ENR;  
      volatile uint32_t BDCR;  
      volatile uint32_t CSR;  
      volatile uint32_t AHBRSTR;  
      volatile uint32_t CFGR2;  
      volatile uint32_t CFGR3;  
   }  

Typedef RTC_TypeDef

* @brief Real-Time Clock

typedef struct {...} RTC_TypeDef

struct  
   {  
      volatile uint32_t TR;  
      volatile uint32_t DR;  
      volatile uint32_t CR;  
      volatile uint32_t ISR;  
      volatile uint32_t PRER;  
      volatile uint32_t WUTR;  
      uint32_t RESERVED0;  
      volatile uint32_t ALRMAR;  
      volatile uint32_t ALRMBR;  
      volatile uint32_t WPR;  
      volatile uint32_t SSR;  
      volatile uint32_t SHIFTR;  
      volatile uint32_t TSTR;  
      volatile uint32_t TSDR;  
      volatile uint32_t TSSSR;  
      volatile uint32_t CALR;  
      volatile uint32_t TAFCR;  
      volatile uint32_t ALRMASSR;  
      volatile uint32_t ALRMBSSR;  
      uint32_t RESERVED7;  
      volatile uint32_t BKP0R;  
      volatile uint32_t BKP1R;  
      volatile uint32_t BKP2R;  
      volatile uint32_t BKP3R;  
      volatile uint32_t BKP4R;  
      volatile uint32_t BKP5R;  
      volatile uint32_t BKP6R;  
      volatile uint32_t BKP7R;  
      volatile uint32_t BKP8R;  
      volatile uint32_t BKP9R;  
      volatile uint32_t BKP10R;  
      volatile uint32_t BKP11R;  
      volatile uint32_t BKP12R;  
      volatile uint32_t BKP13R;  
      volatile uint32_t BKP14R;  
      volatile uint32_t BKP15R;  
      volatile uint32_t BKP16R;  
      volatile uint32_t BKP17R;  
      volatile uint32_t BKP18R;  
      volatile uint32_t BKP19R;  
      volatile uint32_t BKP20R;  
      volatile uint32_t BKP21R;  
      volatile uint32_t BKP22R;  
      volatile uint32_t BKP23R;  
      volatile uint32_t BKP24R;  
      volatile uint32_t BKP25R;  
      volatile uint32_t BKP26R;  
      volatile uint32_t BKP27R;  
      volatile uint32_t BKP28R;  
      volatile uint32_t BKP29R;  
      volatile uint32_t BKP30R;  
      volatile uint32_t BKP31R;  
   }  

Typedef SDADC_TypeDef

* @brief Sigma-Delta Analog to Digital Converter (SDADC)

typedef struct {...} SDADC_TypeDef

struct  
   {  
      volatile uint32_t CR1;  
      volatile uint32_t CR2;  
      volatile uint32_t ISR;  
      volatile uint32_t CLRISR;  
      volatile uint32_t RESERVED0;  
      volatile uint32_t JCHGR;  
      volatile uint32_t RESERVED1;  
      volatile uint32_t RESERVED2;  
      volatile uint32_t CONF0R;  
      volatile uint32_t CONF1R;  
      volatile uint32_t CONF2R;  
      volatile uint32_t RESERVED3[5];  
      volatile uint32_t CONFCHR1;  
      volatile uint32_t CONFCHR2;  
      volatile uint32_t RESERVED4[6];  
      volatile uint32_t JDATAR;  
      volatile uint32_t RDATAR;  
      volatile uint32_t RESERVED5[2];  
      volatile uint32_t JDATA12R;  
      volatile uint32_t RDATA12R;  
      volatile uint32_t JDATA13R;  
      volatile uint32_t RDATA13R;  
   }  

Typedef SPI_TypeDef

* @brief Serial Peripheral Interface

typedef struct {...} SPI_TypeDef

struct  
   {  
      volatile uint16_t CR1;  
      uint16_t RESERVED0;  
      volatile uint16_t CR2;  
      uint16_t RESERVED1;  
      volatile uint16_t SR;  
      uint16_t RESERVED2;  
      volatile uint16_t DR;  
      uint16_t RESERVED3;  
      volatile uint16_t CRCPR;  
      uint16_t RESERVED4;  
      volatile uint16_t RXCRCR;  
      uint16_t RESERVED5;  
      volatile uint16_t TXCRCR;  
      uint16_t RESERVED6;  
      volatile uint16_t I2SCFGR;  
      uint16_t RESERVED7;  
      volatile uint16_t I2SPR;  
      uint16_t RESERVED8;  
   }  

Typedef TIM_TypeDef

* @brief TIM

typedef struct {...} TIM_TypeDef

struct  
   {  
      volatile uint16_t CR1;  
      uint16_t RESERVED0;  
      volatile uint16_t CR2;  
      uint16_t RESERVED1;  
      volatile uint16_t SMCR;  
      uint16_t RESERVED2;  
      volatile uint16_t DIER;  
      uint16_t RESERVED3;  
      volatile uint16_t SR;  
      uint16_t RESERVED4;  
      volatile uint16_t EGR;  
      uint16_t RESERVED5;  
      volatile uint16_t CCMR1;  
      uint16_t RESERVED6;  
      volatile uint16_t CCMR2;  
      uint16_t RESERVED7;  
      volatile uint16_t CCER;  
      uint16_t RESERVED8;  
      volatile uint32_t CNT;  
      volatile uint16_t PSC;  
      uint16_t RESERVED9;  
      volatile uint32_t ARR;  
      volatile uint16_t RCR;  
      uint16_t RESERVED10;  
      volatile uint32_t CCR1;  
      volatile uint32_t CCR2;  
      volatile uint32_t CCR3;  
      volatile uint32_t CCR4;  
      volatile uint16_t BDTR;  
      uint16_t RESERVED11;  
      volatile uint16_t DCR;  
      uint16_t RESERVED12;  
      volatile uint16_t DMAR;  
      uint16_t RESERVED13;  
      volatile uint16_t OR;  
      uint16_t RESERVED14;  
   }  

Typedef TSC_TypeDef

* @brief Touch Sensing Controller (TSC)

typedef struct {...} TSC_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t IER;  
      volatile uint32_t ICR;  
      volatile uint32_t ISR;  
      volatile uint32_t IOHCR;  
      uint32_t RESERVED1;  
      volatile uint32_t IOASCR;  
      uint32_t RESERVED2;  
      volatile uint32_t IOSCR;  
      uint32_t RESERVED3;  
      volatile uint32_t IOCCR;  
      uint32_t RESERVED4;  
      volatile uint32_t IOGCSR;  
      volatile uint32_t IOGXCR[8];  
   }  

Typedef USART_TypeDef

* @brief Universal Synchronous Asynchronous Receiver Transmitter

typedef struct {...} USART_TypeDef

struct  
   {  
      volatile uint32_t CR1;  
      volatile uint32_t CR2;  
      volatile uint32_t CR3;  
      volatile uint16_t BRR;  
      uint16_t RESERVED1;  
      volatile uint16_t GTPR;  
      uint16_t RESERVED2;  
      volatile uint32_t RTOR;  
      volatile uint16_t RQR;  
      uint16_t RESERVED3;  
      volatile uint32_t ISR;  
      volatile uint32_t ICR;  
      volatile uint16_t RDR;  
      uint16_t RESERVED4;  
      volatile uint16_t TDR;  
      uint16_t RESERVED5;  
   }  

Typedef WWDG_TypeDef

* @brief Window WATCHDOG

typedef struct {...} WWDG_TypeDef

struct  
   {  
      volatile uint32_t CR;  
      volatile uint32_t CFR;  
      volatile uint32_t SR;  
   }