stm32f401xc.h

Cortex-M4 Processor Exceptions Numbers

Included Files

@addtogroup stm32f401xc * @{

#include <nut/include/cfg/arch.h>

#include <nut/include/cfg/clock.h>

* @}

#include <nut/include/arch/cm3/core_cm4.h>

#include <nut/include/arch/cm3/stm/system_stm32.h>

#include <stdint.h>

Preprocessor definitions

#define __STM32F401xC_H

* @brief Configuration of the Cortex-M4 Processor and Core Peripherals

#define __CM4_REV 0x0001

#define __MPU_PRESENT 1

#define __NVIC_PRIO_BITS 4

#define __Vendor_SysTickConfig 0

#define __FPU_PRESENT 1

* @brief Peripheral_memory_map

#define FLASH_BASE

#define CCMDATARAM_BASE

#define SRAM1_BASE

#define SRAM2_BASE

#define SRAM3_BASE

#define PERIPH_BASE

#define BKPSRAM_BASE

#define CCMDATARAM_BB_BASE

#define SRAM1_BB_BASE

#define SRAM2_BB_BASE

#define SRAM3_BB_BASE

#define PERIPH_BB_BASE

#define BKPSRAM_BB_BASE

#define SRAM_BASE SRAM1_BASE

#define SRAM_BB_BASE SRAM1_BB_BASE

#define APB1PERIPH_BASE PERIPH_BASE

#define APB2PERIPH_BASE

#define AHB1PERIPH_BASE

#define AHB2PERIPH_BASE

#define TIM2_BASE

#define TIM3_BASE

#define TIM4_BASE

#define TIM5_BASE

#define RTC_BASE

#define WWDG_BASE

#define IWDG_BASE

#define I2S2ext_BASE

#define SPI2_BASE

#define SPI3_BASE

#define I2S3ext_BASE

#define USART2_BASE

#define I2C1_BASE

#define I2C2_BASE

#define I2C3_BASE

#define PWR_BASE

#define TIM1_BASE

#define USART1_BASE

#define USART6_BASE

#define ADC1_BASE

#define ADC_BASE

#define SDIO_BASE

#define SPI1_BASE

#define SPI4_BASE

#define SYSCFG_BASE

#define EXTI_BASE

#define TIM9_BASE

#define TIM10_BASE

#define TIM11_BASE

#define GPIOA_BASE

#define GPIOB_BASE

#define GPIOC_BASE

#define GPIOD_BASE

#define GPIOE_BASE

#define GPIOH_BASE

#define CRC_BASE

#define RCC_BASE

#define FLASH_R_BASE

#define DMA1_BASE

#define DMA1_Stream0_BASE

#define DMA1_Stream1_BASE

#define DMA1_Stream2_BASE

#define DMA1_Stream3_BASE

#define DMA1_Stream4_BASE

#define DMA1_Stream5_BASE

#define DMA1_Stream6_BASE

#define DMA1_Stream7_BASE

#define DMA2_BASE

#define DMA2_Stream0_BASE

#define DMA2_Stream1_BASE

#define DMA2_Stream2_BASE

#define DMA2_Stream3_BASE

#define DMA2_Stream4_BASE

#define DMA2_Stream5_BASE

#define DMA2_Stream6_BASE

#define DMA2_Stream7_BASE

#define RNG_BASE

#define DBGMCU_BASE

#define USB_OTG_FS_PERIPH_BASE

#define USB_OTG_GLOBAL_BASE

#define USB_OTG_DEVICE_BASE

#define USB_OTG_IN_ENDPOINT_BASE

#define USB_OTG_OUT_ENDPOINT_BASE

#define USB_OTG_EP_REG_SIZE

#define USB_OTG_HOST_BASE

#define USB_OTG_HOST_PORT_BASE

#define USB_OTG_HOST_CHANNEL_BASE

#define USB_OTG_HOST_CHANNEL_SIZE

#define USB_OTG_PCGCCTL_BASE

#define USB_OTG_FIFO_BASE

#define USB_OTG_FIFO_SIZE

@addtogroup Peripheral_declaration * @{

#define TIM2

#define TIM3

#define TIM4

#define TIM5

#define RTC

#define WWDG

#define IWDG

#define I2S2ext

#define SPI2

#define SPI3

#define I2S3ext

#define USART2

#define I2C1

#define I2C2

#define I2C3

#define PWR

#define TIM1

#define USART1

#define USART6

#define ADC

#define ADC1

#define SDIO

#define SPI1

#define SPI4

#define SYSCFG

#define EXTI

#define TIM9

#define TIM10

#define TIM11

#define GPIOA

#define GPIOB

#define GPIOC

#define GPIOD

#define GPIOE

#define GPIOH

#define CRC

#define RCC

#define FLASH

#define DMA1

#define DMA1_Stream0

#define DMA1_Stream1

#define DMA1_Stream2

#define DMA1_Stream3

#define DMA1_Stream4

#define DMA1_Stream5

#define DMA1_Stream6

#define DMA1_Stream7

#define DMA2

#define DMA2_Stream0

#define DMA2_Stream1

#define DMA2_Stream2

#define DMA2_Stream3

#define DMA2_Stream4

#define DMA2_Stream5

#define DMA2_Stream6

#define DMA2_Stream7

#define RNG

#define DBGMCU

#define USB_OTG_FS

#define ADC_SR_AWD

#define ADC_SR_EOC

#define ADC_SR_JEOC

#define ADC_SR_JSTRT

#define ADC_SR_STRT

#define ADC_SR_OVR

#define ADC_CR1_AWDCH

#define ADC_CR1_AWDCH_0

#define ADC_CR1_AWDCH_1

#define ADC_CR1_AWDCH_2

#define ADC_CR1_AWDCH_3

#define ADC_CR1_AWDCH_4

#define ADC_CR1_EOCIE

#define ADC_CR1_AWDIE

#define ADC_CR1_JEOCIE

#define ADC_CR1_SCAN

#define ADC_CR1_AWDSGL

#define ADC_CR1_JAUTO

#define ADC_CR1_DISCEN

#define ADC_CR1_JDISCEN

#define ADC_CR1_DISCNUM

#define ADC_CR1_DISCNUM_0

#define ADC_CR1_DISCNUM_1

#define ADC_CR1_DISCNUM_2

#define ADC_CR1_JAWDEN

#define ADC_CR1_AWDEN

#define ADC_CR1_RES

#define ADC_CR1_RES_0

#define ADC_CR1_RES_1

#define ADC_CR1_OVRIE

#define ADC_CR2_ADON

#define ADC_CR2_CONT

#define ADC_CR2_DMA

#define ADC_CR2_DDS

#define ADC_CR2_EOCS

#define ADC_CR2_ALIGN

#define ADC_CR2_JEXTSEL

#define ADC_CR2_JEXTSEL_0

#define ADC_CR2_JEXTSEL_1

#define ADC_CR2_JEXTSEL_2

#define ADC_CR2_JEXTSEL_3

#define ADC_CR2_JEXTEN

#define ADC_CR2_JEXTEN_0

#define ADC_CR2_JEXTEN_1

#define ADC_CR2_JSWSTART

#define ADC_CR2_EXTSEL

#define ADC_CR2_EXTSEL_0

#define ADC_CR2_EXTSEL_1

#define ADC_CR2_EXTSEL_2

#define ADC_CR2_EXTSEL_3

#define ADC_CR2_EXTEN

#define ADC_CR2_EXTEN_0

#define ADC_CR2_EXTEN_1

#define ADC_CR2_SWSTART

#define ADC_SMPR1_SMP10

#define ADC_SMPR1_SMP10_0

#define ADC_SMPR1_SMP10_1

#define ADC_SMPR1_SMP10_2

#define ADC_SMPR1_SMP11

#define ADC_SMPR1_SMP11_0

#define ADC_SMPR1_SMP11_1

#define ADC_SMPR1_SMP11_2

#define ADC_SMPR1_SMP12

#define ADC_SMPR1_SMP12_0

#define ADC_SMPR1_SMP12_1

#define ADC_SMPR1_SMP12_2

#define ADC_SMPR1_SMP13

#define ADC_SMPR1_SMP13_0

#define ADC_SMPR1_SMP13_1

#define ADC_SMPR1_SMP13_2

#define ADC_SMPR1_SMP14

#define ADC_SMPR1_SMP14_0

#define ADC_SMPR1_SMP14_1

#define ADC_SMPR1_SMP14_2

#define ADC_SMPR1_SMP15

#define ADC_SMPR1_SMP15_0

#define ADC_SMPR1_SMP15_1

#define ADC_SMPR1_SMP15_2

#define ADC_SMPR1_SMP16

#define ADC_SMPR1_SMP16_0

#define ADC_SMPR1_SMP16_1

#define ADC_SMPR1_SMP16_2

#define ADC_SMPR1_SMP17

#define ADC_SMPR1_SMP17_0

#define ADC_SMPR1_SMP17_1

#define ADC_SMPR1_SMP17_2

#define ADC_SMPR1_SMP18

#define ADC_SMPR1_SMP18_0

#define ADC_SMPR1_SMP18_1

#define ADC_SMPR1_SMP18_2

#define ADC_SMPR2_SMP0

#define ADC_SMPR2_SMP0_0

#define ADC_SMPR2_SMP0_1

#define ADC_SMPR2_SMP0_2

#define ADC_SMPR2_SMP1

#define ADC_SMPR2_SMP1_0

#define ADC_SMPR2_SMP1_1

#define ADC_SMPR2_SMP1_2

#define ADC_SMPR2_SMP2

#define ADC_SMPR2_SMP2_0

#define ADC_SMPR2_SMP2_1

#define ADC_SMPR2_SMP2_2

#define ADC_SMPR2_SMP3

#define ADC_SMPR2_SMP3_0

#define ADC_SMPR2_SMP3_1

#define ADC_SMPR2_SMP3_2

#define ADC_SMPR2_SMP4

#define ADC_SMPR2_SMP4_0

#define ADC_SMPR2_SMP4_1

#define ADC_SMPR2_SMP4_2

#define ADC_SMPR2_SMP5

#define ADC_SMPR2_SMP5_0

#define ADC_SMPR2_SMP5_1

#define ADC_SMPR2_SMP5_2

#define ADC_SMPR2_SMP6

#define ADC_SMPR2_SMP6_0

#define ADC_SMPR2_SMP6_1

#define ADC_SMPR2_SMP6_2

#define ADC_SMPR2_SMP7

#define ADC_SMPR2_SMP7_0

#define ADC_SMPR2_SMP7_1

#define ADC_SMPR2_SMP7_2

#define ADC_SMPR2_SMP8

#define ADC_SMPR2_SMP8_0

#define ADC_SMPR2_SMP8_1

#define ADC_SMPR2_SMP8_2

#define ADC_SMPR2_SMP9

#define ADC_SMPR2_SMP9_0

#define ADC_SMPR2_SMP9_1

#define ADC_SMPR2_SMP9_2

#define ADC_JOFR1_JOFFSET1

#define ADC_JOFR2_JOFFSET2

#define ADC_JOFR3_JOFFSET3

#define ADC_JOFR4_JOFFSET4

#define ADC_HTR_HT

#define ADC_LTR_LT

#define ADC_SQR1_SQ13

#define ADC_SQR1_SQ13_0

#define ADC_SQR1_SQ13_1

#define ADC_SQR1_SQ13_2

#define ADC_SQR1_SQ13_3

#define ADC_SQR1_SQ13_4

#define ADC_SQR1_SQ14

#define ADC_SQR1_SQ14_0

#define ADC_SQR1_SQ14_1

#define ADC_SQR1_SQ14_2

#define ADC_SQR1_SQ14_3

#define ADC_SQR1_SQ14_4

#define ADC_SQR1_SQ15

#define ADC_SQR1_SQ15_0

#define ADC_SQR1_SQ15_1

#define ADC_SQR1_SQ15_2

#define ADC_SQR1_SQ15_3

#define ADC_SQR1_SQ15_4

#define ADC_SQR1_SQ16

#define ADC_SQR1_SQ16_0

#define ADC_SQR1_SQ16_1

#define ADC_SQR1_SQ16_2

#define ADC_SQR1_SQ16_3

#define ADC_SQR1_SQ16_4

#define ADC_SQR1_L

#define ADC_SQR1_L_0

#define ADC_SQR1_L_1

#define ADC_SQR1_L_2

#define ADC_SQR1_L_3

#define ADC_SQR2_SQ7

#define ADC_SQR2_SQ7_0

#define ADC_SQR2_SQ7_1

#define ADC_SQR2_SQ7_2

#define ADC_SQR2_SQ7_3

#define ADC_SQR2_SQ7_4

#define ADC_SQR2_SQ8

#define ADC_SQR2_SQ8_0

#define ADC_SQR2_SQ8_1

#define ADC_SQR2_SQ8_2

#define ADC_SQR2_SQ8_3

#define ADC_SQR2_SQ8_4

#define ADC_SQR2_SQ9

#define ADC_SQR2_SQ9_0

#define ADC_SQR2_SQ9_1

#define ADC_SQR2_SQ9_2

#define ADC_SQR2_SQ9_3

#define ADC_SQR2_SQ9_4

#define ADC_SQR2_SQ10

#define ADC_SQR2_SQ10_0

#define ADC_SQR2_SQ10_1

#define ADC_SQR2_SQ10_2

#define ADC_SQR2_SQ10_3

#define ADC_SQR2_SQ10_4

#define ADC_SQR2_SQ11

#define ADC_SQR2_SQ11_0

#define ADC_SQR2_SQ11_1

#define ADC_SQR2_SQ11_2

#define ADC_SQR2_SQ11_3

#define ADC_SQR2_SQ11_4

#define ADC_SQR2_SQ12

#define ADC_SQR2_SQ12_0

#define ADC_SQR2_SQ12_1

#define ADC_SQR2_SQ12_2

#define ADC_SQR2_SQ12_3

#define ADC_SQR2_SQ12_4

#define ADC_SQR3_SQ1

#define ADC_SQR3_SQ1_0

#define ADC_SQR3_SQ1_1

#define ADC_SQR3_SQ1_2

#define ADC_SQR3_SQ1_3

#define ADC_SQR3_SQ1_4

#define ADC_SQR3_SQ2

#define ADC_SQR3_SQ2_0

#define ADC_SQR3_SQ2_1

#define ADC_SQR3_SQ2_2

#define ADC_SQR3_SQ2_3

#define ADC_SQR3_SQ2_4

#define ADC_SQR3_SQ3

#define ADC_SQR3_SQ3_0

#define ADC_SQR3_SQ3_1

#define ADC_SQR3_SQ3_2

#define ADC_SQR3_SQ3_3

#define ADC_SQR3_SQ3_4

#define ADC_SQR3_SQ4

#define ADC_SQR3_SQ4_0

#define ADC_SQR3_SQ4_1

#define ADC_SQR3_SQ4_2

#define ADC_SQR3_SQ4_3

#define ADC_SQR3_SQ4_4

#define ADC_SQR3_SQ5

#define ADC_SQR3_SQ5_0

#define ADC_SQR3_SQ5_1

#define ADC_SQR3_SQ5_2

#define ADC_SQR3_SQ5_3

#define ADC_SQR3_SQ5_4

#define ADC_SQR3_SQ6

#define ADC_SQR3_SQ6_0

#define ADC_SQR3_SQ6_1

#define ADC_SQR3_SQ6_2

#define ADC_SQR3_SQ6_3

#define ADC_SQR3_SQ6_4

#define ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_4

#define ADC_JSQR_JL

#define ADC_JSQR_JL_0

#define ADC_JSQR_JL_1

#define ADC_JDR1_JDATA

#define ADC_JDR2_JDATA

#define ADC_JDR3_JDATA

#define ADC_JDR4_JDATA

#define ADC_DR_DATA

#define ADC_DR_ADC2DATA

#define ADC_CSR_AWD1

#define ADC_CSR_EOC1

#define ADC_CSR_JEOC1

#define ADC_CSR_JSTRT1

#define ADC_CSR_STRT1

#define ADC_CSR_DOVR1

#define ADC_CSR_AWD2

#define ADC_CSR_EOC2

#define ADC_CSR_JEOC2

#define ADC_CSR_JSTRT2

#define ADC_CSR_STRT2

#define ADC_CSR_DOVR2

#define ADC_CSR_AWD3

#define ADC_CSR_EOC3

#define ADC_CSR_JEOC3

#define ADC_CSR_JSTRT3

#define ADC_CSR_STRT3

#define ADC_CSR_DOVR3

#define ADC_CCR_MULTI

#define ADC_CCR_MULTI_0

#define ADC_CCR_MULTI_1

#define ADC_CCR_MULTI_2

#define ADC_CCR_MULTI_3

#define ADC_CCR_MULTI_4

#define ADC_CCR_DELAY

#define ADC_CCR_DELAY_0

#define ADC_CCR_DELAY_1

#define ADC_CCR_DELAY_2

#define ADC_CCR_DELAY_3

#define ADC_CCR_DDS

#define ADC_CCR_DMA

#define ADC_CCR_DMA_0

#define ADC_CCR_DMA_1

#define ADC_CCR_ADCPRE

#define ADC_CCR_ADCPRE_0

#define ADC_CCR_ADCPRE_1

#define ADC_CCR_VBATE

#define ADC_CCR_TSVREFE

#define ADC_CDR_DATA1

#define ADC_CDR_DATA2

#define CRC_DR_DR

#define CRC_IDR_IDR

#define CRC_CR_RESET

#define DMA_SxCR_CHSEL

#define DMA_SxCR_CHSEL_0

#define DMA_SxCR_CHSEL_1

#define DMA_SxCR_CHSEL_2

#define DMA_SxCR_MBURST

#define DMA_SxCR_MBURST_0

#define DMA_SxCR_MBURST_1

#define DMA_SxCR_PBURST

#define DMA_SxCR_PBURST_0

#define DMA_SxCR_PBURST_1

#define DMA_SxCR_ACK

#define DMA_SxCR_CT

#define DMA_SxCR_DBM

#define DMA_SxCR_PL

#define DMA_SxCR_PL_0

#define DMA_SxCR_PL_1

#define DMA_SxCR_PINCOS

#define DMA_SxCR_MSIZE

#define DMA_SxCR_MSIZE_0

#define DMA_SxCR_MSIZE_1

#define DMA_SxCR_PSIZE

#define DMA_SxCR_PSIZE_0

#define DMA_SxCR_PSIZE_1

#define DMA_SxCR_MINC

#define DMA_SxCR_PINC

#define DMA_SxCR_CIRC

#define DMA_SxCR_DIR

#define DMA_SxCR_DIR_0

#define DMA_SxCR_DIR_1

#define DMA_SxCR_PFCTRL

#define DMA_SxCR_TCIE

#define DMA_SxCR_HTIE

#define DMA_SxCR_TEIE

#define DMA_SxCR_DMEIE

#define DMA_SxCR_EN

#define DMA_SxNDT

#define DMA_SxNDT_0

#define DMA_SxNDT_1

#define DMA_SxNDT_2

#define DMA_SxNDT_3

#define DMA_SxNDT_4

#define DMA_SxNDT_5

#define DMA_SxNDT_6

#define DMA_SxNDT_7

#define DMA_SxNDT_8

#define DMA_SxNDT_9

#define DMA_SxNDT_10

#define DMA_SxNDT_11

#define DMA_SxNDT_12

#define DMA_SxNDT_13

#define DMA_SxNDT_14

#define DMA_SxNDT_15

#define DMA_SxFCR_FEIE

#define DMA_SxFCR_FS

#define DMA_SxFCR_FS_0

#define DMA_SxFCR_FS_1

#define DMA_SxFCR_FS_2

#define DMA_SxFCR_DMDIS

#define DMA_SxFCR_FTH

#define DMA_SxFCR_FTH_0

#define DMA_SxFCR_FTH_1

#define DMA_LISR_TCIF3

#define DMA_LISR_HTIF3

#define DMA_LISR_TEIF3

#define DMA_LISR_DMEIF3

#define DMA_LISR_FEIF3

#define DMA_LISR_TCIF2

#define DMA_LISR_HTIF2

#define DMA_LISR_TEIF2

#define DMA_LISR_DMEIF2

#define DMA_LISR_FEIF2

#define DMA_LISR_TCIF1

#define DMA_LISR_HTIF1

#define DMA_LISR_TEIF1

#define DMA_LISR_DMEIF1

#define DMA_LISR_FEIF1

#define DMA_LISR_TCIF0

#define DMA_LISR_HTIF0

#define DMA_LISR_TEIF0

#define DMA_LISR_DMEIF0

#define DMA_LISR_FEIF0

#define DMA_HISR_TCIF7

#define DMA_HISR_HTIF7

#define DMA_HISR_TEIF7

#define DMA_HISR_DMEIF7

#define DMA_HISR_FEIF7

#define DMA_HISR_TCIF6

#define DMA_HISR_HTIF6

#define DMA_HISR_TEIF6

#define DMA_HISR_DMEIF6

#define DMA_HISR_FEIF6

#define DMA_HISR_TCIF5

#define DMA_HISR_HTIF5

#define DMA_HISR_TEIF5

#define DMA_HISR_DMEIF5

#define DMA_HISR_FEIF5

#define DMA_HISR_TCIF4

#define DMA_HISR_HTIF4

#define DMA_HISR_TEIF4

#define DMA_HISR_DMEIF4

#define DMA_HISR_FEIF4

#define DMA_LIFCR_CTCIF3

#define DMA_LIFCR_CHTIF3

#define DMA_LIFCR_CTEIF3

#define DMA_LIFCR_CDMEIF3

#define DMA_LIFCR_CFEIF3

#define DMA_LIFCR_CTCIF2

#define DMA_LIFCR_CHTIF2

#define DMA_LIFCR_CTEIF2

#define DMA_LIFCR_CDMEIF2

#define DMA_LIFCR_CFEIF2

#define DMA_LIFCR_CTCIF1

#define DMA_LIFCR_CHTIF1

#define DMA_LIFCR_CTEIF1

#define DMA_LIFCR_CDMEIF1

#define DMA_LIFCR_CFEIF1

#define DMA_LIFCR_CTCIF0

#define DMA_LIFCR_CHTIF0

#define DMA_LIFCR_CTEIF0

#define DMA_LIFCR_CDMEIF0

#define DMA_LIFCR_CFEIF0

#define DMA_HIFCR_CTCIF7

#define DMA_HIFCR_CHTIF7

#define DMA_HIFCR_CTEIF7

#define DMA_HIFCR_CDMEIF7

#define DMA_HIFCR_CFEIF7

#define DMA_HIFCR_CTCIF6

#define DMA_HIFCR_CHTIF6

#define DMA_HIFCR_CTEIF6

#define DMA_HIFCR_CDMEIF6

#define DMA_HIFCR_CFEIF6

#define DMA_HIFCR_CTCIF5

#define DMA_HIFCR_CHTIF5

#define DMA_HIFCR_CTEIF5

#define DMA_HIFCR_CDMEIF5

#define DMA_HIFCR_CFEIF5

#define DMA_HIFCR_CTCIF4

#define DMA_HIFCR_CHTIF4

#define DMA_HIFCR_CTEIF4

#define DMA_HIFCR_CDMEIF4

#define DMA_HIFCR_CFEIF4

#define EXTI_IMR_MR0

#define EXTI_IMR_MR1

#define EXTI_IMR_MR2

#define EXTI_IMR_MR3

#define EXTI_IMR_MR4

#define EXTI_IMR_MR5

#define EXTI_IMR_MR6

#define EXTI_IMR_MR7

#define EXTI_IMR_MR8

#define EXTI_IMR_MR9

#define EXTI_IMR_MR10

#define EXTI_IMR_MR11

#define EXTI_IMR_MR12

#define EXTI_IMR_MR13

#define EXTI_IMR_MR14

#define EXTI_IMR_MR15

#define EXTI_IMR_MR16

#define EXTI_IMR_MR17

#define EXTI_IMR_MR18

#define EXTI_IMR_MR19

#define EXTI_EMR_MR0

#define EXTI_EMR_MR1

#define EXTI_EMR_MR2

#define EXTI_EMR_MR3

#define EXTI_EMR_MR4

#define EXTI_EMR_MR5

#define EXTI_EMR_MR6

#define EXTI_EMR_MR7

#define EXTI_EMR_MR8

#define EXTI_EMR_MR9

#define EXTI_EMR_MR10

#define EXTI_EMR_MR11

#define EXTI_EMR_MR12

#define EXTI_EMR_MR13

#define EXTI_EMR_MR14

#define EXTI_EMR_MR15

#define EXTI_EMR_MR16

#define EXTI_EMR_MR17

#define EXTI_EMR_MR18

#define EXTI_EMR_MR19

#define EXTI_RTSR_TR0

#define EXTI_RTSR_TR1

#define EXTI_RTSR_TR2

#define EXTI_RTSR_TR3

#define EXTI_RTSR_TR4

#define EXTI_RTSR_TR5

#define EXTI_RTSR_TR6

#define EXTI_RTSR_TR7

#define EXTI_RTSR_TR8

#define EXTI_RTSR_TR9

#define EXTI_RTSR_TR10

#define EXTI_RTSR_TR11

#define EXTI_RTSR_TR12

#define EXTI_RTSR_TR13

#define EXTI_RTSR_TR14

#define EXTI_RTSR_TR15

#define EXTI_RTSR_TR16

#define EXTI_RTSR_TR17

#define EXTI_RTSR_TR18

#define EXTI_RTSR_TR19

#define EXTI_FTSR_TR0

#define EXTI_FTSR_TR1

#define EXTI_FTSR_TR2

#define EXTI_FTSR_TR3

#define EXTI_FTSR_TR4

#define EXTI_FTSR_TR5

#define EXTI_FTSR_TR6

#define EXTI_FTSR_TR7

#define EXTI_FTSR_TR8

#define EXTI_FTSR_TR9

#define EXTI_FTSR_TR10

#define EXTI_FTSR_TR11

#define EXTI_FTSR_TR12

#define EXTI_FTSR_TR13

#define EXTI_FTSR_TR14

#define EXTI_FTSR_TR15

#define EXTI_FTSR_TR16

#define EXTI_FTSR_TR17

#define EXTI_FTSR_TR18

#define EXTI_FTSR_TR19

#define EXTI_SWIER_SWIER0

#define EXTI_SWIER_SWIER1

#define EXTI_SWIER_SWIER2

#define EXTI_SWIER_SWIER3

#define EXTI_SWIER_SWIER4

#define EXTI_SWIER_SWIER5

#define EXTI_SWIER_SWIER6

#define EXTI_SWIER_SWIER7

#define EXTI_SWIER_SWIER8

#define EXTI_SWIER_SWIER9

#define EXTI_SWIER_SWIER10

#define EXTI_SWIER_SWIER11

#define EXTI_SWIER_SWIER12

#define EXTI_SWIER_SWIER13

#define EXTI_SWIER_SWIER14

#define EXTI_SWIER_SWIER15

#define EXTI_SWIER_SWIER16

#define EXTI_SWIER_SWIER17

#define EXTI_SWIER_SWIER18

#define EXTI_SWIER_SWIER19

#define EXTI_PR_PR0

#define EXTI_PR_PR1

#define EXTI_PR_PR2

#define EXTI_PR_PR3

#define EXTI_PR_PR4

#define EXTI_PR_PR5

#define EXTI_PR_PR6

#define EXTI_PR_PR7

#define EXTI_PR_PR8

#define EXTI_PR_PR9

#define EXTI_PR_PR10

#define EXTI_PR_PR11

#define EXTI_PR_PR12

#define EXTI_PR_PR13

#define EXTI_PR_PR14

#define EXTI_PR_PR15

#define EXTI_PR_PR16

#define EXTI_PR_PR17

#define EXTI_PR_PR18

#define EXTI_PR_PR19

#define FLASH_ACR_LATENCY

#define FLASH_ACR_LATENCY_0WS

#define FLASH_ACR_LATENCY_1WS

#define FLASH_ACR_LATENCY_2WS

#define FLASH_ACR_LATENCY_3WS

#define FLASH_ACR_LATENCY_4WS

#define FLASH_ACR_LATENCY_5WS

#define FLASH_ACR_LATENCY_6WS

#define FLASH_ACR_LATENCY_7WS

#define FLASH_ACR_PRFTEN

#define FLASH_ACR_ICEN

#define FLASH_ACR_DCEN

#define FLASH_ACR_ICRST

#define FLASH_ACR_DCRST

#define FLASH_ACR_BYTE0_ADDRESS

#define FLASH_ACR_BYTE2_ADDRESS

#define FLASH_SR_EOP

#define FLASH_SR_SOP

#define FLASH_SR_WRPERR

#define FLASH_SR_PGAERR

#define FLASH_SR_PGPERR

#define FLASH_SR_PGSERR

#define FLASH_SR_BSY

#define FLASH_CR_PG

#define FLASH_CR_SER

#define FLASH_CR_MER

#define FLASH_CR_SNB

#define FLASH_CR_SNB_0

#define FLASH_CR_SNB_1

#define FLASH_CR_SNB_2

#define FLASH_CR_SNB_3

#define FLASH_CR_SNB_4

#define FLASH_CR_PSIZE

#define FLASH_CR_PSIZE_0

#define FLASH_CR_PSIZE_1

#define FLASH_CR_STRT

#define FLASH_CR_EOPIE

#define FLASH_CR_LOCK

#define FLASH_OPTCR_OPTLOCK

#define FLASH_OPTCR_OPTSTRT

#define FLASH_OPTCR_BOR_LEV_0

#define FLASH_OPTCR_BOR_LEV_1

#define FLASH_OPTCR_BOR_LEV

#define FLASH_OPTCR_WDG_SW

#define FLASH_OPTCR_nRST_STOP

#define FLASH_OPTCR_nRST_STDBY

#define FLASH_OPTCR_RDP

#define FLASH_OPTCR_RDP_0

#define FLASH_OPTCR_RDP_1

#define FLASH_OPTCR_RDP_2

#define FLASH_OPTCR_RDP_3

#define FLASH_OPTCR_RDP_4

#define FLASH_OPTCR_RDP_5

#define FLASH_OPTCR_RDP_6

#define FLASH_OPTCR_RDP_7

#define FLASH_OPTCR_nWRP

#define FLASH_OPTCR_nWRP_0

#define FLASH_OPTCR_nWRP_1

#define FLASH_OPTCR_nWRP_2

#define FLASH_OPTCR_nWRP_3

#define FLASH_OPTCR_nWRP_4

#define FLASH_OPTCR_nWRP_5

#define FLASH_OPTCR_nWRP_6

#define FLASH_OPTCR_nWRP_7

#define FLASH_OPTCR_nWRP_8

#define FLASH_OPTCR_nWRP_9

#define FLASH_OPTCR_nWRP_10

#define FLASH_OPTCR_nWRP_11

#define FLASH_OPTCR1_nWRP

#define FLASH_OPTCR1_nWRP_0

#define FLASH_OPTCR1_nWRP_1

#define FLASH_OPTCR1_nWRP_2

#define FLASH_OPTCR1_nWRP_3

#define FLASH_OPTCR1_nWRP_4

#define FLASH_OPTCR1_nWRP_5

#define FLASH_OPTCR1_nWRP_6

#define FLASH_OPTCR1_nWRP_7

#define FLASH_OPTCR1_nWRP_8

#define FLASH_OPTCR1_nWRP_9

#define FLASH_OPTCR1_nWRP_10

#define FLASH_OPTCR1_nWRP_11

#define GPIO_MODER_MODER0

#define GPIO_MODER_MODER0_0

#define GPIO_MODER_MODER0_1

#define GPIO_MODER_MODER1

#define GPIO_MODER_MODER1_0

#define GPIO_MODER_MODER1_1

#define GPIO_MODER_MODER2

#define GPIO_MODER_MODER2_0

#define GPIO_MODER_MODER2_1

#define GPIO_MODER_MODER3

#define GPIO_MODER_MODER3_0

#define GPIO_MODER_MODER3_1

#define GPIO_MODER_MODER4

#define GPIO_MODER_MODER4_0

#define GPIO_MODER_MODER4_1

#define GPIO_MODER_MODER5

#define GPIO_MODER_MODER5_0

#define GPIO_MODER_MODER5_1

#define GPIO_MODER_MODER6

#define GPIO_MODER_MODER6_0

#define GPIO_MODER_MODER6_1

#define GPIO_MODER_MODER7

#define GPIO_MODER_MODER7_0

#define GPIO_MODER_MODER7_1

#define GPIO_MODER_MODER8

#define GPIO_MODER_MODER8_0

#define GPIO_MODER_MODER8_1

#define GPIO_MODER_MODER9

#define GPIO_MODER_MODER9_0

#define GPIO_MODER_MODER9_1

#define GPIO_MODER_MODER10

#define GPIO_MODER_MODER10_0

#define GPIO_MODER_MODER10_1

#define GPIO_MODER_MODER11

#define GPIO_MODER_MODER11_0

#define GPIO_MODER_MODER11_1

#define GPIO_MODER_MODER12

#define GPIO_MODER_MODER12_0

#define GPIO_MODER_MODER12_1

#define GPIO_MODER_MODER13

#define GPIO_MODER_MODER13_0

#define GPIO_MODER_MODER13_1

#define GPIO_MODER_MODER14

#define GPIO_MODER_MODER14_0

#define GPIO_MODER_MODER14_1

#define GPIO_MODER_MODER15

#define GPIO_MODER_MODER15_0

#define GPIO_MODER_MODER15_1

#define GPIO_OTYPER_OT_0

#define GPIO_OTYPER_OT_1

#define GPIO_OTYPER_OT_2

#define GPIO_OTYPER_OT_3

#define GPIO_OTYPER_OT_4

#define GPIO_OTYPER_OT_5

#define GPIO_OTYPER_OT_6

#define GPIO_OTYPER_OT_7

#define GPIO_OTYPER_OT_8

#define GPIO_OTYPER_OT_9

#define GPIO_OTYPER_OT_10

#define GPIO_OTYPER_OT_11

#define GPIO_OTYPER_OT_12

#define GPIO_OTYPER_OT_13

#define GPIO_OTYPER_OT_14

#define GPIO_OTYPER_OT_15

#define GPIO_OSPEEDER_OSPEEDR0

#define GPIO_OSPEEDER_OSPEEDR0_0

#define GPIO_OSPEEDER_OSPEEDR0_1

#define GPIO_OSPEEDER_OSPEEDR1

#define GPIO_OSPEEDER_OSPEEDR1_0

#define GPIO_OSPEEDER_OSPEEDR1_1

#define GPIO_OSPEEDER_OSPEEDR2

#define GPIO_OSPEEDER_OSPEEDR2_0

#define GPIO_OSPEEDER_OSPEEDR2_1

#define GPIO_OSPEEDER_OSPEEDR3

#define GPIO_OSPEEDER_OSPEEDR3_0

#define GPIO_OSPEEDER_OSPEEDR3_1

#define GPIO_OSPEEDER_OSPEEDR4

#define GPIO_OSPEEDER_OSPEEDR4_0

#define GPIO_OSPEEDER_OSPEEDR4_1

#define GPIO_OSPEEDER_OSPEEDR5

#define GPIO_OSPEEDER_OSPEEDR5_0

#define GPIO_OSPEEDER_OSPEEDR5_1

#define GPIO_OSPEEDER_OSPEEDR6

#define GPIO_OSPEEDER_OSPEEDR6_0

#define GPIO_OSPEEDER_OSPEEDR6_1

#define GPIO_OSPEEDER_OSPEEDR7

#define GPIO_OSPEEDER_OSPEEDR7_0

#define GPIO_OSPEEDER_OSPEEDR7_1

#define GPIO_OSPEEDER_OSPEEDR8

#define GPIO_OSPEEDER_OSPEEDR8_0

#define GPIO_OSPEEDER_OSPEEDR8_1

#define GPIO_OSPEEDER_OSPEEDR9

#define GPIO_OSPEEDER_OSPEEDR9_0

#define GPIO_OSPEEDER_OSPEEDR9_1

#define GPIO_OSPEEDER_OSPEEDR10

#define GPIO_OSPEEDER_OSPEEDR10_0

#define GPIO_OSPEEDER_OSPEEDR10_1

#define GPIO_OSPEEDER_OSPEEDR11

#define GPIO_OSPEEDER_OSPEEDR11_0

#define GPIO_OSPEEDER_OSPEEDR11_1

#define GPIO_OSPEEDER_OSPEEDR12

#define GPIO_OSPEEDER_OSPEEDR12_0

#define GPIO_OSPEEDER_OSPEEDR12_1

#define GPIO_OSPEEDER_OSPEEDR13

#define GPIO_OSPEEDER_OSPEEDR13_0

#define GPIO_OSPEEDER_OSPEEDR13_1

#define GPIO_OSPEEDER_OSPEEDR14

#define GPIO_OSPEEDER_OSPEEDR14_0

#define GPIO_OSPEEDER_OSPEEDR14_1

#define GPIO_OSPEEDER_OSPEEDR15

#define GPIO_OSPEEDER_OSPEEDR15_0

#define GPIO_OSPEEDER_OSPEEDR15_1

#define GPIO_PUPDR_PUPDR0

#define GPIO_PUPDR_PUPDR0_0

#define GPIO_PUPDR_PUPDR0_1

#define GPIO_PUPDR_PUPDR1

#define GPIO_PUPDR_PUPDR1_0

#define GPIO_PUPDR_PUPDR1_1

#define GPIO_PUPDR_PUPDR2

#define GPIO_PUPDR_PUPDR2_0

#define GPIO_PUPDR_PUPDR2_1

#define GPIO_PUPDR_PUPDR3

#define GPIO_PUPDR_PUPDR3_0

#define GPIO_PUPDR_PUPDR3_1

#define GPIO_PUPDR_PUPDR4

#define GPIO_PUPDR_PUPDR4_0

#define GPIO_PUPDR_PUPDR4_1

#define GPIO_PUPDR_PUPDR5

#define GPIO_PUPDR_PUPDR5_0

#define GPIO_PUPDR_PUPDR5_1

#define GPIO_PUPDR_PUPDR6

#define GPIO_PUPDR_PUPDR6_0

#define GPIO_PUPDR_PUPDR6_1

#define GPIO_PUPDR_PUPDR7

#define GPIO_PUPDR_PUPDR7_0

#define GPIO_PUPDR_PUPDR7_1

#define GPIO_PUPDR_PUPDR8

#define GPIO_PUPDR_PUPDR8_0

#define GPIO_PUPDR_PUPDR8_1

#define GPIO_PUPDR_PUPDR9

#define GPIO_PUPDR_PUPDR9_0

#define GPIO_PUPDR_PUPDR9_1

#define GPIO_PUPDR_PUPDR10

#define GPIO_PUPDR_PUPDR10_0

#define GPIO_PUPDR_PUPDR10_1

#define GPIO_PUPDR_PUPDR11

#define GPIO_PUPDR_PUPDR11_0

#define GPIO_PUPDR_PUPDR11_1

#define GPIO_PUPDR_PUPDR12

#define GPIO_PUPDR_PUPDR12_0

#define GPIO_PUPDR_PUPDR12_1

#define GPIO_PUPDR_PUPDR13

#define GPIO_PUPDR_PUPDR13_0

#define GPIO_PUPDR_PUPDR13_1

#define GPIO_PUPDR_PUPDR14

#define GPIO_PUPDR_PUPDR14_0

#define GPIO_PUPDR_PUPDR14_1

#define GPIO_PUPDR_PUPDR15

#define GPIO_PUPDR_PUPDR15_0

#define GPIO_PUPDR_PUPDR15_1

#define GPIO_IDR_IDR_0

#define GPIO_IDR_IDR_1

#define GPIO_IDR_IDR_2

#define GPIO_IDR_IDR_3

#define GPIO_IDR_IDR_4

#define GPIO_IDR_IDR_5

#define GPIO_IDR_IDR_6

#define GPIO_IDR_IDR_7

#define GPIO_IDR_IDR_8

#define GPIO_IDR_IDR_9

#define GPIO_IDR_IDR_10

#define GPIO_IDR_IDR_11

#define GPIO_IDR_IDR_12

#define GPIO_IDR_IDR_13

#define GPIO_IDR_IDR_14

#define GPIO_IDR_IDR_15

#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0

#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1

#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2

#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3

#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4

#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5

#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6

#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7

#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8

#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9

#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10

#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11

#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12

#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13

#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14

#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15

#define GPIO_ODR_ODR_0

#define GPIO_ODR_ODR_1

#define GPIO_ODR_ODR_2

#define GPIO_ODR_ODR_3

#define GPIO_ODR_ODR_4

#define GPIO_ODR_ODR_5

#define GPIO_ODR_ODR_6

#define GPIO_ODR_ODR_7

#define GPIO_ODR_ODR_8

#define GPIO_ODR_ODR_9

#define GPIO_ODR_ODR_10

#define GPIO_ODR_ODR_11

#define GPIO_ODR_ODR_12

#define GPIO_ODR_ODR_13

#define GPIO_ODR_ODR_14

#define GPIO_ODR_ODR_15

#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0

#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1

#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2

#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3

#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4

#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5

#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6

#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7

#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8

#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9

#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10

#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11

#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12

#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13

#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14

#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15

#define GPIO_BSRR_BS_0

#define GPIO_BSRR_BS_1

#define GPIO_BSRR_BS_2

#define GPIO_BSRR_BS_3

#define GPIO_BSRR_BS_4

#define GPIO_BSRR_BS_5

#define GPIO_BSRR_BS_6

#define GPIO_BSRR_BS_7

#define GPIO_BSRR_BS_8

#define GPIO_BSRR_BS_9

#define GPIO_BSRR_BS_10

#define GPIO_BSRR_BS_11

#define GPIO_BSRR_BS_12

#define GPIO_BSRR_BS_13

#define GPIO_BSRR_BS_14

#define GPIO_BSRR_BS_15

#define GPIO_BSRR_BR_0

#define GPIO_BSRR_BR_1

#define GPIO_BSRR_BR_2

#define GPIO_BSRR_BR_3

#define GPIO_BSRR_BR_4

#define GPIO_BSRR_BR_5

#define GPIO_BSRR_BR_6

#define GPIO_BSRR_BR_7

#define GPIO_BSRR_BR_8

#define GPIO_BSRR_BR_9

#define GPIO_BSRR_BR_10

#define GPIO_BSRR_BR_11

#define GPIO_BSRR_BR_12

#define GPIO_BSRR_BR_13

#define GPIO_BSRR_BR_14

#define GPIO_BSRR_BR_15

#define I2C_CR1_PE

#define I2C_CR1_SMBUS

#define I2C_CR1_SMBTYPE

#define I2C_CR1_ENARP

#define I2C_CR1_ENPEC

#define I2C_CR1_ENGC

#define I2C_CR1_NOSTRETCH

#define I2C_CR1_START

#define I2C_CR1_STOP

#define I2C_CR1_ACK

#define I2C_CR1_POS

#define I2C_CR1_PEC

#define I2C_CR1_ALERT

#define I2C_CR1_SWRST

#define I2C_CR2_FREQ

#define I2C_CR2_FREQ_0

#define I2C_CR2_FREQ_1

#define I2C_CR2_FREQ_2

#define I2C_CR2_FREQ_3

#define I2C_CR2_FREQ_4

#define I2C_CR2_FREQ_5

#define I2C_CR2_ITERREN

#define I2C_CR2_ITEVTEN

#define I2C_CR2_ITBUFEN

#define I2C_CR2_DMAEN

#define I2C_CR2_LAST

#define I2C_OAR1_ADD1_7

#define I2C_OAR1_ADD8_9

#define I2C_OAR1_ADD0

#define I2C_OAR1_ADD1

#define I2C_OAR1_ADD2

#define I2C_OAR1_ADD3

#define I2C_OAR1_ADD4

#define I2C_OAR1_ADD5

#define I2C_OAR1_ADD6

#define I2C_OAR1_ADD7

#define I2C_OAR1_ADD8

#define I2C_OAR1_ADD9

#define I2C_OAR1_ADDMODE

#define I2C_OAR2_ENDUAL

#define I2C_OAR2_ADD2

#define I2C_DR_DR

#define I2C_SR1_SB

#define I2C_SR1_ADDR

#define I2C_SR1_BTF

#define I2C_SR1_ADD10

#define I2C_SR1_STOPF

#define I2C_SR1_RXNE

#define I2C_SR1_TXE

#define I2C_SR1_BERR

#define I2C_SR1_ARLO

#define I2C_SR1_AF

#define I2C_SR1_OVR

#define I2C_SR1_PECERR

#define I2C_SR1_TIMEOUT

#define I2C_SR1_SMBALERT

#define I2C_SR2_MSL

#define I2C_SR2_BUSY

#define I2C_SR2_TRA

#define I2C_SR2_GENCALL

#define I2C_SR2_SMBDEFAULT

#define I2C_SR2_SMBHOST

#define I2C_SR2_DUALF

#define I2C_SR2_PEC

#define I2C_CCR_CCR

#define I2C_CCR_DUTY

#define I2C_CCR_FS

#define I2C_TRISE_TRISE

#define I2C_FLTR_DNF

#define I2C_FLTR_ANOFF

#define IWDG_KR_KEY

#define IWDG_PR_PR

#define IWDG_PR_PR_0

#define IWDG_PR_PR_1

#define IWDG_PR_PR_2

#define IWDG_RLR_RL

#define IWDG_SR_PVU

#define IWDG_SR_RVU

#define PWR_CR_LPDS

#define PWR_CR_PDDS

#define PWR_CR_CWUF

#define PWR_CR_CSBF

#define PWR_CR_PVDE

#define PWR_CR_PLS

#define PWR_CR_PLS_0

#define PWR_CR_PLS_1

#define PWR_CR_PLS_2

#define PWR_CR_PLS_LEV0

#define PWR_CR_PLS_LEV1

#define PWR_CR_PLS_LEV2

#define PWR_CR_PLS_LEV3

#define PWR_CR_PLS_LEV4

#define PWR_CR_PLS_LEV5

#define PWR_CR_PLS_LEV6

#define PWR_CR_PLS_LEV7

#define PWR_CR_DBP

#define PWR_CR_FPDS

#define PWR_CR_VOS

#define PWR_CR_VOS_0

#define PWR_CR_VOS_1

#define PWR_CR_PMODE PWR_CR_VOS

#define PWR_CSR_WUF

#define PWR_CSR_SBF

#define PWR_CSR_PVDO

#define PWR_CSR_BRR

#define PWR_CSR_EWUP

#define PWR_CSR_BRE

#define PWR_CSR_VOSRDY

#define PWR_CSR_REGRDY PWR_CSR_VOSRDY

#define RCC_CR_HSION

#define RCC_CR_HSIRDY

#define RCC_CR_HSITRIM

#define RCC_CR_HSITRIM_0

#define RCC_CR_HSITRIM_1

#define RCC_CR_HSITRIM_2

#define RCC_CR_HSITRIM_3

#define RCC_CR_HSITRIM_4

#define RCC_CR_HSICAL

#define RCC_CR_HSICAL_0

#define RCC_CR_HSICAL_1

#define RCC_CR_HSICAL_2

#define RCC_CR_HSICAL_3

#define RCC_CR_HSICAL_4

#define RCC_CR_HSICAL_5

#define RCC_CR_HSICAL_6

#define RCC_CR_HSICAL_7

#define RCC_CR_HSEON

#define RCC_CR_HSERDY

#define RCC_CR_HSEBYP

#define RCC_CR_CSSON

#define RCC_CR_PLLON

#define RCC_CR_PLLRDY

#define RCC_CR_PLLI2SON

#define RCC_CR_PLLI2SRDY

#define RCC_PLLCFGR_PLLM

#define RCC_PLLCFGR_PLLM_0

#define RCC_PLLCFGR_PLLM_1

#define RCC_PLLCFGR_PLLM_2

#define RCC_PLLCFGR_PLLM_3

#define RCC_PLLCFGR_PLLM_4

#define RCC_PLLCFGR_PLLM_5

#define RCC_PLLCFGR_PLLN

#define RCC_PLLCFGR_PLLN_0

#define RCC_PLLCFGR_PLLN_1

#define RCC_PLLCFGR_PLLN_2

#define RCC_PLLCFGR_PLLN_3

#define RCC_PLLCFGR_PLLN_4

#define RCC_PLLCFGR_PLLN_5

#define RCC_PLLCFGR_PLLN_6

#define RCC_PLLCFGR_PLLN_7

#define RCC_PLLCFGR_PLLN_8

#define RCC_PLLCFGR_PLLP

#define RCC_PLLCFGR_PLLP_0

#define RCC_PLLCFGR_PLLP_1

#define RCC_PLLCFGR_PLLSRC

#define RCC_PLLCFGR_PLLSRC_HSE

#define RCC_PLLCFGR_PLLSRC_HSI

#define RCC_PLLCFGR_PLLQ

#define RCC_PLLCFGR_PLLQ_0

#define RCC_PLLCFGR_PLLQ_1

#define RCC_PLLCFGR_PLLQ_2

#define RCC_PLLCFGR_PLLQ_3

#define RCC_CFGR_SW

#define RCC_CFGR_SW_0

#define RCC_CFGR_SW_1

#define RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_PLL

#define RCC_CFGR_SWS

#define RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_PLL

#define RCC_CFGR_HPRE

#define RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV2

#define RCC_CFGR_HPRE_DIV4

#define RCC_CFGR_HPRE_DIV8

#define RCC_CFGR_HPRE_DIV16

#define RCC_CFGR_HPRE_DIV64

#define RCC_CFGR_HPRE_DIV128

#define RCC_CFGR_HPRE_DIV256

#define RCC_CFGR_HPRE_DIV512

#define RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1_0

#define RCC_CFGR_PPRE1_1

#define RCC_CFGR_PPRE1_2

#define RCC_CFGR_PPRE1_DIV1

#define RCC_CFGR_PPRE1_DIV2

#define RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV8

#define RCC_CFGR_PPRE1_DIV16

#define RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2_0

#define RCC_CFGR_PPRE2_1

#define RCC_CFGR_PPRE2_2

#define RCC_CFGR_PPRE2_DIV1

#define RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV4

#define RCC_CFGR_PPRE2_DIV8

#define RCC_CFGR_PPRE2_DIV16

#define RCC_CFGR_RTCPRE

#define RCC_CFGR_RTCPRE_0

#define RCC_CFGR_RTCPRE_1

#define RCC_CFGR_RTCPRE_2

#define RCC_CFGR_RTCPRE_3

#define RCC_CFGR_RTCPRE_4

#define RCC_CFGR_MCO1

#define RCC_CFGR_MCO1_0

#define RCC_CFGR_MCO1_1

#define RCC_CFGR_I2SSRC

#define RCC_CFGR_MCO1PRE

#define RCC_CFGR_MCO1PRE_0

#define RCC_CFGR_MCO1PRE_1

#define RCC_CFGR_MCO1PRE_2

#define RCC_CFGR_MCO2PRE

#define RCC_CFGR_MCO2PRE_0

#define RCC_CFGR_MCO2PRE_1

#define RCC_CFGR_MCO2PRE_2

#define RCC_CFGR_MCO2

#define RCC_CFGR_MCO2_0

#define RCC_CFGR_MCO2_1

#define RCC_CIR_LSIRDYF

#define RCC_CIR_LSERDYF

#define RCC_CIR_HSIRDYF

#define RCC_CIR_HSERDYF

#define RCC_CIR_PLLRDYF

#define RCC_CIR_PLLI2SRDYF

#define RCC_CIR_CSSF

#define RCC_CIR_LSIRDYIE

#define RCC_CIR_LSERDYIE

#define RCC_CIR_HSIRDYIE

#define RCC_CIR_HSERDYIE

#define RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLI2SRDYIE

#define RCC_CIR_LSIRDYC

#define RCC_CIR_LSERDYC

#define RCC_CIR_HSIRDYC

#define RCC_CIR_HSERDYC

#define RCC_CIR_PLLRDYC

#define RCC_CIR_PLLI2SRDYC

#define RCC_CIR_CSSC

#define RCC_AHB1RSTR_GPIOARST

#define RCC_AHB1RSTR_GPIOBRST

#define RCC_AHB1RSTR_GPIOCRST

#define RCC_AHB1RSTR_GPIODRST

#define RCC_AHB1RSTR_GPIOERST

#define RCC_AHB1RSTR_GPIOHRST

#define RCC_AHB1RSTR_CRCRST

#define RCC_AHB1RSTR_DMA1RST

#define RCC_AHB1RSTR_DMA2RST

#define RCC_AHB2RSTR_RNGRST

#define RCC_AHB2RSTR_OTGFSRST

#define RCC_APB1RSTR_TIM2RST

#define RCC_APB1RSTR_TIM3RST

#define RCC_APB1RSTR_TIM4RST

#define RCC_APB1RSTR_TIM5RST

#define RCC_APB1RSTR_WWDGRST

#define RCC_APB1RSTR_SPI2RST

#define RCC_APB1RSTR_SPI3RST

#define RCC_APB1RSTR_USART2RST

#define RCC_APB1RSTR_I2C1RST

#define RCC_APB1RSTR_I2C2RST

#define RCC_APB1RSTR_I2C3RST

#define RCC_APB1RSTR_PWRRST

#define RCC_APB2RSTR_TIM1RST

#define RCC_APB2RSTR_USART1RST

#define RCC_APB2RSTR_USART6RST

#define RCC_APB2RSTR_ADCRST

#define RCC_APB2RSTR_SDIORST

#define RCC_APB2RSTR_SPI1RST

#define RCC_APB2RSTR_SPI4RST

#define RCC_APB2RSTR_SYSCFGRST

#define RCC_APB2RSTR_TIM9RST

#define RCC_APB2RSTR_TIM10RST

#define RCC_APB2RSTR_TIM11RST

#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST

#define RCC_AHB1ENR_GPIOAEN

#define RCC_AHB1ENR_GPIOBEN

#define RCC_AHB1ENR_GPIOCEN

#define RCC_AHB1ENR_GPIODEN

#define RCC_AHB1ENR_GPIOEEN

#define RCC_AHB1ENR_GPIOHEN

#define RCC_AHB1ENR_CRCEN

#define RCC_AHB1ENR_BKPSRAMEN

#define RCC_AHB1ENR_CCMDATARAMEN

#define RCC_AHB1ENR_DMA1EN

#define RCC_AHB1ENR_DMA2EN

#define RCC_AHB2ENR_RNGEN

#define RCC_AHB2ENR_OTGFSEN

#define RCC_APB1ENR_TIM2EN

#define RCC_APB1ENR_TIM3EN

#define RCC_APB1ENR_TIM4EN

#define RCC_APB1ENR_TIM5EN

#define RCC_APB1ENR_WWDGEN

#define RCC_APB1ENR_SPI2EN

#define RCC_APB1ENR_SPI3EN

#define RCC_APB1ENR_USART2EN

#define RCC_APB1ENR_I2C1EN

#define RCC_APB1ENR_I2C2EN

#define RCC_APB1ENR_I2C3EN

#define RCC_APB1ENR_PWREN

#define RCC_APB2ENR_TIM1EN

#define RCC_APB2ENR_USART1EN

#define RCC_APB2ENR_USART6EN

#define RCC_APB2ENR_ADC1EN

#define RCC_APB2ENR_SDIOEN

#define RCC_APB2ENR_SPI1EN

#define RCC_APB2ENR_SPI4EN

#define RCC_APB2ENR_SYSCFGEN

#define RCC_APB2ENR_TIM9EN

#define RCC_APB2ENR_TIM10EN

#define RCC_APB2ENR_TIM11EN

#define RCC_AHB1LPENR_GPIOALPEN

#define RCC_AHB1LPENR_GPIOBLPEN

#define RCC_AHB1LPENR_GPIOCLPEN

#define RCC_AHB1LPENR_GPIODLPEN

#define RCC_AHB1LPENR_GPIOELPEN

#define RCC_AHB1LPENR_GPIOHLPEN

#define RCC_AHB1LPENR_CRCLPEN

#define RCC_AHB1LPENR_FLITFLPEN

#define RCC_AHB1LPENR_SRAM1LPEN

#define RCC_AHB1LPENR_SRAM2LPEN

#define RCC_AHB1LPENR_BKPSRAMLPEN

#define RCC_AHB1LPENR_SRAM3LPEN

#define RCC_AHB1LPENR_DMA1LPEN

#define RCC_AHB1LPENR_DMA2LPEN

#define RCC_AHB2LPENR_RNGLPEN

#define RCC_AHB2LPENR_OTGFSLPEN

#define RCC_APB1LPENR_TIM2LPEN

#define RCC_APB1LPENR_TIM3LPEN

#define RCC_APB1LPENR_TIM4LPEN

#define RCC_APB1LPENR_TIM5LPEN

#define RCC_APB1LPENR_WWDGLPEN

#define RCC_APB1LPENR_SPI2LPEN

#define RCC_APB1LPENR_SPI3LPEN

#define RCC_APB1LPENR_USART2LPEN

#define RCC_APB1LPENR_I2C1LPEN

#define RCC_APB1LPENR_I2C2LPEN

#define RCC_APB1LPENR_I2C3LPEN

#define RCC_APB1LPENR_PWRLPEN

#define RCC_APB1LPENR_DACLPEN

#define RCC_APB2LPENR_TIM1LPEN

#define RCC_APB2LPENR_USART1LPEN

#define RCC_APB2LPENR_USART6LPEN

#define RCC_APB2LPENR_ADC1LPEN

#define RCC_APB2LPENR_SDIOLPEN

#define RCC_APB2LPENR_SPI1LPEN

#define RCC_APB2LPENR_SPI4LPEN

#define RCC_APB2LPENR_SYSCFGLPEN

#define RCC_APB2LPENR_TIM9LPEN

#define RCC_APB2LPENR_TIM10LPEN

#define RCC_APB2LPENR_TIM11LPEN

#define RCC_BDCR_LSEON

#define RCC_BDCR_LSERDY

#define RCC_BDCR_LSEBYP

#define RCC_BDCR_RTCSEL

#define RCC_BDCR_RTCSEL_0

#define RCC_BDCR_RTCSEL_1

#define RCC_BDCR_RTCEN

#define RCC_BDCR_BDRST

#define RCC_CSR_LSION

#define RCC_CSR_LSIRDY

#define RCC_CSR_RMVF

#define RCC_CSR_BORRSTF

#define RCC_CSR_PADRSTF

#define RCC_CSR_PORRSTF

#define RCC_CSR_SFTRSTF

#define RCC_CSR_WDGRSTF

#define RCC_CSR_WWDGRSTF

#define RCC_CSR_LPWRRSTF

#define RCC_SSCGR_MODPER

#define RCC_SSCGR_INCSTEP

#define RCC_SSCGR_SPREADSEL

#define RCC_SSCGR_SSCGEN

#define RCC_PLLI2SCFGR_PLLI2SN

#define RCC_PLLI2SCFGR_PLLI2SN_0

#define RCC_PLLI2SCFGR_PLLI2SN_1

#define RCC_PLLI2SCFGR_PLLI2SN_2

#define RCC_PLLI2SCFGR_PLLI2SN_3

#define RCC_PLLI2SCFGR_PLLI2SN_4

#define RCC_PLLI2SCFGR_PLLI2SN_5

#define RCC_PLLI2SCFGR_PLLI2SN_6

#define RCC_PLLI2SCFGR_PLLI2SN_7

#define RCC_PLLI2SCFGR_PLLI2SN_8

#define RCC_PLLI2SCFGR_PLLI2SR

#define RCC_PLLI2SCFGR_PLLI2SR_0

#define RCC_PLLI2SCFGR_PLLI2SR_1

#define RCC_PLLI2SCFGR_PLLI2SR_2

#define RNG_CR_RNGEN

#define RNG_CR_IE

#define RNG_SR_DRDY

#define RNG_SR_CECS

#define RNG_SR_SECS

#define RNG_SR_CEIS

#define RNG_SR_SEIS

#define RTC_TR_PM

#define RTC_TR_HT

#define RTC_TR_HT_0

#define RTC_TR_HT_1

#define RTC_TR_HU

#define RTC_TR_HU_0

#define RTC_TR_HU_1

#define RTC_TR_HU_2

#define RTC_TR_HU_3

#define RTC_TR_MNT

#define RTC_TR_MNT_0

#define RTC_TR_MNT_1

#define RTC_TR_MNT_2

#define RTC_TR_MNU

#define RTC_TR_MNU_0

#define RTC_TR_MNU_1

#define RTC_TR_MNU_2

#define RTC_TR_MNU_3

#define RTC_TR_ST

#define RTC_TR_ST_0

#define RTC_TR_ST_1

#define RTC_TR_ST_2

#define RTC_TR_SU

#define RTC_TR_SU_0

#define RTC_TR_SU_1

#define RTC_TR_SU_2

#define RTC_TR_SU_3

#define RTC_DR_YT

#define RTC_DR_YT_0

#define RTC_DR_YT_1

#define RTC_DR_YT_2

#define RTC_DR_YT_3

#define RTC_DR_YU

#define RTC_DR_YU_0

#define RTC_DR_YU_1

#define RTC_DR_YU_2

#define RTC_DR_YU_3

#define RTC_DR_WDU

#define RTC_DR_WDU_0

#define RTC_DR_WDU_1

#define RTC_DR_WDU_2

#define RTC_DR_MT

#define RTC_DR_MU

#define RTC_DR_MU_0

#define RTC_DR_MU_1

#define RTC_DR_MU_2

#define RTC_DR_MU_3

#define RTC_DR_DT

#define RTC_DR_DT_0

#define RTC_DR_DT_1

#define RTC_DR_DU

#define RTC_DR_DU_0

#define RTC_DR_DU_1

#define RTC_DR_DU_2

#define RTC_DR_DU_3

#define RTC_CR_COE

#define RTC_CR_OSEL

#define RTC_CR_OSEL_0

#define RTC_CR_OSEL_1

#define RTC_CR_POL

#define RTC_CR_COSEL

#define RTC_CR_BCK

#define RTC_CR_SUB1H

#define RTC_CR_ADD1H

#define RTC_CR_TSIE

#define RTC_CR_WUTIE

#define RTC_CR_ALRBIE

#define RTC_CR_ALRAIE

#define RTC_CR_TSE

#define RTC_CR_WUTE

#define RTC_CR_ALRBE

#define RTC_CR_ALRAE

#define RTC_CR_DCE

#define RTC_CR_FMT

#define RTC_CR_BYPSHAD

#define RTC_CR_REFCKON

#define RTC_CR_TSEDGE

#define RTC_CR_WUCKSEL

#define RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_2

#define RTC_ISR_RECALPF

#define RTC_ISR_TAMP1F

#define RTC_ISR_TAMP2F

#define RTC_ISR_TSOVF

#define RTC_ISR_TSF

#define RTC_ISR_WUTF

#define RTC_ISR_ALRBF

#define RTC_ISR_ALRAF

#define RTC_ISR_INIT

#define RTC_ISR_INITF

#define RTC_ISR_RSF

#define RTC_ISR_INITS

#define RTC_ISR_SHPF

#define RTC_ISR_WUTWF

#define RTC_ISR_ALRBWF

#define RTC_ISR_ALRAWF

#define RTC_PRER_PREDIV_A

#define RTC_PRER_PREDIV_S

#define RTC_WUTR_WUT

#define RTC_CALIBR_DCS

#define RTC_CALIBR_DC

#define RTC_ALRMAR_MSK4

#define RTC_ALRMAR_WDSEL

#define RTC_ALRMAR_DT

#define RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DU

#define RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_3

#define RTC_ALRMAR_MSK3

#define RTC_ALRMAR_PM

#define RTC_ALRMAR_HT

#define RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HU

#define RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_3

#define RTC_ALRMAR_MSK2

#define RTC_ALRMAR_MNT

#define RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNU

#define RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MSK1

#define RTC_ALRMAR_ST

#define RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_2

#define RTC_ALRMAR_SU

#define RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_3

#define RTC_ALRMBR_MSK4

#define RTC_ALRMBR_WDSEL

#define RTC_ALRMBR_DT

#define RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DU

#define RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_3

#define RTC_ALRMBR_MSK3

#define RTC_ALRMBR_PM

#define RTC_ALRMBR_HT

#define RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HU

#define RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_3

#define RTC_ALRMBR_MSK2

#define RTC_ALRMBR_MNT

#define RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNU

#define RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MSK1

#define RTC_ALRMBR_ST

#define RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_2

#define RTC_ALRMBR_SU

#define RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_3

#define RTC_WPR_KEY

#define RTC_SSR_SS

#define RTC_SHIFTR_SUBFS

#define RTC_SHIFTR_ADD1S

#define RTC_TSTR_PM

#define RTC_TSTR_HT

#define RTC_TSTR_HT_0

#define RTC_TSTR_HT_1

#define RTC_TSTR_HU

#define RTC_TSTR_HU_0

#define RTC_TSTR_HU_1

#define RTC_TSTR_HU_2

#define RTC_TSTR_HU_3

#define RTC_TSTR_MNT

#define RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_2

#define RTC_TSTR_MNU

#define RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_3

#define RTC_TSTR_ST

#define RTC_TSTR_ST_0

#define RTC_TSTR_ST_1

#define RTC_TSTR_ST_2

#define RTC_TSTR_SU

#define RTC_TSTR_SU_0

#define RTC_TSTR_SU_1

#define RTC_TSTR_SU_2

#define RTC_TSTR_SU_3

#define RTC_TSDR_WDU

#define RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_2

#define RTC_TSDR_MT

#define RTC_TSDR_MU

#define RTC_TSDR_MU_0

#define RTC_TSDR_MU_1

#define RTC_TSDR_MU_2

#define RTC_TSDR_MU_3

#define RTC_TSDR_DT

#define RTC_TSDR_DT_0

#define RTC_TSDR_DT_1

#define RTC_TSDR_DU

#define RTC_TSDR_DU_0

#define RTC_TSDR_DU_1

#define RTC_TSDR_DU_2

#define RTC_TSDR_DU_3

#define RTC_TSSSR_SS

#define RTC_CALR_CALP

#define RTC_CALR_CALW8

#define RTC_CALR_CALW16

#define RTC_CALR_CALM

#define RTC_CALR_CALM_0

#define RTC_CALR_CALM_1

#define RTC_CALR_CALM_2

#define RTC_CALR_CALM_3

#define RTC_CALR_CALM_4

#define RTC_CALR_CALM_5

#define RTC_CALR_CALM_6

#define RTC_CALR_CALM_7

#define RTC_CALR_CALM_8

#define RTC_TAFCR_ALARMOUTTYPE

#define RTC_TAFCR_TSINSEL

#define RTC_TAFCR_TAMPINSEL

#define RTC_TAFCR_TAMPPUDIS

#define RTC_TAFCR_TAMPPRCH

#define RTC_TAFCR_TAMPPRCH_0

#define RTC_TAFCR_TAMPPRCH_1

#define RTC_TAFCR_TAMPFLT

#define RTC_TAFCR_TAMPFLT_0

#define RTC_TAFCR_TAMPFLT_1

#define RTC_TAFCR_TAMPFREQ

#define RTC_TAFCR_TAMPFREQ_0

#define RTC_TAFCR_TAMPFREQ_1

#define RTC_TAFCR_TAMPFREQ_2

#define RTC_TAFCR_TAMPTS

#define RTC_TAFCR_TAMP2TRG

#define RTC_TAFCR_TAMP2E

#define RTC_TAFCR_TAMPIE

#define RTC_TAFCR_TAMP1TRG

#define RTC_TAFCR_TAMP1E

#define RTC_ALRMASSR_MASKSS

#define RTC_ALRMASSR_MASKSS_0

#define RTC_ALRMASSR_MASKSS_1

#define RTC_ALRMASSR_MASKSS_2

#define RTC_ALRMASSR_MASKSS_3

#define RTC_ALRMASSR_SS

#define RTC_ALRMBSSR_MASKSS

#define RTC_ALRMBSSR_MASKSS_0

#define RTC_ALRMBSSR_MASKSS_1

#define RTC_ALRMBSSR_MASKSS_2

#define RTC_ALRMBSSR_MASKSS_3

#define RTC_ALRMBSSR_SS

#define RTC_BKP0R

#define RTC_BKP1R

#define RTC_BKP2R

#define RTC_BKP3R

#define RTC_BKP4R

#define RTC_BKP5R

#define RTC_BKP6R

#define RTC_BKP7R

#define RTC_BKP8R

#define RTC_BKP9R

#define RTC_BKP10R

#define RTC_BKP11R

#define RTC_BKP12R

#define RTC_BKP13R

#define RTC_BKP14R

#define RTC_BKP15R

#define RTC_BKP16R

#define RTC_BKP17R

#define RTC_BKP18R

#define RTC_BKP19R

#define SDIO_POWER_PWRCTRL

#define SDIO_POWER_PWRCTRL_0

#define SDIO_POWER_PWRCTRL_1

#define SDIO_CLKCR_CLKDIV

#define SDIO_CLKCR_CLKEN

#define SDIO_CLKCR_PWRSAV

#define SDIO_CLKCR_BYPASS

#define SDIO_CLKCR_WIDBUS

#define SDIO_CLKCR_WIDBUS_0

#define SDIO_CLKCR_WIDBUS_1

#define SDIO_CLKCR_NEGEDGE

#define SDIO_CLKCR_HWFC_EN

#define SDIO_ARG_CMDARG

#define SDIO_CMD_CMDINDEX

#define SDIO_CMD_WAITRESP

#define SDIO_CMD_WAITRESP_0

#define SDIO_CMD_WAITRESP_1

#define SDIO_CMD_WAITINT

#define SDIO_CMD_WAITPEND

#define SDIO_CMD_CPSMEN

#define SDIO_CMD_SDIOSUSPEND

#define SDIO_CMD_ENCMDCOMPL

#define SDIO_CMD_NIEN

#define SDIO_CMD_CEATACMD

#define SDIO_RESPCMD_RESPCMD

#define SDIO_RESP0_CARDSTATUS0

#define SDIO_RESP1_CARDSTATUS1

#define SDIO_RESP2_CARDSTATUS2

#define SDIO_RESP3_CARDSTATUS3

#define SDIO_RESP4_CARDSTATUS4

#define SDIO_DTIMER_DATATIME

#define SDIO_DLEN_DATALENGTH

#define SDIO_DCTRL_DTEN

#define SDIO_DCTRL_DTDIR

#define SDIO_DCTRL_DTMODE

#define SDIO_DCTRL_DMAEN

#define SDIO_DCTRL_DBLOCKSIZE

#define SDIO_DCTRL_DBLOCKSIZE_0

#define SDIO_DCTRL_DBLOCKSIZE_1

#define SDIO_DCTRL_DBLOCKSIZE_2

#define SDIO_DCTRL_DBLOCKSIZE_3

#define SDIO_DCTRL_RWSTART

#define SDIO_DCTRL_RWSTOP

#define SDIO_DCTRL_RWMOD

#define SDIO_DCTRL_SDIOEN

#define SDIO_DCOUNT_DATACOUNT

#define SDIO_STA_CCRCFAIL

#define SDIO_STA_DCRCFAIL

#define SDIO_STA_CTIMEOUT

#define SDIO_STA_DTIMEOUT

#define SDIO_STA_TXUNDERR

#define SDIO_STA_RXOVERR

#define SDIO_STA_CMDREND

#define SDIO_STA_CMDSENT

#define SDIO_STA_DATAEND

#define SDIO_STA_STBITERR

#define SDIO_STA_DBCKEND

#define SDIO_STA_CMDACT

#define SDIO_STA_TXACT

#define SDIO_STA_RXACT

#define SDIO_STA_TXFIFOHE

#define SDIO_STA_RXFIFOHF

#define SDIO_STA_TXFIFOF

#define SDIO_STA_RXFIFOF

#define SDIO_STA_TXFIFOE

#define SDIO_STA_RXFIFOE

#define SDIO_STA_TXDAVL

#define SDIO_STA_RXDAVL

#define SDIO_STA_SDIOIT

#define SDIO_STA_CEATAEND

#define SDIO_ICR_CCRCFAILC

#define SDIO_ICR_DCRCFAILC

#define SDIO_ICR_CTIMEOUTC

#define SDIO_ICR_DTIMEOUTC

#define SDIO_ICR_TXUNDERRC

#define SDIO_ICR_RXOVERRC

#define SDIO_ICR_CMDRENDC

#define SDIO_ICR_CMDSENTC

#define SDIO_ICR_DATAENDC

#define SDIO_ICR_STBITERRC

#define SDIO_ICR_DBCKENDC

#define SDIO_ICR_SDIOITC

#define SDIO_ICR_CEATAENDC

#define SDIO_MASK_CCRCFAILIE

#define SDIO_MASK_DCRCFAILIE

#define SDIO_MASK_CTIMEOUTIE

#define SDIO_MASK_DTIMEOUTIE

#define SDIO_MASK_TXUNDERRIE

#define SDIO_MASK_RXOVERRIE

#define SDIO_MASK_CMDRENDIE

#define SDIO_MASK_CMDSENTIE

#define SDIO_MASK_DATAENDIE

#define SDIO_MASK_STBITERRIE

#define SDIO_MASK_DBCKENDIE

#define SDIO_MASK_CMDACTIE

#define SDIO_MASK_TXACTIE

#define SDIO_MASK_RXACTIE

#define SDIO_MASK_TXFIFOHEIE

#define SDIO_MASK_RXFIFOHFIE

#define SDIO_MASK_TXFIFOFIE

#define SDIO_MASK_RXFIFOFIE

#define SDIO_MASK_TXFIFOEIE

#define SDIO_MASK_RXFIFOEIE

#define SDIO_MASK_TXDAVLIE

#define SDIO_MASK_RXDAVLIE

#define SDIO_MASK_SDIOITIE

#define SDIO_MASK_CEATAENDIE

#define SDIO_FIFOCNT_FIFOCOUNT

#define SDIO_FIFO_FIFODATA

#define SPI_CR1_CPHA

#define SPI_CR1_CPOL

#define SPI_CR1_MSTR

#define SPI_CR1_BR

#define SPI_CR1_BR_0

#define SPI_CR1_BR_1

#define SPI_CR1_BR_2

#define SPI_CR1_SPE

#define SPI_CR1_LSBFIRST

#define SPI_CR1_SSI

#define SPI_CR1_SSM

#define SPI_CR1_RXONLY

#define SPI_CR1_DFF

#define SPI_CR1_CRCNEXT

#define SPI_CR1_CRCEN

#define SPI_CR1_BIDIOE

#define SPI_CR1_BIDIMODE

#define SPI_CR2_RXDMAEN

#define SPI_CR2_TXDMAEN

#define SPI_CR2_SSOE

#define SPI_CR2_FRF

#define SPI_CR2_ERRIE

#define SPI_CR2_RXNEIE

#define SPI_CR2_TXEIE

#define SPI_SR_RXNE

#define SPI_SR_TXE

#define SPI_SR_CHSIDE

#define SPI_SR_UDR

#define SPI_SR_CRCERR

#define SPI_SR_MODF

#define SPI_SR_OVR

#define SPI_SR_BSY

#define SPI_SR_FRE

#define SPI_DR_DR

#define SPI_CRCPR_CRCPOLY

#define SPI_RXCRCR_RXCRC

#define SPI_TXCRCR_TXCRC

#define SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SMOD

#define SPI_I2SPR_I2SDIV

#define SPI_I2SPR_ODD

#define SPI_I2SPR_MCKOE

#define SYSCFG_MEMRMP_MEM_MODE

#define SYSCFG_MEMRMP_MEM_MODE_0

#define SYSCFG_MEMRMP_MEM_MODE_1

#define SYSCFG_MEMRMP_MEM_MODE_2

#define SYSCFG_PMC_ADCxDC2

#define SYSCFG_PMC_ADC1DC2

#define SYSCFG_PMC_ADC2DC2

#define SYSCFG_PMC_ADC3DC2

#define SYSCFG_EXTICR1_EXTI0

#define SYSCFG_EXTICR1_EXTI1

#define SYSCFG_EXTICR1_EXTI2

#define SYSCFG_EXTICR1_EXTI3

* @brief EXTI0 configuration

#define SYSCFG_EXTICR1_EXTI0_PA

#define SYSCFG_EXTICR1_EXTI0_PB

#define SYSCFG_EXTICR1_EXTI0_PC

#define SYSCFG_EXTICR1_EXTI0_PD

#define SYSCFG_EXTICR1_EXTI0_PE

#define SYSCFG_EXTICR1_EXTI0_PH

* @brief EXTI1 configuration

#define SYSCFG_EXTICR1_EXTI1_PA

#define SYSCFG_EXTICR1_EXTI1_PB

#define SYSCFG_EXTICR1_EXTI1_PC

#define SYSCFG_EXTICR1_EXTI1_PD

#define SYSCFG_EXTICR1_EXTI1_PE

#define SYSCFG_EXTICR1_EXTI1_PH

* @brief EXTI2 configuration

#define SYSCFG_EXTICR1_EXTI2_PA

#define SYSCFG_EXTICR1_EXTI2_PB

#define SYSCFG_EXTICR1_EXTI2_PC

#define SYSCFG_EXTICR1_EXTI2_PD

#define SYSCFG_EXTICR1_EXTI2_PE

#define SYSCFG_EXTICR1_EXTI2_PH

* @brief EXTI3 configuration

#define SYSCFG_EXTICR1_EXTI3_PA

#define SYSCFG_EXTICR1_EXTI3_PB

#define SYSCFG_EXTICR1_EXTI3_PC

#define SYSCFG_EXTICR1_EXTI3_PD

#define SYSCFG_EXTICR1_EXTI3_PE

#define SYSCFG_EXTICR1_EXTI3_PH

#define SYSCFG_EXTICR2_EXTI4

#define SYSCFG_EXTICR2_EXTI5

#define SYSCFG_EXTICR2_EXTI6

#define SYSCFG_EXTICR2_EXTI7

* @brief EXTI4 configuration

#define SYSCFG_EXTICR2_EXTI4_PA

#define SYSCFG_EXTICR2_EXTI4_PB

#define SYSCFG_EXTICR2_EXTI4_PC

#define SYSCFG_EXTICR2_EXTI4_PD

#define SYSCFG_EXTICR2_EXTI4_PE

#define SYSCFG_EXTICR2_EXTI4_PH

* @brief EXTI5 configuration

#define SYSCFG_EXTICR2_EXTI5_PA

#define SYSCFG_EXTICR2_EXTI5_PB

#define SYSCFG_EXTICR2_EXTI5_PC

#define SYSCFG_EXTICR2_EXTI5_PD

#define SYSCFG_EXTICR2_EXTI5_PE

#define SYSCFG_EXTICR2_EXTI5_PH

* @brief EXTI6 configuration

#define SYSCFG_EXTICR2_EXTI6_PA

#define SYSCFG_EXTICR2_EXTI6_PB

#define SYSCFG_EXTICR2_EXTI6_PC

#define SYSCFG_EXTICR2_EXTI6_PD

#define SYSCFG_EXTICR2_EXTI6_PE

#define SYSCFG_EXTICR2_EXTI6_PH

* @brief EXTI7 configuration

#define SYSCFG_EXTICR2_EXTI7_PA

#define SYSCFG_EXTICR2_EXTI7_PB

#define SYSCFG_EXTICR2_EXTI7_PC

#define SYSCFG_EXTICR2_EXTI7_PD

#define SYSCFG_EXTICR2_EXTI7_PE

#define SYSCFG_EXTICR2_EXTI7_PH

#define SYSCFG_EXTICR3_EXTI8

#define SYSCFG_EXTICR3_EXTI9

#define SYSCFG_EXTICR3_EXTI10

#define SYSCFG_EXTICR3_EXTI11

* @brief EXTI8 configuration

#define SYSCFG_EXTICR3_EXTI8_PA

#define SYSCFG_EXTICR3_EXTI8_PB

#define SYSCFG_EXTICR3_EXTI8_PC

#define SYSCFG_EXTICR3_EXTI8_PD

#define SYSCFG_EXTICR3_EXTI8_PE

#define SYSCFG_EXTICR3_EXTI8_PH

* @brief EXTI9 configuration

#define SYSCFG_EXTICR3_EXTI9_PA

#define SYSCFG_EXTICR3_EXTI9_PB

#define SYSCFG_EXTICR3_EXTI9_PC

#define SYSCFG_EXTICR3_EXTI9_PD

#define SYSCFG_EXTICR3_EXTI9_PE

#define SYSCFG_EXTICR3_EXTI9_PH

* @brief EXTI10 configuration

#define SYSCFG_EXTICR3_EXTI10_PA

#define SYSCFG_EXTICR3_EXTI10_PB

#define SYSCFG_EXTICR3_EXTI10_PC

#define SYSCFG_EXTICR3_EXTI10_PD

#define SYSCFG_EXTICR3_EXTI10_PE

#define SYSCFG_EXTICR3_EXTI10_PH

* @brief EXTI11 configuration

#define SYSCFG_EXTICR3_EXTI11_PA

#define SYSCFG_EXTICR3_EXTI11_PB

#define SYSCFG_EXTICR3_EXTI11_PC

#define SYSCFG_EXTICR3_EXTI11_PD

#define SYSCFG_EXTICR3_EXTI11_PE

#define SYSCFG_EXTICR3_EXTI11_PH

#define SYSCFG_EXTICR4_EXTI12

#define SYSCFG_EXTICR4_EXTI13

#define SYSCFG_EXTICR4_EXTI14

#define SYSCFG_EXTICR4_EXTI15

* @brief EXTI12 configuration

#define SYSCFG_EXTICR4_EXTI12_PA

#define SYSCFG_EXTICR4_EXTI12_PB

#define SYSCFG_EXTICR4_EXTI12_PC

#define SYSCFG_EXTICR4_EXTI12_PD

#define SYSCFG_EXTICR4_EXTI12_PE

#define SYSCFG_EXTICR4_EXTI12_PH

* @brief EXTI13 configuration

#define SYSCFG_EXTICR4_EXTI13_PA

#define SYSCFG_EXTICR4_EXTI13_PB

#define SYSCFG_EXTICR4_EXTI13_PC

#define SYSCFG_EXTICR4_EXTI13_PD

#define SYSCFG_EXTICR4_EXTI13_PE

#define SYSCFG_EXTICR4_EXTI13_PH

* @brief EXTI14 configuration

#define SYSCFG_EXTICR4_EXTI14_PA

#define SYSCFG_EXTICR4_EXTI14_PB

#define SYSCFG_EXTICR4_EXTI14_PC

#define SYSCFG_EXTICR4_EXTI14_PD

#define SYSCFG_EXTICR4_EXTI14_PE

#define SYSCFG_EXTICR4_EXTI14_PH

* @brief EXTI15 configuration

#define SYSCFG_EXTICR4_EXTI15_PA

#define SYSCFG_EXTICR4_EXTI15_PB

#define SYSCFG_EXTICR4_EXTI15_PC

#define SYSCFG_EXTICR4_EXTI15_PD

#define SYSCFG_EXTICR4_EXTI15_PE

#define SYSCFG_EXTICR4_EXTI15_PH

#define SYSCFG_CMPCR_CMP_PD

#define SYSCFG_CMPCR_READY

#define TIM_CR1_CEN

#define TIM_CR1_UDIS

#define TIM_CR1_URS

#define TIM_CR1_OPM

#define TIM_CR1_DIR

#define TIM_CR1_CMS

#define TIM_CR1_CMS_0

#define TIM_CR1_CMS_1

#define TIM_CR1_ARPE

#define TIM_CR1_CKD

#define TIM_CR1_CKD_0

#define TIM_CR1_CKD_1

#define TIM_CR2_CCPC

#define TIM_CR2_CCUS

#define TIM_CR2_CCDS

#define TIM_CR2_MMS

#define TIM_CR2_MMS_0

#define TIM_CR2_MMS_1

#define TIM_CR2_MMS_2

#define TIM_CR2_TI1S

#define TIM_CR2_OIS1

#define TIM_CR2_OIS1N

#define TIM_CR2_OIS2

#define TIM_CR2_OIS2N

#define TIM_CR2_OIS3

#define TIM_CR2_OIS3N

#define TIM_CR2_OIS4

#define TIM_SMCR_SMS

#define TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_2

#define TIM_SMCR_TS

#define TIM_SMCR_TS_0

#define TIM_SMCR_TS_1

#define TIM_SMCR_TS_2

#define TIM_SMCR_MSM

#define TIM_SMCR_ETF

#define TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_3

#define TIM_SMCR_ETPS

#define TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_1

#define TIM_SMCR_ECE

#define TIM_SMCR_ETP

#define TIM_DIER_UIE

#define TIM_DIER_CC1IE

#define TIM_DIER_CC2IE

#define TIM_DIER_CC3IE

#define TIM_DIER_CC4IE

#define TIM_DIER_COMIE

#define TIM_DIER_TIE

#define TIM_DIER_BIE

#define TIM_DIER_UDE

#define TIM_DIER_CC1DE

#define TIM_DIER_CC2DE

#define TIM_DIER_CC3DE

#define TIM_DIER_CC4DE

#define TIM_DIER_COMDE

#define TIM_DIER_TDE

#define TIM_SR_UIF

#define TIM_SR_CC1IF

#define TIM_SR_CC2IF

#define TIM_SR_CC3IF

#define TIM_SR_CC4IF

#define TIM_SR_COMIF

#define TIM_SR_TIF

#define TIM_SR_BIF

#define TIM_SR_CC1OF

#define TIM_SR_CC2OF

#define TIM_SR_CC3OF

#define TIM_SR_CC4OF

#define TIM_EGR_UG

#define TIM_EGR_CC1G

#define TIM_EGR_CC2G

#define TIM_EGR_CC3G

#define TIM_EGR_CC4G

#define TIM_EGR_COMG

#define TIM_EGR_TG

#define TIM_EGR_BG

#define TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_1

#define TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1CE

#define TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_1

#define TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2CE

#define TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_3

#define TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_1

#define TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3CE

#define TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_1

#define TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4CE

#define TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_3

#define TIM_CCER_CC1E

#define TIM_CCER_CC1P

#define TIM_CCER_CC1NE

#define TIM_CCER_CC1NP

#define TIM_CCER_CC2E

#define TIM_CCER_CC2P

#define TIM_CCER_CC2NE

#define TIM_CCER_CC2NP

#define TIM_CCER_CC3E

#define TIM_CCER_CC3P

#define TIM_CCER_CC3NE

#define TIM_CCER_CC3NP

#define TIM_CCER_CC4E

#define TIM_CCER_CC4P

#define TIM_CCER_CC4NP

#define TIM_CNT_CNT

#define TIM_PSC_PSC

#define TIM_ARR_ARR

#define TIM_RCR_REP

#define TIM_CCR1_CCR1

#define TIM_CCR2_CCR2

#define TIM_CCR3_CCR3

#define TIM_CCR4_CCR4

#define TIM_BDTR_DTG

#define TIM_BDTR_DTG_0

#define TIM_BDTR_DTG_1

#define TIM_BDTR_DTG_2

#define TIM_BDTR_DTG_3

#define TIM_BDTR_DTG_4

#define TIM_BDTR_DTG_5

#define TIM_BDTR_DTG_6

#define TIM_BDTR_DTG_7

#define TIM_BDTR_LOCK

#define TIM_BDTR_LOCK_0

#define TIM_BDTR_LOCK_1

#define TIM_BDTR_OSSI

#define TIM_BDTR_OSSR

#define TIM_BDTR_BKE

#define TIM_BDTR_BKP

#define TIM_BDTR_AOE

#define TIM_BDTR_MOE

#define TIM_DCR_DBA

#define TIM_DCR_DBA_0

#define TIM_DCR_DBA_1

#define TIM_DCR_DBA_2

#define TIM_DCR_DBA_3

#define TIM_DCR_DBA_4

#define TIM_DCR_DBL

#define TIM_DCR_DBL_0

#define TIM_DCR_DBL_1

#define TIM_DCR_DBL_2

#define TIM_DCR_DBL_3

#define TIM_DCR_DBL_4

#define TIM_DMAR_DMAB

#define TIM_OR_TI4_RMP

#define TIM_OR_TI4_RMP_0

#define TIM_OR_TI4_RMP_1

#define TIM_OR_ITR1_RMP

#define TIM_OR_ITR1_RMP_0

#define TIM_OR_ITR1_RMP_1

#define USART_SR_PE

#define USART_SR_FE

#define USART_SR_NE

#define USART_SR_ORE

#define USART_SR_IDLE

#define USART_SR_RXNE

#define USART_SR_TC

#define USART_SR_TXE

#define USART_SR_LBD

#define USART_SR_CTS

#define USART_DR_DR

#define USART_BRR_DIV_Fraction

#define USART_BRR_DIV_Mantissa

#define USART_CR1_SBK

#define USART_CR1_RWU

#define USART_CR1_RE

#define USART_CR1_TE

#define USART_CR1_IDLEIE

#define USART_CR1_RXNEIE

#define USART_CR1_TCIE

#define USART_CR1_TXEIE

#define USART_CR1_PEIE

#define USART_CR1_PS

#define USART_CR1_PCE

#define USART_CR1_WAKE

#define USART_CR1_M

#define USART_CR1_UE

#define USART_CR1_OVER8

#define USART_CR2_ADD

#define USART_CR2_LBDL

#define USART_CR2_LBDIE

#define USART_CR2_LBCL

#define USART_CR2_CPHA

#define USART_CR2_CPOL

#define USART_CR2_CLKEN

#define USART_CR2_STOP

#define USART_CR2_STOP_0

#define USART_CR2_STOP_1

#define USART_CR2_LINEN

#define USART_CR3_EIE

#define USART_CR3_IREN

#define USART_CR3_IRLP

#define USART_CR3_HDSEL

#define USART_CR3_NACK

#define USART_CR3_SCEN

#define USART_CR3_DMAR

#define USART_CR3_DMAT

#define USART_CR3_RTSE

#define USART_CR3_CTSE

#define USART_CR3_CTSIE

#define USART_CR3_ONEBIT

#define USART_GTPR_PSC

#define USART_GTPR_PSC_0

#define USART_GTPR_PSC_1

#define USART_GTPR_PSC_2

#define USART_GTPR_PSC_3

#define USART_GTPR_PSC_4

#define USART_GTPR_PSC_5

#define USART_GTPR_PSC_6

#define USART_GTPR_PSC_7

#define USART_GTPR_GT

#define WWDG_CR_T

#define WWDG_CR_T0

#define WWDG_CR_T1

#define WWDG_CR_T2

#define WWDG_CR_T3

#define WWDG_CR_T4

#define WWDG_CR_T5

#define WWDG_CR_T6

#define WWDG_CR_WDGA

#define WWDG_CFR_W

#define WWDG_CFR_W0

#define WWDG_CFR_W1

#define WWDG_CFR_W2

#define WWDG_CFR_W3

#define WWDG_CFR_W4

#define WWDG_CFR_W5

#define WWDG_CFR_W6

#define WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB0

#define WWDG_CFR_WDGTB1

#define WWDG_CFR_EWI

#define WWDG_SR_EWIF

#define DBGMCU_IDCODE_DEV_ID

#define DBGMCU_IDCODE_REV_ID

#define DBGMCU_CR_DBG_SLEEP

#define DBGMCU_CR_DBG_STOP

#define DBGMCU_CR_DBG_STANDBY

#define DBGMCU_CR_TRACE_IOEN

#define DBGMCU_CR_TRACE_MODE

#define DBGMCU_CR_TRACE_MODE_0

#define DBGMCU_CR_TRACE_MODE_1

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP

#define DBGMCU_APB1_FZ_DBG_TIM12_STOP

#define DBGMCU_APB1_FZ_DBG_TIM13_STOP

#define DBGMCU_APB1_FZ_DBG_TIM14_STOP

#define DBGMCU_APB1_FZ_DBG_RTC_STOP

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP

#define DBGMCU_APB1_FZ_DBG_CAN2_STOP

#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP

#define DBGMCU_APB2_FZ_DBG_TIM1_STOP

#define DBGMCU_APB2_FZ_DBG_TIM8_STOP

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP

#define USB_OTG_GOTGCTL_SRQSCS

#define USB_OTG_GOTGCTL_SRQ

#define USB_OTG_GOTGCTL_HNGSCS

#define USB_OTG_GOTGCTL_HNPRQ

#define USB_OTG_GOTGCTL_HSHNPEN

#define USB_OTG_GOTGCTL_DHNPEN

#define USB_OTG_GOTGCTL_CIDSTS

#define USB_OTG_GOTGCTL_DBCT

#define USB_OTG_GOTGCTL_ASVLD

#define USB_OTG_GOTGCTL_BSVLD

#define USB_OTG_HCFG_FSLSPCS

#define USB_OTG_HCFG_FSLSPCS_0

#define USB_OTG_HCFG_FSLSPCS_1

#define USB_OTG_HCFG_FSLSS

#define USB_OTG_DCFG_DSPD

#define USB_OTG_DCFG_DSPD_0

#define USB_OTG_DCFG_DSPD_1

#define USB_OTG_DCFG_NZLSOHSK

#define USB_OTG_DCFG_DAD

#define USB_OTG_DCFG_DAD_0

#define USB_OTG_DCFG_DAD_1

#define USB_OTG_DCFG_DAD_2

#define USB_OTG_DCFG_DAD_3

#define USB_OTG_DCFG_DAD_4

#define USB_OTG_DCFG_DAD_5

#define USB_OTG_DCFG_DAD_6

#define USB_OTG_DCFG_PFIVL

#define USB_OTG_DCFG_PFIVL_0

#define USB_OTG_DCFG_PFIVL_1

#define USB_OTG_DCFG_PERSCHIVL

#define USB_OTG_DCFG_PERSCHIVL_0

#define USB_OTG_DCFG_PERSCHIVL_1

#define USB_OTG_PCGCR_STPPCLK

#define USB_OTG_PCGCR_GATEHCLK

#define USB_OTG_PCGCR_PHYSUSP

#define USB_OTG_GOTGINT_SEDET

#define USB_OTG_GOTGINT_SRSSCHG

#define USB_OTG_GOTGINT_HNSSCHG

#define USB_OTG_GOTGINT_HNGDET

#define USB_OTG_GOTGINT_ADTOCHG

#define USB_OTG_GOTGINT_DBCDNE

#define USB_OTG_DCTL_RWUSIG

#define USB_OTG_DCTL_SDIS

#define USB_OTG_DCTL_GINSTS

#define USB_OTG_DCTL_GONSTS

#define USB_OTG_DCTL_TCTL

#define USB_OTG_DCTL_TCTL_0

#define USB_OTG_DCTL_TCTL_1

#define USB_OTG_DCTL_TCTL_2

#define USB_OTG_DCTL_SGINAK

#define USB_OTG_DCTL_CGINAK

#define USB_OTG_DCTL_SGONAK

#define USB_OTG_DCTL_CGONAK

#define USB_OTG_DCTL_POPRGDNE

#define USB_OTG_HFIR_FRIVL

#define USB_OTG_HFNUM_FRNUM

#define USB_OTG_HFNUM_FTREM

#define USB_OTG_DSTS_SUSPSTS

#define USB_OTG_DSTS_ENUMSPD

#define USB_OTG_DSTS_ENUMSPD_0

#define USB_OTG_DSTS_ENUMSPD_1

#define USB_OTG_DSTS_EERR

#define USB_OTG_DSTS_FNSOF

#define USB_OTG_GAHBCFG_GINT

#define USB_OTG_GAHBCFG_HBSTLEN

#define USB_OTG_GAHBCFG_HBSTLEN_0

#define USB_OTG_GAHBCFG_HBSTLEN_1

#define USB_OTG_GAHBCFG_HBSTLEN_2

#define USB_OTG_GAHBCFG_HBSTLEN_3

#define USB_OTG_GAHBCFG_DMAEN

#define USB_OTG_GAHBCFG_TXFELVL

#define USB_OTG_GAHBCFG_PTXFELVL

#define USB_OTG_GUSBCFG_TOCAL

#define USB_OTG_GUSBCFG_TOCAL_0

#define USB_OTG_GUSBCFG_TOCAL_1

#define USB_OTG_GUSBCFG_TOCAL_2

#define USB_OTG_GUSBCFG_PHYSEL

#define USB_OTG_GUSBCFG_SRPCAP

#define USB_OTG_GUSBCFG_HNPCAP

#define USB_OTG_GUSBCFG_TRDT

#define USB_OTG_GUSBCFG_TRDT_0

#define USB_OTG_GUSBCFG_TRDT_1

#define USB_OTG_GUSBCFG_TRDT_2

#define USB_OTG_GUSBCFG_TRDT_3

#define USB_OTG_GUSBCFG_PHYLPCS

#define USB_OTG_GUSBCFG_ULPIFSLS

#define USB_OTG_GUSBCFG_ULPIAR

#define USB_OTG_GUSBCFG_ULPICSM

#define USB_OTG_GUSBCFG_ULPIEVBUSD

#define USB_OTG_GUSBCFG_ULPIEVBUSI

#define USB_OTG_GUSBCFG_TSDPS

#define USB_OTG_GUSBCFG_PCCI

#define USB_OTG_GUSBCFG_PTCI

#define USB_OTG_GUSBCFG_ULPIIPD

#define USB_OTG_GUSBCFG_FHMOD

#define USB_OTG_GUSBCFG_FDMOD

#define USB_OTG_GUSBCFG_CTXPKT

#define USB_OTG_GRSTCTL_CSRST

#define USB_OTG_GRSTCTL_HSRST

#define USB_OTG_GRSTCTL_FCRST

#define USB_OTG_GRSTCTL_RXFFLSH

#define USB_OTG_GRSTCTL_TXFFLSH

#define USB_OTG_GRSTCTL_TXFNUM

#define USB_OTG_GRSTCTL_TXFNUM_0

#define USB_OTG_GRSTCTL_TXFNUM_1

#define USB_OTG_GRSTCTL_TXFNUM_2

#define USB_OTG_GRSTCTL_TXFNUM_3

#define USB_OTG_GRSTCTL_TXFNUM_4

#define USB_OTG_GRSTCTL_DMAREQ

#define USB_OTG_GRSTCTL_AHBIDL

#define USB_OTG_DIEPMSK_XFRCM

#define USB_OTG_DIEPMSK_EPDM

#define USB_OTG_DIEPMSK_TOM

#define USB_OTG_DIEPMSK_ITTXFEMSK

#define USB_OTG_DIEPMSK_INEPNMM

#define USB_OTG_DIEPMSK_INEPNEM

#define USB_OTG_DIEPMSK_TXFURM

#define USB_OTG_DIEPMSK_BIM

#define USB_OTG_HPTXSTS_PTXFSAVL

#define USB_OTG_HPTXSTS_PTXQSAV

#define USB_OTG_HPTXSTS_PTXQSAV_0

#define USB_OTG_HPTXSTS_PTXQSAV_1

#define USB_OTG_HPTXSTS_PTXQSAV_2

#define USB_OTG_HPTXSTS_PTXQSAV_3

#define USB_OTG_HPTXSTS_PTXQSAV_4

#define USB_OTG_HPTXSTS_PTXQSAV_5

#define USB_OTG_HPTXSTS_PTXQSAV_6

#define USB_OTG_HPTXSTS_PTXQSAV_7

#define USB_OTG_HPTXSTS_PTXQTOP

#define USB_OTG_HPTXSTS_PTXQTOP_0

#define USB_OTG_HPTXSTS_PTXQTOP_1

#define USB_OTG_HPTXSTS_PTXQTOP_2

#define USB_OTG_HPTXSTS_PTXQTOP_3

#define USB_OTG_HPTXSTS_PTXQTOP_4

#define USB_OTG_HPTXSTS_PTXQTOP_5

#define USB_OTG_HPTXSTS_PTXQTOP_6

#define USB_OTG_HPTXSTS_PTXQTOP_7

#define USB_OTG_HAINT_HAINT

#define USB_OTG_DOEPMSK_XFRCM

#define USB_OTG_DOEPMSK_EPDM

#define USB_OTG_DOEPMSK_STUPM

#define USB_OTG_DOEPMSK_OTEPDM

#define USB_OTG_DOEPMSK_B2BSTUP

#define USB_OTG_DOEPMSK_OPEM

#define USB_OTG_DOEPMSK_BOIM

#define USB_OTG_GINTSTS_CMOD

#define USB_OTG_GINTSTS_MMIS

#define USB_OTG_GINTSTS_OTGINT

#define USB_OTG_GINTSTS_SOF

#define USB_OTG_GINTSTS_RXFLVL

#define USB_OTG_GINTSTS_NPTXFE

#define USB_OTG_GINTSTS_GINAKEFF

#define USB_OTG_GINTSTS_BOUTNAKEFF

#define USB_OTG_GINTSTS_ESUSP

#define USB_OTG_GINTSTS_USBSUSP

#define USB_OTG_GINTSTS_USBRST

#define USB_OTG_GINTSTS_ENUMDNE

#define USB_OTG_GINTSTS_ISOODRP

#define USB_OTG_GINTSTS_EOPF

#define USB_OTG_GINTSTS_IEPINT

#define USB_OTG_GINTSTS_OEPINT

#define USB_OTG_GINTSTS_IISOIXFR

#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT

#define USB_OTG_GINTSTS_DATAFSUSP

#define USB_OTG_GINTSTS_HPRTINT

#define USB_OTG_GINTSTS_HCINT

#define USB_OTG_GINTSTS_PTXFE

#define USB_OTG_GINTSTS_CIDSCHG

#define USB_OTG_GINTSTS_DISCINT

#define USB_OTG_GINTSTS_SRQINT

#define USB_OTG_GINTSTS_WKUINT

#define USB_OTG_GINTMSK_MMISM

#define USB_OTG_GINTMSK_OTGINT

#define USB_OTG_GINTMSK_SOFM

#define USB_OTG_GINTMSK_RXFLVLM

#define USB_OTG_GINTMSK_NPTXFEM

#define USB_OTG_GINTMSK_GINAKEFFM

#define USB_OTG_GINTMSK_GONAKEFFM

#define USB_OTG_GINTMSK_ESUSPM

#define USB_OTG_GINTMSK_USBSUSPM

#define USB_OTG_GINTMSK_USBRST

#define USB_OTG_GINTMSK_ENUMDNEM

#define USB_OTG_GINTMSK_ISOODRPM

#define USB_OTG_GINTMSK_EOPFM

#define USB_OTG_GINTMSK_EPMISM

#define USB_OTG_GINTMSK_IEPINT

#define USB_OTG_GINTMSK_OEPINT

#define USB_OTG_GINTMSK_IISOIXFRM

#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM

#define USB_OTG_GINTMSK_FSUSPM

#define USB_OTG_GINTMSK_PRTIM

#define USB_OTG_GINTMSK_HCIM

#define USB_OTG_GINTMSK_PTXFEM

#define USB_OTG_GINTMSK_CIDSCHGM

#define USB_OTG_GINTMSK_DISCINT

#define USB_OTG_GINTMSK_SRQIM

#define USB_OTG_GINTMSK_WUIM

#define USB_OTG_DAINT_IEPINT

#define USB_OTG_DAINT_OEPINT

#define USB_OTG_HAINTMSK_HAINTM

#define USB_OTG_GRXSTSP_EPNUM

#define USB_OTG_GRXSTSP_BCNT

#define USB_OTG_GRXSTSP_DPID

#define USB_OTG_GRXSTSP_PKTSTS

#define USB_OTG_DAINTMSK_IEPM

#define USB_OTG_DAINTMSK_OEPM

#define USB_OTG_CHNUM

#define USB_OTG_CHNUM_0

#define USB_OTG_CHNUM_1

#define USB_OTG_CHNUM_2

#define USB_OTG_CHNUM_3

#define USB_OTG_BCNT

#define USB_OTG_DPID

#define USB_OTG_DPID_0

#define USB_OTG_DPID_1

#define USB_OTG_PKTSTS

#define USB_OTG_PKTSTS_0

#define USB_OTG_PKTSTS_1

#define USB_OTG_PKTSTS_2

#define USB_OTG_PKTSTS_3

#define USB_OTG_EPNUM

#define USB_OTG_EPNUM_0

#define USB_OTG_EPNUM_1

#define USB_OTG_EPNUM_2

#define USB_OTG_EPNUM_3

#define USB_OTG_FRMNUM

#define USB_OTG_FRMNUM_0

#define USB_OTG_FRMNUM_1

#define USB_OTG_FRMNUM_2

#define USB_OTG_FRMNUM_3

#define USB_OTG_CHNUM

#define USB_OTG_CHNUM_0

#define USB_OTG_CHNUM_1

#define USB_OTG_CHNUM_2

#define USB_OTG_CHNUM_3

#define USB_OTG_BCNT

#define USB_OTG_DPID

#define USB_OTG_DPID_0

#define USB_OTG_DPID_1

#define USB_OTG_PKTSTS

#define USB_OTG_PKTSTS_0

#define USB_OTG_PKTSTS_1

#define USB_OTG_PKTSTS_2

#define USB_OTG_PKTSTS_3

#define USB_OTG_EPNUM

#define USB_OTG_EPNUM_0

#define USB_OTG_EPNUM_1

#define USB_OTG_EPNUM_2

#define USB_OTG_EPNUM_3

#define USB_OTG_FRMNUM

#define USB_OTG_FRMNUM_0

#define USB_OTG_FRMNUM_1

#define USB_OTG_FRMNUM_2

#define USB_OTG_FRMNUM_3

#define USB_OTG_GRXFSIZ_RXFD

#define USB_OTG_DVBUSDIS_VBUSDT

#define USB_OTG_NPTXFSA

#define USB_OTG_NPTXFD

#define USB_OTG_TX0FSA

#define USB_OTG_TX0FD

#define USB_OTG_DVBUSPULSE_DVBUSP

#define USB_OTG_GNPTXSTS_NPTXFSAV

#define USB_OTG_GNPTXSTS_NPTQXSAV

#define USB_OTG_GNPTXSTS_NPTQXSAV_0

#define USB_OTG_GNPTXSTS_NPTQXSAV_1

#define USB_OTG_GNPTXSTS_NPTQXSAV_2

#define USB_OTG_GNPTXSTS_NPTQXSAV_3

#define USB_OTG_GNPTXSTS_NPTQXSAV_4

#define USB_OTG_GNPTXSTS_NPTQXSAV_5

#define USB_OTG_GNPTXSTS_NPTQXSAV_6

#define USB_OTG_GNPTXSTS_NPTQXSAV_7

#define USB_OTG_GNPTXSTS_NPTXQTOP

#define USB_OTG_GNPTXSTS_NPTXQTOP_0

#define USB_OTG_GNPTXSTS_NPTXQTOP_1

#define USB_OTG_GNPTXSTS_NPTXQTOP_2

#define USB_OTG_GNPTXSTS_NPTXQTOP_3

#define USB_OTG_GNPTXSTS_NPTXQTOP_4

#define USB_OTG_GNPTXSTS_NPTXQTOP_5

#define USB_OTG_GNPTXSTS_NPTXQTOP_6

#define USB_OTG_DTHRCTL_NONISOTHREN

#define USB_OTG_DTHRCTL_ISOTHREN

#define USB_OTG_DTHRCTL_TXTHRLEN

#define USB_OTG_DTHRCTL_TXTHRLEN_0

#define USB_OTG_DTHRCTL_TXTHRLEN_1

#define USB_OTG_DTHRCTL_TXTHRLEN_2

#define USB_OTG_DTHRCTL_TXTHRLEN_3

#define USB_OTG_DTHRCTL_TXTHRLEN_4

#define USB_OTG_DTHRCTL_TXTHRLEN_5

#define USB_OTG_DTHRCTL_TXTHRLEN_6

#define USB_OTG_DTHRCTL_TXTHRLEN_7

#define USB_OTG_DTHRCTL_TXTHRLEN_8

#define USB_OTG_DTHRCTL_RXTHREN

#define USB_OTG_DTHRCTL_RXTHRLEN

#define USB_OTG_DTHRCTL_RXTHRLEN_0

#define USB_OTG_DTHRCTL_RXTHRLEN_1

#define USB_OTG_DTHRCTL_RXTHRLEN_2

#define USB_OTG_DTHRCTL_RXTHRLEN_3

#define USB_OTG_DTHRCTL_RXTHRLEN_4

#define USB_OTG_DTHRCTL_RXTHRLEN_5

#define USB_OTG_DTHRCTL_RXTHRLEN_6

#define USB_OTG_DTHRCTL_RXTHRLEN_7

#define USB_OTG_DTHRCTL_RXTHRLEN_8

#define USB_OTG_DTHRCTL_ARPEN

#define USB_OTG_DIEPEMPMSK_INEPTXFEM

#define USB_OTG_DEACHINT_IEP1INT

#define USB_OTG_DEACHINT_OEP1INT

#define USB_OTG_GCCFG_PWRDWN

#define USB_OTG_GCCFG_I2CPADEN

#define USB_OTG_GCCFG_VBUSASEN

#define USB_OTG_GCCFG_VBUSBSEN

#define USB_OTG_GCCFG_SOFOUTEN

#define USB_OTG_GCCFG_NOVBUSSENS

#define USB_OTG_DEACHINTMSK_IEP1INTM

#define USB_OTG_DEACHINTMSK_OEP1INTM

#define USB_OTG_CID_PRODUCT_ID

#define USB_OTG_DIEPEACHMSK1_XFRCM

#define USB_OTG_DIEPEACHMSK1_EPDM

#define USB_OTG_DIEPEACHMSK1_TOM

#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK

#define USB_OTG_DIEPEACHMSK1_INEPNMM

#define USB_OTG_DIEPEACHMSK1_INEPNEM

#define USB_OTG_DIEPEACHMSK1_TXFURM

#define USB_OTG_DIEPEACHMSK1_BIM

#define USB_OTG_DIEPEACHMSK1_NAKM

#define USB_OTG_HPRT_PCSTS

#define USB_OTG_HPRT_PCDET

#define USB_OTG_HPRT_PENA

#define USB_OTG_HPRT_PENCHNG

#define USB_OTG_HPRT_POCA

#define USB_OTG_HPRT_POCCHNG

#define USB_OTG_HPRT_PRES

#define USB_OTG_HPRT_PSUSP

#define USB_OTG_HPRT_PRST

#define USB_OTG_HPRT_PLSTS

#define USB_OTG_HPRT_PLSTS_0

#define USB_OTG_HPRT_PLSTS_1

#define USB_OTG_HPRT_PPWR

#define USB_OTG_HPRT_PTCTL

#define USB_OTG_HPRT_PTCTL_0

#define USB_OTG_HPRT_PTCTL_1

#define USB_OTG_HPRT_PTCTL_2

#define USB_OTG_HPRT_PTCTL_3

#define USB_OTG_HPRT_PSPD

#define USB_OTG_HPRT_PSPD_0

#define USB_OTG_HPRT_PSPD_1

#define USB_OTG_DOEPEACHMSK1_XFRCM

#define USB_OTG_DOEPEACHMSK1_EPDM

#define USB_OTG_DOEPEACHMSK1_TOM

#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK

#define USB_OTG_DOEPEACHMSK1_INEPNMM

#define USB_OTG_DOEPEACHMSK1_INEPNEM

#define USB_OTG_DOEPEACHMSK1_TXFURM

#define USB_OTG_DOEPEACHMSK1_BIM

#define USB_OTG_DOEPEACHMSK1_BERRM

#define USB_OTG_DOEPEACHMSK1_NAKM

#define USB_OTG_DOEPEACHMSK1_NYETM

#define USB_OTG_HPTXFSIZ_PTXSA

#define USB_OTG_HPTXFSIZ_PTXFD

#define USB_OTG_DIEPCTL_MPSIZ

#define USB_OTG_DIEPCTL_USBAEP

#define USB_OTG_DIEPCTL_EONUM_DPID

#define USB_OTG_DIEPCTL_NAKSTS

#define USB_OTG_DIEPCTL_EPTYP

#define USB_OTG_DIEPCTL_EPTYP_0

#define USB_OTG_DIEPCTL_EPTYP_1

#define USB_OTG_DIEPCTL_STALL

#define USB_OTG_DIEPCTL_TXFNUM

#define USB_OTG_DIEPCTL_TXFNUM_0

#define USB_OTG_DIEPCTL_TXFNUM_1

#define USB_OTG_DIEPCTL_TXFNUM_2

#define USB_OTG_DIEPCTL_TXFNUM_3

#define USB_OTG_DIEPCTL_CNAK

#define USB_OTG_DIEPCTL_SNAK

#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM

#define USB_OTG_DIEPCTL_SODDFRM

#define USB_OTG_DIEPCTL_EPDIS

#define USB_OTG_DIEPCTL_EPENA

#define USB_OTG_HCCHAR_MPSIZ

#define USB_OTG_HCCHAR_EPNUM

#define USB_OTG_HCCHAR_EPNUM_0

#define USB_OTG_HCCHAR_EPNUM_1

#define USB_OTG_HCCHAR_EPNUM_2

#define USB_OTG_HCCHAR_EPNUM_3

#define USB_OTG_HCCHAR_EPDIR

#define USB_OTG_HCCHAR_LSDEV

#define USB_OTG_HCCHAR_EPTYP

#define USB_OTG_HCCHAR_EPTYP_0

#define USB_OTG_HCCHAR_EPTYP_1

#define USB_OTG_HCCHAR_MC

#define USB_OTG_HCCHAR_MC_0

#define USB_OTG_HCCHAR_MC_1

#define USB_OTG_HCCHAR_DAD

#define USB_OTG_HCCHAR_DAD_0

#define USB_OTG_HCCHAR_DAD_1

#define USB_OTG_HCCHAR_DAD_2

#define USB_OTG_HCCHAR_DAD_3

#define USB_OTG_HCCHAR_DAD_4

#define USB_OTG_HCCHAR_DAD_5

#define USB_OTG_HCCHAR_DAD_6

#define USB_OTG_HCCHAR_ODDFRM

#define USB_OTG_HCCHAR_CHDIS

#define USB_OTG_HCCHAR_CHENA

#define USB_OTG_HCSPLT_PRTADDR

#define USB_OTG_HCSPLT_PRTADDR_0

#define USB_OTG_HCSPLT_PRTADDR_1

#define USB_OTG_HCSPLT_PRTADDR_2

#define USB_OTG_HCSPLT_PRTADDR_3

#define USB_OTG_HCSPLT_PRTADDR_4

#define USB_OTG_HCSPLT_PRTADDR_5

#define USB_OTG_HCSPLT_PRTADDR_6

#define USB_OTG_HCSPLT_HUBADDR

#define USB_OTG_HCSPLT_HUBADDR_0

#define USB_OTG_HCSPLT_HUBADDR_1

#define USB_OTG_HCSPLT_HUBADDR_2

#define USB_OTG_HCSPLT_HUBADDR_3

#define USB_OTG_HCSPLT_HUBADDR_4

#define USB_OTG_HCSPLT_HUBADDR_5

#define USB_OTG_HCSPLT_HUBADDR_6

#define USB_OTG_HCSPLT_XACTPOS

#define USB_OTG_HCSPLT_XACTPOS_0

#define USB_OTG_HCSPLT_XACTPOS_1

#define USB_OTG_HCSPLT_COMPLSPLT

#define USB_OTG_HCSPLT_SPLITEN

#define USB_OTG_HCINT_XFRC

#define USB_OTG_HCINT_CHH

#define USB_OTG_HCINT_AHBERR

#define USB_OTG_HCINT_STALL

#define USB_OTG_HCINT_NAK

#define USB_OTG_HCINT_ACK

#define USB_OTG_HCINT_NYET

#define USB_OTG_HCINT_TXERR

#define USB_OTG_HCINT_BBERR

#define USB_OTG_HCINT_FRMOR

#define USB_OTG_HCINT_DTERR

#define USB_OTG_DIEPINT_XFRC

#define USB_OTG_DIEPINT_EPDISD

#define USB_OTG_DIEPINT_TOC

#define USB_OTG_DIEPINT_ITTXFE

#define USB_OTG_DIEPINT_INEPNE

#define USB_OTG_DIEPINT_TXFE

#define USB_OTG_DIEPINT_TXFIFOUDRN

#define USB_OTG_DIEPINT_BNA

#define USB_OTG_DIEPINT_PKTDRPSTS

#define USB_OTG_DIEPINT_BERR

#define USB_OTG_DIEPINT_NAK

#define USB_OTG_HCINTMSK_XFRCM

#define USB_OTG_HCINTMSK_CHHM

#define USB_OTG_HCINTMSK_AHBERR

#define USB_OTG_HCINTMSK_STALLM

#define USB_OTG_HCINTMSK_NAKM

#define USB_OTG_HCINTMSK_ACKM

#define USB_OTG_HCINTMSK_NYET

#define USB_OTG_HCINTMSK_TXERRM

#define USB_OTG_HCINTMSK_BBERRM

#define USB_OTG_HCINTMSK_FRMORM

#define USB_OTG_HCINTMSK_DTERRM

#define USB_OTG_DIEPTSIZ_XFRSIZ

#define USB_OTG_DIEPTSIZ_PKTCNT

#define USB_OTG_DIEPTSIZ_MULCNT

#define USB_OTG_HCTSIZ_XFRSIZ

#define USB_OTG_HCTSIZ_PKTCNT

#define USB_OTG_HCTSIZ_DOPING

#define USB_OTG_HCTSIZ_DPID

#define USB_OTG_HCTSIZ_DPID_0

#define USB_OTG_HCTSIZ_DPID_1

#define USB_OTG_DIEPDMA_DMAADDR

#define USB_OTG_HCDMA_DMAADDR

#define USB_OTG_DTXFSTS_INEPTFSAV

#define USB_OTG_DIEPTXF_INEPTXSA

#define USB_OTG_DIEPTXF_INEPTXFD

#define USB_OTG_DOEPCTL_MPSIZ

#define USB_OTG_DOEPCTL_USBAEP

#define USB_OTG_DOEPCTL_NAKSTS

#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM

#define USB_OTG_DOEPCTL_SODDFRM

#define USB_OTG_DOEPCTL_EPTYP

#define USB_OTG_DOEPCTL_EPTYP_0

#define USB_OTG_DOEPCTL_EPTYP_1

#define USB_OTG_DOEPCTL_SNPM

#define USB_OTG_DOEPCTL_STALL

#define USB_OTG_DOEPCTL_CNAK

#define USB_OTG_DOEPCTL_SNAK

#define USB_OTG_DOEPCTL_EPDIS

#define USB_OTG_DOEPCTL_EPENA

#define USB_OTG_DOEPINT_XFRC

#define USB_OTG_DOEPINT_EPDISD

#define USB_OTG_DOEPINT_STUP

#define USB_OTG_DOEPINT_OTEPDIS

#define USB_OTG_DOEPINT_B2BSTUP

#define USB_OTG_DOEPINT_NYET

#define USB_OTG_DOEPTSIZ_XFRSIZ

#define USB_OTG_DOEPTSIZ_PKTCNT

#define USB_OTG_DOEPTSIZ_STUPCNT

#define USB_OTG_DOEPTSIZ_STUPCNT_0

#define USB_OTG_DOEPTSIZ_STUPCNT_1

#define USB_OTG_PCGCCTL_STOPCLK

#define USB_OTG_PCGCCTL_GATECLK

#define USB_OTG_PCGCCTL_PHYSUSP

#define IS_ADC_ALL_INSTANCE( INSTANCE )

#define IS_CRC_ALL_INSTANCE( INSTANCE )

#define IS_DMA_STREAM_ALL_INSTANCE( INSTANCE )

#define IS_GPIO_ALL_INSTANCE( INSTANCE )

#define IS_I2C_ALL_INSTANCE( INSTANCE )

#define IS_I2S_INSTANCE( INSTANCE )

#define IS_I2S_INSTANCE_EXT( PERIPH )

#define IS_RNG_ALL_INSTANCE( INSTANCE )

#define IS_RTC_ALL_INSTANCE( INSTANCE )

#define IS_SPI_ALL_INSTANCE( INSTANCE )

#define IS_SPI_ALL_INSTANCE_EXT( INSTANCE )

#define IS_TIM_INSTANCE( INSTANCE )

#define IS_TIM_CC1_INSTANCE( INSTANCE )

#define IS_TIM_CC2_INSTANCE( INSTANCE )

#define IS_TIM_CC3_INSTANCE( INSTANCE )

#define IS_TIM_CC4_INSTANCE( INSTANCE )

#define IS_TIM_ADVANCED_INSTANCE( INSTANCE )

#define IS_TIM_XOR_INSTANCE( INSTANCE )

#define IS_TIM_DMA_INSTANCE( INSTANCE )

#define IS_TIM_DMA_CC_INSTANCE( INSTANCE )

#define IS_TIM_CCDMA_INSTANCE( INSTANCE )

#define IS_TIM_DMABURST_INSTANCE( INSTANCE )

#define IS_TIM_MASTER_INSTANCE( INSTANCE )

#define IS_TIM_SLAVE_INSTANCE( INSTANCE )

#define IS_TIM_32B_COUNTER_INSTANCE( INSTANCE )

#define IS_TIM_ETR_INSTANCE( INSTANCE )

#define IS_TIM_REMAP_INSTANCE( INSTANCE )

#define IS_TIM_CCX_INSTANCE( INSTANCE, CHANNEL )

#define IS_TIM_CCXN_INSTANCE( INSTANCE, CHANNEL )

#define IS_USART_INSTANCE( INSTANCE )

#define IS_UART_INSTANCE( INSTANCE )

#define IS_UART_HWFLOW_INSTANCE( INSTANCE )

#define IS_SMARTCARD_INSTANCE( INSTANCE )

#define IS_IRDA_INSTANCE( INSTANCE )

#define IS_IWDG_ALL_INSTANCE( INSTANCE )

#define IS_WWDG_ALL_INSTANCE( INSTANCE )

Typedef IRQn_Type

* @brief STM32F4XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section

typedef enum {...} IRQn_Type

`enum`
`{`
`NonMaskableInt_IRQn;`
`MemoryManagement_IRQn;`
`BusFault_IRQn;`
`UsageFault_IRQn;`
`SVCall_IRQn;`
`DebugMonitor_IRQn;`
`PendSV_IRQn;`
`SysTick_IRQn;`
`WWDG_IRQn;`
`PVD_IRQn;`
`TAMP_STAMP_IRQn;`
`RTC_WKUP_IRQn;`
`FLASH_IRQn;`
`RCC_IRQn;`
`EXTI0_IRQn;`
`EXTI1_IRQn;`
`EXTI2_IRQn;`
`EXTI3_IRQn;`
`EXTI4_IRQn;`
`DMA1_Stream0_IRQn;`
`DMA1_Stream1_IRQn;`
`DMA1_Stream2_IRQn;`
`DMA1_Stream3_IRQn;`
`DMA1_Stream4_IRQn;`
`DMA1_Stream5_IRQn;`
`DMA1_Stream6_IRQn;`
`ADC_IRQn;`
`EXTI9_5_IRQn;`
`TIM1_BRK_TIM9_IRQn;`
`TIM1_UP_TIM10_IRQn;`
`TIM1_TRG_COM_TIM11_IRQn;`
`TIM1_CC_IRQn;`
`TIM2_IRQn;`
`TIM3_IRQn;`
`TIM4_IRQn;`
`I2C1_EV_IRQn;`
`I2C1_ER_IRQn;`
`I2C2_EV_IRQn;`
`I2C2_ER_IRQn;`
`SPI1_IRQn;`
`SPI2_IRQn;`
`USART1_IRQn;`
`USART2_IRQn;`
`EXTI15_10_IRQn;`
`RTC_Alarm_IRQn;`
`OTG_FS_WKUP_IRQn;`
`DMA1_Stream7_IRQn;`
`SDIO_IRQn;`
`TIM5_IRQn;`
`SPI3_IRQn;`
`DMA2_Stream0_IRQn;`
`DMA2_Stream1_IRQn;`
`DMA2_Stream2_IRQn;`
`DMA2_Stream3_IRQn;`
`DMA2_Stream4_IRQn;`
`OTG_FS_IRQn;`
`DMA2_Stream5_IRQn;`
`DMA2_Stream6_IRQn;`
`DMA2_Stream7_IRQn;`
`USART6_IRQn;`
`I2C3_EV_IRQn;`
`I2C3_ER_IRQn;`
`FPU_IRQn;`
`SPI4_IRQn;`
`IRQn_MAX;`
`}`

Typedef ADC_TypeDef

* @brief Analog to Digital Converter

typedef struct {...} ADC_TypeDef

`struct`
`{`
`volatile uint32_t SR;`
`volatile uint32_t CR1;`
`volatile uint32_t CR2;`
`volatile uint32_t SMPR1;`
`volatile uint32_t SMPR2;`
`volatile uint32_t JOFR1;`
`volatile uint32_t JOFR2;`
`volatile uint32_t JOFR3;`
`volatile uint32_t JOFR4;`
`volatile uint32_t HTR;`
`volatile uint32_t LTR;`
`volatile uint32_t SQR1;`
`volatile uint32_t SQR2;`
`volatile uint32_t SQR3;`
`volatile uint32_t JSQR;`
`volatile uint32_t JDR1;`
`volatile uint32_t JDR2;`
`volatile uint32_t JDR3;`
`volatile uint32_t JDR4;`
`volatile uint32_t DR;`
`}`

Typedef ADC_Common_TypeDef

typedef struct {...} ADC_Common_TypeDef

`struct`
`{`
`volatile uint32_t CSR;`
`volatile uint32_t CCR;`
`volatile uint32_t CDR;`
`}`

Typedef CRC_TypeDef

* @brief CRC calculation unit

typedef struct {...} CRC_TypeDef

`struct`
`{`
`volatile uint32_t DR;`
`volatile uint8_t IDR;`
`uint8_t RESERVED0;`
`uint16_t RESERVED1;`
`volatile uint32_t CR;`
`}`

Typedef DBGMCU_TypeDef

* @brief Debug MCU

typedef struct {...} DBGMCU_TypeDef

`struct`
`{`
`volatile uint32_t IDCODE;`
`volatile uint32_t CR;`
`volatile uint32_t APB1FZ;`
`volatile uint32_t APB2FZ;`
`}`

Typedef DMA_Stream_TypeDef

* @brief DMA Controller

typedef struct {...} DMA_Stream_TypeDef

`struct`
`{`
`volatile uint32_t CR;`
`volatile uint32_t NDTR;`
`volatile uint32_t PAR;`
`volatile uint32_t M0AR;`
`volatile uint32_t M1AR;`
`volatile uint32_t FCR;`
`}`

Typedef DMA_TypeDef

typedef struct {...} DMA_TypeDef

`struct`
`{`
`volatile uint32_t LISR;`
`volatile uint32_t HISR;`
`volatile uint32_t LIFCR;`
`volatile uint32_t HIFCR;`
`}`

Typedef EXTI_TypeDef

* @brief External Interrupt/Event Controller

typedef struct {...} EXTI_TypeDef

`struct`
`{`
`volatile uint32_t IMR;`
`volatile uint32_t EMR;`
`volatile uint32_t RTSR;`
`volatile uint32_t FTSR;`
`volatile uint32_t SWIER;`
`volatile uint32_t PR;`
`}`

Typedef FLASH_TypeDef

* @brief FLASH Registers

typedef struct {...} FLASH_TypeDef

`struct`
`{`
`volatile uint32_t ACR;`
`volatile uint32_t KEYR;`
`volatile uint32_t OPTKEYR;`
`volatile uint32_t SR;`
`volatile uint32_t CR;`
`volatile uint32_t OPTCR;`
`volatile uint32_t OPTCR1;`
`}`

Typedef GPIO_TypeDef

* @brief General Purpose I/O

typedef struct {...} GPIO_TypeDef

`struct`
`{`
`volatile uint32_t MODER;`
`volatile uint32_t OTYPER;`
`volatile uint32_t OSPEEDR;`
`volatile uint32_t PUPDR;`
`volatile uint32_t IDR;`
`volatile uint32_t ODR;`
`volatile uint16_t BSRRL;`
`volatile uint16_t BSRRH;`
`volatile uint32_t LCKR;`
`volatile uint32_t AFR[2];`
`}`

Typedef SYSCFG_TypeDef

* @brief System configuration controller

typedef struct {...} SYSCFG_TypeDef

`struct`
`{`
`volatile uint32_t MEMRMP;`
`volatile uint32_t PMC;`
`volatile uint32_t EXTICR[4];`
`uint32_t RESERVED[2];`
`volatile uint32_t CMPCR;`
`}`

Typedef I2C_TypeDef

* @brief Inter-integrated Circuit Interface

typedef struct {...} I2C_TypeDef

`struct`
`{`
`volatile uint32_t CR1;`
`volatile uint32_t CR2;`
`volatile uint32_t OAR1;`
`volatile uint32_t OAR2;`
`volatile uint32_t DR;`
`volatile uint32_t SR1;`
`volatile uint32_t SR2;`
`volatile uint32_t CCR;`
`volatile uint32_t TRISE;`
`volatile uint32_t FLTR;`
`}`

Typedef IWDG_TypeDef

* @brief Independent WATCHDOG

typedef struct {...} IWDG_TypeDef

`struct`
`{`
`volatile uint32_t KR;`
`volatile uint32_t PR;`
`volatile uint32_t RLR;`
`volatile uint32_t SR;`
`}`

Typedef PWR_TypeDef

* @brief Power Control

typedef struct {...} PWR_TypeDef

`struct`
`{`
`volatile uint32_t CR;`
`volatile uint32_t CSR;`
`}`

Typedef RCC_TypeDef

* @brief Reset and Clock Control

typedef struct {...} RCC_TypeDef

`struct`
`{`
`volatile uint32_t CR;`
`volatile uint32_t PLLCFGR;`
`volatile uint32_t CFGR;`
`volatile uint32_t CIR;`
`volatile uint32_t AHB1RSTR;`
`volatile uint32_t AHB2RSTR;`
`volatile uint32_t AHB3RSTR;`
`uint32_t RESERVED0;`
`volatile uint32_t APB1RSTR;`
`volatile uint32_t APB2RSTR;`
`uint32_t RESERVED1[2];`
`volatile uint32_t AHB1ENR;`
`volatile uint32_t AHB2ENR;`
`volatile uint32_t AHB3ENR;`
`uint32_t RESERVED2;`
`volatile uint32_t APB1ENR;`
`volatile uint32_t APB2ENR;`
`uint32_t RESERVED3[2];`
`volatile uint32_t AHB1LPENR;`
`volatile uint32_t AHB2LPENR;`
`volatile uint32_t AHB3LPENR;`
`uint32_t RESERVED4;`
`volatile uint32_t APB1LPENR;`
`volatile uint32_t APB2LPENR;`
`uint32_t RESERVED5[2];`
`volatile uint32_t BDCR;`
`volatile uint32_t CSR;`
`uint32_t RESERVED6[2];`
`volatile uint32_t SSCGR;`
`volatile uint32_t PLLI2SCFGR;`
`}`

Typedef RTC_TypeDef

* @brief Real-Time Clock

typedef struct {...} RTC_TypeDef

`struct`
`{`
`volatile uint32_t TR;`
`volatile uint32_t DR;`
`volatile uint32_t CR;`
`volatile uint32_t ISR;`
`volatile uint32_t PRER;`
`volatile uint32_t WUTR;`
`volatile uint32_t CALIBR;`
`volatile uint32_t ALRMAR;`
`volatile uint32_t ALRMBR;`
`volatile uint32_t WPR;`
`volatile uint32_t SSR;`
`volatile uint32_t SHIFTR;`
`volatile uint32_t TSTR;`
`volatile uint32_t TSDR;`
`volatile uint32_t TSSSR;`
`volatile uint32_t CALR;`
`volatile uint32_t TAFCR;`
`volatile uint32_t ALRMASSR;`
`volatile uint32_t ALRMBSSR;`
`uint32_t RESERVED7;`
`volatile uint32_t BKP0R;`
`volatile uint32_t BKP1R;`
`volatile uint32_t BKP2R;`
`volatile uint32_t BKP3R;`
`volatile uint32_t BKP4R;`
`volatile uint32_t BKP5R;`
`volatile uint32_t BKP6R;`
`volatile uint32_t BKP7R;`
`volatile uint32_t BKP8R;`
`volatile uint32_t BKP9R;`
`volatile uint32_t BKP10R;`
`volatile uint32_t BKP11R;`
`volatile uint32_t BKP12R;`
`volatile uint32_t BKP13R;`
`volatile uint32_t BKP14R;`
`volatile uint32_t BKP15R;`
`volatile uint32_t BKP16R;`
`volatile uint32_t BKP17R;`
`volatile uint32_t BKP18R;`
`volatile uint32_t BKP19R;`
`}`

Typedef SDIO_TypeDef

* @brief SD host Interface

typedef struct {...} SDIO_TypeDef

`struct`
`{`
`volatile uint32_t POWER;`
`volatile uint32_t CLKCR;`
`volatile uint32_t ARG;`
`volatile uint32_t CMD;`
`volatile const uint32_t RESPCMD;`
`volatile const uint32_t RESP1;`
`volatile const uint32_t RESP2;`
`volatile const uint32_t RESP3;`
`volatile const uint32_t RESP4;`
`volatile uint32_t DTIMER;`
`volatile uint32_t DLEN;`
`volatile uint32_t DCTRL;`
`volatile const uint32_t DCOUNT;`
`volatile const uint32_t STA;`
`volatile uint32_t ICR;`
`volatile uint32_t MASK;`
`uint32_t RESERVED0[2];`
`volatile const uint32_t FIFOCNT;`
`uint32_t RESERVED1[13];`
`volatile uint32_t FIFO;`
`}`

Typedef SPI_TypeDef

* @brief Serial Peripheral Interface

typedef struct {...} SPI_TypeDef

`struct`
`{`
`volatile uint32_t CR1;`
`volatile uint32_t CR2;`
`volatile uint32_t SR;`
`volatile uint32_t DR;`
`volatile uint32_t CRCPR;`
`volatile uint32_t RXCRCR;`
`volatile uint32_t TXCRCR;`
`volatile uint32_t I2SCFGR;`
`volatile uint32_t I2SPR;`
`}`

Typedef TIM_TypeDef

* @brief TIM

typedef struct {...} TIM_TypeDef

`struct`
`{`
`volatile uint32_t CR1;`
`volatile uint32_t CR2;`
`volatile uint32_t SMCR;`
`volatile uint32_t DIER;`
`volatile uint32_t SR;`
`volatile uint32_t EGR;`
`volatile uint32_t CCMR1;`
`volatile uint32_t CCMR2;`
`volatile uint32_t CCER;`
`volatile uint32_t CNT;`
`volatile uint32_t PSC;`
`volatile uint32_t ARR;`
`volatile uint32_t RCR;`
`volatile uint32_t CCR1;`
`volatile uint32_t CCR2;`
`volatile uint32_t CCR3;`
`volatile uint32_t CCR4;`
`volatile uint32_t BDTR;`
`volatile uint32_t DCR;`
`volatile uint32_t DMAR;`
`volatile uint32_t OR;`
`}`

Typedef USART_TypeDef

* @brief Universal Synchronous Asynchronous Receiver Transmitter

typedef struct {...} USART_TypeDef

`struct`
`{`
`volatile uint32_t SR;`
`volatile uint32_t DR;`
`volatile uint32_t BRR;`
`volatile uint32_t CR1;`
`volatile uint32_t CR2;`
`volatile uint32_t CR3;`
`volatile uint32_t GTPR;`
`}`

Typedef WWDG_TypeDef

* @brief Window WATCHDOG

typedef struct {...} WWDG_TypeDef

`struct`
`{`
`volatile uint32_t CR;`
`volatile uint32_t CFR;`
`volatile uint32_t SR;`
`}`

Typedef RNG_TypeDef

* @brief RNG

typedef struct {...} RNG_TypeDef

`struct`
`{`
`volatile uint32_t CR;`
`volatile uint32_t SR;`
`volatile uint32_t DR;`
`}`

Typedef USB_OTG_GlobalTypeDef

* @brief __USB_OTG_Core_register

typedef struct {...} USB_OTG_GlobalTypeDef

`struct`
`{`
`volatile uint32_t GOTGCTL;`
`volatile uint32_t GOTGINT;`
`volatile uint32_t GAHBCFG;`
`volatile uint32_t GUSBCFG;`
`volatile uint32_t GRSTCTL;`
`volatile uint32_t GINTSTS;`
`volatile uint32_t GINTMSK;`
`volatile uint32_t GRXSTSR;`
`volatile uint32_t GRXSTSP;`
`volatile uint32_t GRXFSIZ;`
`volatile uint32_t DIEPTXF0_HNPTXFSIZ;`
`volatile uint32_t HNPTXSTS;`
`uint32_t Reserved30[2];`
`volatile uint32_t GCCFG;`
`volatile uint32_t CID;`
`uint32_t Reserved40[48];`
`volatile uint32_t HPTXFSIZ;`
`volatile uint32_t DIEPTXF[0x0F];`
`}`

Typedef USB_OTG_DeviceTypeDef

* @brief __device_Registers

typedef struct {...} USB_OTG_DeviceTypeDef

`struct`
`{`
`volatile uint32_t DCFG;`
`volatile uint32_t DCTL;`
`volatile uint32_t DSTS;`
`uint32_t Reserved0C;`
`volatile uint32_t DIEPMSK;`
`volatile uint32_t DOEPMSK;`
`volatile uint32_t DAINT;`
`volatile uint32_t DAINTMSK;`
`uint32_t Reserved20;`
`uint32_t Reserved9;`
`volatile uint32_t DVBUSDIS;`
`volatile uint32_t DVBUSPULSE;`
`volatile uint32_t DTHRCTL;`
`volatile uint32_t DIEPEMPMSK;`
`volatile uint32_t DEACHINT;`
`volatile uint32_t DEACHMSK;`
`uint32_t Reserved40;`
`volatile uint32_t DINEP1MSK;`
`uint32_t Reserved44[15];`
`volatile uint32_t DOUTEP1MSK;`
`}`

Typedef USB_OTG_INEndpointTypeDef

* @brief __IN_Endpoint-Specific_Register

typedef struct {...} USB_OTG_INEndpointTypeDef

`struct`
`{`
`volatile uint32_t DIEPCTL;`
`uint32_t Reserved04;`
`volatile uint32_t DIEPINT;`
`uint32_t Reserved0C;`
`volatile uint32_t DIEPTSIZ;`
`volatile uint32_t DIEPDMA;`
`volatile uint32_t DTXFSTS;`
`uint32_t Reserved18;`
`}`

Typedef USB_OTG_OUTEndpointTypeDef

* @brief __OUT_Endpoint-Specific_Registers

typedef struct {...} USB_OTG_OUTEndpointTypeDef

`struct`
`{`
`volatile uint32_t DOEPCTL;`
`uint32_t Reserved04;`
`volatile uint32_t DOEPINT;`
`uint32_t Reserved0C;`
`volatile uint32_t DOEPTSIZ;`
`volatile uint32_t DOEPDMA;`
`uint32_t Reserved18[2];`
`}`

Typedef USB_OTG_HostTypeDef

* @brief __Host_Mode_Register_Structures

typedef struct {...} USB_OTG_HostTypeDef

`struct`
`{`
`volatile uint32_t HCFG;`
`volatile uint32_t HFIR;`
`volatile uint32_t HFNUM;`
`uint32_t Reserved40C;`
`volatile uint32_t HPTXSTS;`
`volatile uint32_t HAINT;`
`volatile uint32_t HAINTMSK;`
`}`

Typedef USB_OTG_HostChannelTypeDef

* @brief __Host_Channel_Specific_Registers

typedef struct {...} USB_OTG_HostChannelTypeDef

`struct`
`{`
`volatile uint32_t HCCHAR;`
`volatile uint32_t HCSPLT;`
`volatile uint32_t HCINT;`
`volatile uint32_t HCINTMSK;`
`volatile uint32_t HCTSIZ;`
`volatile uint32_t HCDMA;`
`uint32_t Reserved[2];`
`}`