File nut/include/arch/cm3/stm/stm32l1xx_rcc.h

(C) COPYRIGHT STMicroelectronics *****END OF FILE

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Preprocessor definitions

****************************************************************************** * @file stm32l1xx_rcc.h * @author MCD Application Team * @version V1.1.1 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the RCC * firmware library. ****************************************************************************** * @attention * * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ******************************************************************************

#define __STM32L1xx_RCC_H

@defgroup RCC_HSE_configuration * @{

#define RCC_HSE_OFF

#define RCC_HSE_ON

#define RCC_HSE_Bypass

#define IS_RCC_HSE( HSE )

@defgroup RCC_MSI_Clock_Range * @{

#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0

#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1

#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2

#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3

#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4

#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5

#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6

#define IS_RCC_MSI_CLOCK_RANGE( RANGE )

@defgroup RCC_PLL_Clock_Source * @{

#define RCC_PLLSource_HSI

#define RCC_PLLSource_HSE

#define IS_RCC_PLL_SOURCE( SOURCE )

@defgroup RCC_PLL_Multiplication_Factor * @{

#define RCC_PLLMul_3

#define RCC_PLLMul_4

#define RCC_PLLMul_6

#define RCC_PLLMul_8

#define RCC_PLLMul_12

#define RCC_PLLMul_16

#define RCC_PLLMul_24

#define RCC_PLLMul_32

#define RCC_PLLMul_48

#define IS_RCC_PLL_MUL( MUL )

@defgroup RCC_PLL_Divider_Factor * @{

#define RCC_PLLDiv_2

#define RCC_PLLDiv_3

#define RCC_PLLDiv_4

#define IS_RCC_PLL_DIV( DIV )

@defgroup RCC_System_Clock_Source * @{

#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI

#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI

#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE

#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL

#define IS_RCC_SYSCLK_SOURCE( SOURCE )

@defgroup RCC_AHB_Clock_Source * @{

#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1

#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2

#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4

#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8

#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16

#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64

#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128

#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256

#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512

#define IS_RCC_HCLK( HCLK )

@defgroup RCC_APB1_APB2_Clock_Source * @{

#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1

#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2

#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4

#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8

#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16

#define IS_RCC_PCLK( PCLK )

@defgroup RCC_Interrupt_Source * @{

#define RCC_IT_LSIRDY

#define RCC_IT_LSERDY

#define RCC_IT_HSIRDY

#define RCC_IT_HSERDY

#define RCC_IT_PLLRDY

#define RCC_IT_MSIRDY

#define RCC_IT_LSECSS

#define RCC_IT_CSS

#define IS_RCC_IT( IT )

#define IS_RCC_GET_IT( IT )

#define IS_RCC_CLEAR_IT( IT )

@defgroup RCC_LSE_Configuration * @{

#define RCC_LSE_OFF

#define RCC_LSE_ON

#define RCC_LSE_Bypass

#define IS_RCC_LSE( LSE )

@defgroup RCC_RTC_Clock_Source * @{

#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE

#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI

#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE

#define RCC_RTCCLKSource_HSE_Div4

#define RCC_RTCCLKSource_HSE_Div8

#define RCC_RTCCLKSource_HSE_Div16

#define IS_RCC_RTCCLK_SOURCE( SOURCE )

@defgroup RCC_AHB_Peripherals * @{

#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN

#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN

#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN

#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN

#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN

#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN

#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN

#define RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN

#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN

#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN

#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN

#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN

#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN

#define RCC_AHBPeriph_AES RCC_AHBENR_AESEN

#define RCC_AHBPeriph_FSMC RCC_AHBENR_FSMCEN

#define IS_RCC_AHB_PERIPH( PERIPH )

#define IS_RCC_AHB_LPMODE_PERIPH( PERIPH )

@defgroup RCC_APB2_Peripherals * @{

#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN

#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN

#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN

#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN

#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN

#define RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN

#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN

#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN

#define IS_RCC_APB2_PERIPH( PERIPH )

@defgroup RCC_APB1_Peripherals * @{

#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN

#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN

#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN

#define RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN

#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN

#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN

#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN

#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN

#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN

#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN

#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN

#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN

#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN

#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN

#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN

#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN

#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN

#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN

#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN

#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN

#define IS_RCC_APB1_PERIPH( PERIPH )

@defgroup RCC_MCO_Clock_Source * @{

#define RCC_MCOSource_NoClock

#define RCC_MCOSource_SYSCLK

#define RCC_MCOSource_HSI

#define RCC_MCOSource_MSI

#define RCC_MCOSource_HSE

#define RCC_MCOSource_PLLCLK

#define RCC_MCOSource_LSI

#define RCC_MCOSource_LSE

#define IS_RCC_MCO_SOURCE( SOURCE )

@defgroup RCC_MCO_Output_Divider * @{

#define RCC_MCODiv_1

#define RCC_MCODiv_2

#define RCC_MCODiv_4

#define RCC_MCODiv_8

#define RCC_MCODiv_16

#define IS_RCC_MCO_DIV( DIV )

@defgroup RCC_Flag * @{

#define RCC_FLAG_HSIRDY

#define RCC_FLAG_MSIRDY

#define RCC_FLAG_HSERDY

#define RCC_FLAG_PLLRDY

#define RCC_FLAG_LSERDY

#define RCC_FLAG_LSECSS

#define RCC_FLAG_LSIRDY

#define RCC_FLAG_OBLRST

#define RCC_FLAG_PINRST

#define RCC_FLAG_PORRST

#define RCC_FLAG_SFTRST

#define RCC_FLAG_IWDGRST

#define RCC_FLAG_WWDGRST

#define RCC_FLAG_LPWRRST

#define IS_RCC_FLAG( FLAG )

#define IS_RCC_HSI_CALIBRATION_VALUE( VALUE )

#define IS_RCC_MSI_CALIBRATION_VALUE( VALUE )

Typedef RCC_ClocksTypeDef

@addtogroup RCC * @{

typedef struct {...} RCC_ClocksTypeDef

struct  
   {  
      uint32_t SYSCLK_Frequency;  
      uint32_t HCLK_Frequency;  
      uint32_t PCLK1_Frequency;  
      uint32_t PCLK2_Frequency;  
   }