File nut/arch/cm3/dev/stm/stm32f2xx_rcc.c

(C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE

Included Files

****************************************************************************** * @file stm32f2xx_rcc.c * @author MCD Application Team * @version V1.0.0 * @date 18-April-2011 * @brief This file provides firmware functions to manage the following * functionalities of the Reset and clock control (RCC) peripheral: * - Internal/external clocks, PLL, CSS and MCO configuration * - System, AHB and APB busses clocks configuration * - Peripheral clocks configuration * - Interrupts and flags management * * @verbatim * * =================================================================== * RCC specific features * =================================================================== * * After reset the device is running from Internal High Speed oscillator * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache * and I-Cache are disabled, and all peripherals are off except internal * SRAM, Flash and JTAG. * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; * all peripherals mapped on these busses are running at HSI speed. * - The clock for all peripherals is switched off, except the SRAM and FLASH. * - All GPIOs are in input floating state, except the JTAG pins which * are assigned to be used for debug purpose. * * Once the device started from reset, the user application has to: * - Configure the clock source to be used to drive the System clock * (if the application needs higher frequency/performance) * - Configure the System clock frequency and Flash settings * - Configure the AHB and APB busses prescalers * - Enable the clock for the peripheral(s) to be used * - Configure the clock source(s) for peripherals which clocks are not * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) * * @endverbatim * ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2> ******************************************************************************

Preprocessor definitions

#define assert_param NUTASSERT

@defgroup RCC * @brief RCC driver modules * @{

#define RCC_OFFSET

#define CR_OFFSET

#define HSION_BitNumber 0x00

#define CR_HSION_BB

#define CSSON_BitNumber 0x13

#define CR_CSSON_BB

#define PLLON_BitNumber 0x18

#define CR_PLLON_BB

#define PLLI2SON_BitNumber 0x1A

#define CR_PLLI2SON_BB

#define CFGR_OFFSET

#define I2SSRC_BitNumber 0x17

#define CFGR_I2SSRC_BB

#define BDCR_OFFSET

#define RTCEN_BitNumber 0x0F

#define BDCR_RTCEN_BB

#define BDRST_BitNumber 0x10

#define BDCR_BDRST_BB

#define CSR_OFFSET

#define LSION_BitNumber 0x00

#define CSR_LSION_BB

#define CFGR_MCO2_RESET_MASK

#define CFGR_MCO1_RESET_MASK

#define FLAG_MASK

#define CR_BYTE3_ADDRESS

#define CIR_BYTE2_ADDRESS

#define CIR_BYTE3_ADDRESS

#define BDCR_ADDRESS

Local Variables

APBAHBPrescTable
static const uint8_t APBAHBPrescTable[16]
Used in: RCC_GetClocksFreq()  

Global Function RCC_AHB1PeriphClockCmd()

* @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock * @arg RCC_AHB1Periph_GPIOF: GPIOF clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_AHB1PeriphClockCmd ( uint32_t RCC_AHB1Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_AHB1PeriphClockLPModeCmd()

* @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock * @arg RCC_AHB1Periph_GPIOF: GPIOF clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_AHB1PeriphClockLPModeCmd ( uint32_t RCC_AHB1Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_AHB1PeriphResetCmd()

* @brief Forces or releases AHB1 peripheral reset. * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock * @arg RCC_AHB1Periph_GPIOF: GPIOF clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock * * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_AHB1PeriphResetCmd ( uint32_t RCC_AHB1Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_AHB2PeriphClockCmd()

* @brief Enables or disables the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB2Periph_DCMI: DCMI clock * @arg RCC_AHB2Periph_CRYP: CRYP clock * @arg RCC_AHB2Periph_HASH: HASH clock * @arg RCC_AHB2Periph_RNG: RNG clock * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_AHB2PeriphClockCmd ( uint32_t RCC_AHB2Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_AHB2PeriphClockLPModeCmd()

* @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB2Periph_DCMI: DCMI clock * @arg RCC_AHB2Periph_CRYP: CRYP clock * @arg RCC_AHB2Periph_HASH: HASH clock * @arg RCC_AHB2Periph_RNG: RNG clock * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_AHB2PeriphClockLPModeCmd ( uint32_t RCC_AHB2Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_AHB2PeriphResetCmd()

* @brief Forces or releases AHB2 peripheral reset. * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_AHB2Periph_DCMI: DCMI clock * @arg RCC_AHB2Periph_CRYP: CRYP clock * @arg RCC_AHB2Periph_HASH: HASH clock * @arg RCC_AHB2Periph_RNG: RNG clock * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_AHB2PeriphResetCmd ( uint32_t RCC_AHB2Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_AHB3PeriphClockCmd()

* @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. * This parameter must be: RCC_AHB3Periph_FSMC * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_AHB3PeriphClockCmd ( uint32_t RCC_AHB3Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_AHB3PeriphClockLPModeCmd()

* @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. * This parameter must be: RCC_AHB3Periph_FSMC * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_AHB3PeriphClockLPModeCmd ( uint32_t RCC_AHB3Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_AHB3PeriphResetCmd()

* @brief Forces or releases AHB3 peripheral reset. * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. * This parameter must be: RCC_AHB3Periph_FSMC * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_AHB3PeriphResetCmd ( uint32_t RCC_AHB3Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_APB1PeriphClockCmd()

* @brief Enables or disables the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB1Periph_TIM2: TIM2 clock * @arg RCC_APB1Periph_TIM3: TIM3 clock * @arg RCC_APB1Periph_TIM4: TIM4 clock * @arg RCC_APB1Periph_TIM5: TIM5 clock * @arg RCC_APB1Periph_TIM6: TIM6 clock * @arg RCC_APB1Periph_TIM7: TIM7 clock * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock * @arg RCC_APB1Periph_UART5: UART5 clock * @arg RCC_APB1Periph_I2C1: I2C1 clock * @arg RCC_APB1Periph_I2C2: I2C2 clock * @arg RCC_APB1Periph_I2C3: I2C3 clock * @arg RCC_APB1Periph_CAN1: CAN1 clock * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_APB1PeriphClockCmd ( uint32_t RCC_APB1Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_APB1PeriphClockLPModeCmd()

* @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB1Periph_TIM2: TIM2 clock * @arg RCC_APB1Periph_TIM3: TIM3 clock * @arg RCC_APB1Periph_TIM4: TIM4 clock * @arg RCC_APB1Periph_TIM5: TIM5 clock * @arg RCC_APB1Periph_TIM6: TIM6 clock * @arg RCC_APB1Periph_TIM7: TIM7 clock * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock * @arg RCC_APB1Periph_UART5: UART5 clock * @arg RCC_APB1Periph_I2C1: I2C1 clock * @arg RCC_APB1Periph_I2C2: I2C2 clock * @arg RCC_APB1Periph_I2C3: I2C3 clock * @arg RCC_APB1Periph_CAN1: CAN1 clock * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_APB1PeriphClockLPModeCmd ( uint32_t RCC_APB1Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_APB1PeriphResetCmd()

* @brief Forces or releases Low Speed APB (APB1) peripheral reset. * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_APB1Periph_TIM2: TIM2 clock * @arg RCC_APB1Periph_TIM3: TIM3 clock * @arg RCC_APB1Periph_TIM4: TIM4 clock * @arg RCC_APB1Periph_TIM5: TIM5 clock * @arg RCC_APB1Periph_TIM6: TIM6 clock * @arg RCC_APB1Periph_TIM7: TIM7 clock * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock * @arg RCC_APB1Periph_UART5: UART5 clock * @arg RCC_APB1Periph_I2C1: I2C1 clock * @arg RCC_APB1Periph_I2C2: I2C2 clock * @arg RCC_APB1Periph_I2C3: I2C3 clock * @arg RCC_APB1Periph_CAN1: CAN1 clock * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_APB1PeriphResetCmd ( uint32_t RCC_APB1Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_APB2PeriphClockCmd()

* @brief Enables or disables the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB2Periph_TIM1: TIM1 clock * @arg RCC_APB2Periph_TIM8: TIM8 clock * @arg RCC_APB2Periph_USART1: USART1 clock * @arg RCC_APB2Periph_USART6: USART6 clock * @arg RCC_APB2Periph_ADC1: ADC1 clock * @arg RCC_APB2Periph_ADC2: ADC2 clock * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_APB2PeriphClockCmd ( uint32_t RCC_APB2Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_APB2PeriphClockLPModeCmd()

* @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB2Periph_TIM1: TIM1 clock * @arg RCC_APB2Periph_TIM8: TIM8 clock * @arg RCC_APB2Periph_USART1: USART1 clock * @arg RCC_APB2Periph_USART6: USART6 clock * @arg RCC_APB2Periph_ADC1: ADC1 clock * @arg RCC_APB2Periph_ADC2: ADC2 clock * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_APB2PeriphClockLPModeCmd ( uint32_t RCC_APB2Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_APB2PeriphResetCmd()

* @brief Forces or releases High Speed APB (APB2) peripheral reset. * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_APB2Periph_TIM1: TIM1 clock * @arg RCC_APB2Periph_TIM8: TIM8 clock * @arg RCC_APB2Periph_USART1: USART1 clock * @arg RCC_APB2Periph_USART6: USART6 clock * @arg RCC_APB2Periph_ADC1: ADC1 clock * @arg RCC_APB2Periph_ADC2: ADC2 clock * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_APB2PeriphResetCmd ( uint32_t RCC_APB2Periph, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_AdjustHSICalibrationValue()

* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. * @param HSICalibrationValue: specifies the calibration trimming value. * This parameter must be a number between 0 and 0x1F. * @retval None

void RCC_AdjustHSICalibrationValue ( uint8_t HSICalibrationValue )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_BackupResetCmd()

* @brief Forces or releases the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_CSR register. * @note The BKPSRAM is not affected by this reset. * @param NewState: new state of the Backup domain reset. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_BackupResetCmd ( FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_ClearFlag()

* @brief Clears the RCC reset flags. * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST * @param None * @retval None

void RCC_ClearFlag ( void )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_ClearITPendingBit()

* @brief Clears the RCC's interrupt pending bits. * @param RCC_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt * @arg RCC_IT_LSERDY: LSE ready interrupt * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt * @arg RCC_IT_CSS: Clock Security System interrupt * @retval None

void RCC_ClearITPendingBit ( uint8_t RCC_IT )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_ClockSecuritySystemCmd()

* @brief Enables or disables the Clock Security System. * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), * allowing the MCU to perform rescue operations. The CSSI is linked to * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. * @param NewState: new state of the Clock Security System. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_ClockSecuritySystemCmd ( FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_DeInit()

* @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE, PLL and PLLI2S OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @param None * @retval None

void RCC_DeInit ( void )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_GetClocksFreq()

* @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, * PCLK1 and PCLK2. * * @note The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * @note (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * @note The result of this function could be not correct when using fractional * value for HSE crystal. * * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold * the clocks frequencies. * * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function * must be called to update the structure's field. Otherwise, any * configuration based on this function will be incorrect. * * @retval None

void RCC_GetClocksFreq ( RCC_ClocksTypeDef* RCC_Clocks )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h
References Variables: APBAHBPrescTable nut/arch/cm3/dev/stm/stm32f2xx_rcc.c

Global Function RCC_GetFlagStatus()

* @brief Checks whether the specified RCC flag is set or not. * @param RCC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready * @arg RCC_FLAG_PLLRDY: main PLL clock ready * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset * @arg RCC_FLAG_PINRST: Pin reset * @arg RCC_FLAG_PORRST: POR/PDR reset * @arg RCC_FLAG_SFTRST: Software reset * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset * @arg RCC_FLAG_WWDGRST: Window Watchdog reset * @arg RCC_FLAG_LPWRRST: Low Power reset * @retval The new state of RCC_FLAG (SET or RESET).

FlagStatus RCC_GetFlagStatus ( uint8_t RCC_FLAG )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h
Called by: RCC_WaitForHSEStartUp() nut/arch/cm3/dev/stm/stm32f2xx_rcc.c

Global Function RCC_GetITStatus()

* @brief Checks whether the specified RCC interrupt has occurred or not. * @param RCC_IT: specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt * @arg RCC_IT_LSERDY: LSE ready interrupt * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt * @arg RCC_IT_CSS: Clock Security System interrupt * @retval The new state of RCC_IT (SET or RESET).

ITStatus RCC_GetITStatus ( uint8_t RCC_IT )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_GetSYSCLKSource()

* @brief Returns the clock source used as system clock. * @param None * @retval The clock source used as system clock. The returned value can be one * of the following: * - 0x00: HSI used as system clock * - 0x04: HSE used as system clock * - 0x08: PLL used as system clock

uint8_t RCC_GetSYSCLKSource ( void )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_HCLKConfig()

* @brief Configures the AHB clock (HCLK). * @note Depending on the device voltage range, the software has to set correctly * these bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above * "CPU, AHB and APB busses clocks configuration functions") * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from * the system clock (SYSCLK). * This parameter can be one of the following values: * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 * @retval None

void RCC_HCLKConfig ( uint32_t RCC_SYSCLK )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_HSEConfig()

* @brief Configures the External High Speed oscillator (HSE). * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the Clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. * @param RCC_HSE: specifies the new state of the HSE. * This parameter can be one of the following values: * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. * @arg RCC_HSE_ON: turn ON the HSE oscillator * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock * @retval None

void RCC_HSEConfig ( uint8_t RCC_HSE )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_HSICmd()

* @brief Enables or disables the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * It is used (enabled by hardware) as system clock source after startup * from Reset, wakeup from STOP and STANDBY mode, or in case of failure * of the HSE used directly or indirectly as system clock (if the Clock * Security System CSS is enabled). * @note HSI can not be stopped if it is used as system clock source. In this case, * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as * system clock source. * @param NewState: new state of the HSI. * This parameter can be: ENABLE or DISABLE. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator * clock cycles. * @retval None

void RCC_HSICmd ( FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_I2SCLKConfig()

* @brief Configures the I2S clock source (I2SCLK). * * @note This function must be called before enabling the I2S APB clock. * @note This function applies only to Silicon RevisionB and RevisionY. * * @param RCC_I2SCLKSource: specifies the I2S clock source. * This parameter can be one of the following values: * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin * used as I2S clock source * @retval None

void RCC_I2SCLKConfig ( uint32_t RCC_I2SCLKSource )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_ITConfig()

* @brief Enables or disables the specified RCC interrupts. * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt * @arg RCC_IT_LSERDY: LSE ready interrupt * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt * @param NewState: new state of the specified RCC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_ITConfig ( uint8_t RCC_IT, FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_LSEConfig()

* @brief Configures the External Low Speed oscillator (LSE). * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. * @param RCC_LSE: specifies the new state of the LSE. * This parameter can be one of the following values: * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. * @arg RCC_LSE_ON: turn ON the LSE oscillator * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock * @retval None

void RCC_LSEConfig ( uint8_t RCC_LSE )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_LSICmd()

* @brief Enables or disables the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. * @note LSI can not be disabled if the IWDG is running. * @param NewState: new state of the LSI. * This parameter can be: ENABLE or DISABLE. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator * clock cycles. * @retval None

void RCC_LSICmd ( FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_MCO1Config()

* @brief Selects the clock source to output on MCO1 pin(PA8). * @note PA8 should be configured in alternate function mode. * @param RCC_MCO1Source: specifies the clock source to output. * This parameter can be one of the following values: * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source * @param RCC_MCO1Div: specifies the MCO1 prescaler. * This parameter can be one of the following values: * @arg RCC_MCO1Div_1: no division applied to MCO1 clock * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock * @retval None

void RCC_MCO1Config ( uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_MCO2Config()

* @brief Selects the clock source to output on MCO2 pin(PC9). * @note PC9 should be configured in alternate function mode. * @param RCC_MCO2Source: specifies the clock source to output. * This parameter can be one of the following values: * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source * @param RCC_MCO2Div: specifies the MCO2 prescaler. * This parameter can be one of the following values: * @arg RCC_MCO2Div_1: no division applied to MCO2 clock * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock * @retval None

void RCC_MCO2Config ( uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_PCLK1Config()

* @brief Configures the Low Speed APB clock (PCLK1). * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from * the AHB clock (HCLK). * This parameter can be one of the following values: * @arg RCC_HCLK_Div1: APB1 clock = HCLK * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 * @retval None

void RCC_PCLK1Config ( uint32_t RCC_HCLK )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_PCLK2Config()

* @brief Configures the High Speed APB clock (PCLK2). * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from * the AHB clock (HCLK). * This parameter can be one of the following values: * @arg RCC_HCLK_Div1: APB2 clock = HCLK * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 * @retval None

void RCC_PCLK2Config ( uint32_t RCC_HCLK )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_PLLCmd()

* @brief Enables or disables the main PLL. * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL can not be disabled if it is used as system clock source * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_PLLCmd ( FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_PLLConfig()

* @brief Configures the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. * * @param RCC_PLLSource: specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. * * @param PLLM: specifies the division factor for PLL VCO input clock * This parameter must be a number between 0 and 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. * * @param PLLN: specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between 192 and 432. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 192 and 432 MHz. * * @param PLLP: specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on * the System clock frequency. * * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks * This parameter must be a number between 4 and 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work * correctly. * * @retval None

void RCC_PLLConfig ( uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_PLLI2SCmd()

* @brief Enables or disables the PLLI2S. * @note PLLI2S is available only in RevisionB and RevisionY * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_PLLI2SCmd ( FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_PLLI2SConfig()

* @brief Configures the PLLI2S clock multiplication and division factors. * * @note PLLI2S is available only in Silicon RevisionB and RevisionY. * @note This function must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between 192 and 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between 192 and 432 MHz. * * @param PLLI2SR: specifies the division factor for I2S clock * This parameter must be a number between 2 and 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * * @retval None

void RCC_PLLI2SConfig ( uint32_t PLLI2SN, uint32_t PLLI2SR )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_RTCCLKCmd()

* @brief Enables or disables the RTC clock. * @note This function must be used only after the RTC clock source was selected * using the RCC_RTCCLKConfig function. * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. * @retval None

void RCC_RTCCLKCmd ( FunctionalState NewState )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_RTCCLKConfig()

* @brief Configures the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using PWR_BackupAccessCmd(ENABLE) function before to configure * the RTC clock source (to be done once after reset). * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using RCC_BackupResetCmd() function, or by * a Power On Reset (POR). * * @param RCC_RTCCLKSource: specifies the RTC clock source. * This parameter can be one of the following values: * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected * as RTC clock, where x:[2,31] * * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). * * @retval None

void RCC_RTCCLKConfig ( uint32_t RCC_RTCCLKSource )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_SYSCLKConfig()

* @brief Configures the system clock (SYSCLK). * @note The HSI is used (enabled by hardware) as system clock source after * startup from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). * @note A switch from one clock source to another occurs only if the target * clock source is ready (clock stable after startup delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will * occur when the clock source will be ready. * You can use RCC_GetSYSCLKSource() function to know which clock is * currently used as system clock source. * @param RCC_SYSCLKSource: specifies the clock source used as system clock. * This parameter can be one of the following values: * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source * @retval None

void RCC_SYSCLKConfig ( uint32_t RCC_SYSCLKSource )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h

Global Function RCC_WaitForHSEStartUp()

* @brief Waits for HSE start-up. * @note This functions waits on HSERDY flag to be set and return SUCCESS if * this flag is set, otherwise returns ERROR if the timeout is reached * and this flag is not set. The timeout value is defined by the constant * HSE_STARTUP_TIMEOUT in stm32f2xx.h file. You can tailor it depending * on the HSE crystal used in your application. * @param None * @retval An ErrorStatus enumeration value: * - SUCCESS: HSE oscillator is stable and ready to use * - ERROR: HSE oscillator not yet ready

ErrorStatus RCC_WaitForHSEStartUp ( void )

Prototyped in: nut/include/arch/cm3/stm/stm32f2xx_rcc.h
Calls: RCC_GetFlagStatus() nut/arch/cm3/dev/stm/stm32f2xx_rcc.c